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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DWC AHCI SATA controller
8
9maintainers:
10 - Serge Semin <fancer.lancer@gmail.com>
11
12description:
13 This document defines device tree bindings for the generic Synopsys DWC
14 implementation of the AHCI SATA controller.
15
16select:
17 properties:
18 compatible:
19 enum:
20 - snps,dwc-ahci
21 - snps,spear-ahci
22 required:
23 - compatible
24
25allOf:
26 - $ref: snps,dwc-ahci-common.yaml#
27
28properties:
29 compatible:
30 oneOf:
31 - description: Synopsys AHCI SATA-compatible devices
32 const: snps,dwc-ahci
33 - description: SPEAr1340 AHCI SATA device
34 const: snps,spear-ahci
35
36 iommus:
37 minItems: 1
38 maxItems: 3
39
40patternProperties:
41 "^sata-port@[0-9a-e]$":
42 $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
43
44 unevaluatedProperties: false
45
46required:
47 - compatible
48 - reg
49 - interrupts
50
51unevaluatedProperties: false
52
53examples:
54 - |
55 #include <dt-bindings/interrupt-controller/arm-gic.h>
56 #include <dt-bindings/ata/ahci.h>
57
58 sata@122f0000 {
59 compatible = "snps,dwc-ahci";
60 reg = <0x122F0000 0x1ff>;
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
65
66 clocks = <&clock1>, <&clock2>;
67 clock-names = "aclk", "ref";
68
69 phys = <&sata_phy>;
70 phy-names = "sata-phy";
71
72 ports-implemented = <0x1>;
73
74 sata-port@0 {
75 reg = <0>;
76
77 hba-port-cap = <HBA_PORT_FBSCP>;
78
79 snps,tx-ts-max = <512>;
80 snps,rx-ts-max = <512>;
81 };
82 };
83
84...