tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2025 Collabora Ltd
4 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
5 */
6
7#ifndef __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H
8#define __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H
9
10#include <linux/soc/mediatek/infracfg.h>
11#include <dt-bindings/power/mediatek,mt6893-power.h>
12#include "mtk-pm-domains.h"
13
14#define MT6893_TOP_AXI_PROT_EN_MCU_STA1 0x2e4
15#define MT6893_TOP_AXI_PROT_EN_MCU_SET 0x2c4
16#define MT6893_TOP_AXI_PROT_EN_MCU_CLR 0x2c8
17#define MT6893_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4
18#define MT6893_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8
19#define MT6893_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0
20#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbb8
21#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbbc
22#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbc4
23
24#define MT6893_TOP_AXI_PROT_EN_1_MFG1_STEP1 GENMASK(21, 19)
25#define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP2 GENMASK(6, 5)
26#define MT6893_TOP_AXI_PROT_EN_MFG1_STEP3 GENMASK(22, 21)
27#define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(7)
28#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP5 GENMASK(19, 17)
29#define MT6893_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(24)
30#define MT6893_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(25)
31#define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(6)
32#define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(7)
33#define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP1 BIT(26)
34#define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP2 BIT(0)
35#define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP3 BIT(27)
36#define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP4 BIT(1)
37#define MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP1 GENMASK(30, 28)
38#define MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP2 GENMASK(31, 29)
39#define MT6893_TOP_AXI_PROT_EN_MDP_STEP1 BIT(10)
40#define MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP2 (BIT(2) | BIT(4) | BIT(6) | \
41 BIT(8) | BIT(18) | BIT(22) | \
42 BIT(28) | BIT(30))
43#define MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP3 (BIT(0) | BIT(2) | BIT(4) | \
44 BIT(6) | BIT(8))
45#define MT6893_TOP_AXI_PROT_EN_MDP_STEP4 BIT(23)
46#define MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP5 (BIT(3) | BIT(5) | BIT(7) | \
47 BIT(9) | BIT(19) | BIT(23) | \
48 BIT(29) | BIT(31))
49#define MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP6 (BIT(1) | BIT(7) | BIT(9) | BIT(11))
50#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MDP_STEP7 BIT(20)
51#define MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP1 (BIT(0) | BIT(6) | BIT(8) | \
52 BIT(10) | BIT(12) | BIT(14) | \
53 BIT(16) | BIT(20) | BIT(24) | \
54 BIT(26))
55#define MT6893_TOP_AXI_PROT_EN_DISP_STEP2 BIT(6)
56#define MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP3 (BIT(1) | BIT(7) | BIT(9) | \
57 BIT(15) | BIT(17) | BIT(21) | \
58 BIT(25) | BIT(27))
59#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_DISP_STEP4 BIT(21)
60#define MT6893_TOP_AXI_PROT_EN_2_ADSP BIT(3)
61#define MT6893_TOP_AXI_PROT_EN_2_CAM_STEP1 BIT(1)
62#define MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP2 (BIT(0) | BIT(2) | BIT(4))
63#define MT6893_TOP_AXI_PROT_EN_1_CAM_STEP3 BIT(22)
64#define MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP4 (BIT(1) | BIT(3) | BIT(5))
65#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP1 BIT(18)
66#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP2 BIT(19)
67#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP1 BIT(20)
68#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP2 BIT(21)
69#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP1 BIT(22)
70#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP2 BIT(23)
71
72/*
73 * MT6893 Power Domain (MTCMOS) support
74 *
75 * The register layout for this IP is very similar to MT8192 so where possible
76 * the same definitions are reused to avoid duplication.
77 * Where the bus protection bits are also the same, the entire set is reused.
78 */
79static const struct scpsys_domain_data scpsys_domain_data_mt6893[] = {
80 [MT6893_POWER_DOMAIN_CONN] = {
81 .name = "conn",
82 .sta_mask = BIT(1),
83 .ctl_offs = 0x304,
84 .pwr_sta_offs = 0x16c,
85 .pwr_sta2nd_offs = 0x170,
86 .sram_pdn_bits = 0,
87 .sram_pdn_ack_bits = 0,
88 .bp_cfg = {
89 BUS_PROT_WR(INFRA,
90 MT8192_TOP_AXI_PROT_EN_CONN,
91 MT8192_TOP_AXI_PROT_EN_SET,
92 MT8192_TOP_AXI_PROT_EN_CLR,
93 MT8192_TOP_AXI_PROT_EN_STA1),
94 BUS_PROT_WR(INFRA,
95 MT8192_TOP_AXI_PROT_EN_CONN_2ND,
96 MT8192_TOP_AXI_PROT_EN_SET,
97 MT8192_TOP_AXI_PROT_EN_CLR,
98 MT8192_TOP_AXI_PROT_EN_STA1),
99 BUS_PROT_WR(INFRA,
100 MT8192_TOP_AXI_PROT_EN_1_CONN,
101 MT8192_TOP_AXI_PROT_EN_1_SET,
102 MT8192_TOP_AXI_PROT_EN_1_CLR,
103 MT8192_TOP_AXI_PROT_EN_1_STA1),
104 },
105 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
106 },
107 [MT6893_POWER_DOMAIN_MFG0] = {
108 .name = "mfg0",
109 .sta_mask = BIT(2),
110 .ctl_offs = 0x308,
111 .pwr_sta_offs = 0x16c,
112 .pwr_sta2nd_offs = 0x170,
113 .sram_pdn_bits = BIT(8),
114 .sram_pdn_ack_bits = BIT(12),
115 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
116 },
117 [MT6893_POWER_DOMAIN_MFG1] = {
118 .name = "mfg1",
119 .sta_mask = BIT(3),
120 .ctl_offs = 0x30c,
121 .pwr_sta_offs = 0x16c,
122 .pwr_sta2nd_offs = 0x170,
123 .sram_pdn_bits = BIT(8),
124 .sram_pdn_ack_bits = BIT(12),
125 .bp_cfg = {
126 BUS_PROT_WR(INFRA,
127 MT6893_TOP_AXI_PROT_EN_1_MFG1_STEP1,
128 MT8192_TOP_AXI_PROT_EN_1_SET,
129 MT8192_TOP_AXI_PROT_EN_1_CLR,
130 MT8192_TOP_AXI_PROT_EN_1_STA1),
131 BUS_PROT_WR(INFRA,
132 MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP2,
133 MT8192_TOP_AXI_PROT_EN_2_SET,
134 MT8192_TOP_AXI_PROT_EN_2_CLR,
135 MT8192_TOP_AXI_PROT_EN_2_STA1),
136 BUS_PROT_WR(INFRA,
137 MT6893_TOP_AXI_PROT_EN_MFG1_STEP3,
138 MT8192_TOP_AXI_PROT_EN_SET,
139 MT8192_TOP_AXI_PROT_EN_CLR,
140 MT8192_TOP_AXI_PROT_EN_STA1),
141 BUS_PROT_WR(INFRA,
142 MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP4,
143 MT8192_TOP_AXI_PROT_EN_2_SET,
144 MT8192_TOP_AXI_PROT_EN_2_CLR,
145 MT8192_TOP_AXI_PROT_EN_2_STA1),
146 BUS_PROT_WR(INFRA,
147 MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP5,
148 MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
149 MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
150 MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
151 },
152 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
153 },
154 [MT6893_POWER_DOMAIN_MFG2] = {
155 .name = "mfg2",
156 .sta_mask = BIT(4),
157 .ctl_offs = 0x310,
158 .pwr_sta_offs = 0x16c,
159 .pwr_sta2nd_offs = 0x170,
160 .sram_pdn_bits = BIT(8),
161 .sram_pdn_ack_bits = BIT(12),
162 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
163 },
164 [MT6893_POWER_DOMAIN_MFG3] = {
165 .name = "mfg3",
166 .sta_mask = BIT(5),
167 .ctl_offs = 0x314,
168 .pwr_sta_offs = 0x16c,
169 .pwr_sta2nd_offs = 0x170,
170 .sram_pdn_bits = BIT(8),
171 .sram_pdn_ack_bits = BIT(12),
172 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
173 },
174 [MT6893_POWER_DOMAIN_MFG4] = {
175 .name = "mfg4",
176 .sta_mask = BIT(6),
177 .ctl_offs = 0x318,
178 .pwr_sta_offs = 0x16c,
179 .pwr_sta2nd_offs = 0x170,
180 .sram_pdn_bits = BIT(8),
181 .sram_pdn_ack_bits = BIT(12),
182 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
183 },
184 [MT6893_POWER_DOMAIN_MFG5] = {
185 .name = "mfg5",
186 .sta_mask = BIT(7),
187 .ctl_offs = 0x31c,
188 .pwr_sta_offs = 0x16c,
189 .pwr_sta2nd_offs = 0x170,
190 .sram_pdn_bits = BIT(8),
191 .sram_pdn_ack_bits = BIT(12),
192 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
193 },
194 [MT6893_POWER_DOMAIN_MFG6] = {
195 .name = "mfg6",
196 .sta_mask = BIT(8),
197 .ctl_offs = 0x320,
198 .pwr_sta_offs = 0x16c,
199 .pwr_sta2nd_offs = 0x170,
200 .sram_pdn_bits = BIT(8),
201 .sram_pdn_ack_bits = BIT(12),
202 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
203 },
204 [MT6893_POWER_DOMAIN_ISP] = {
205 .name = "isp",
206 .sta_mask = BIT(12),
207 .ctl_offs = 0x330,
208 .pwr_sta_offs = 0x16c,
209 .pwr_sta2nd_offs = 0x170,
210 .sram_pdn_bits = BIT(8),
211 .sram_pdn_ack_bits = BIT(12),
212 .bp_cfg = {
213 BUS_PROT_WR(INFRA,
214 MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
215 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
216 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
217 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
218 BUS_PROT_WR(INFRA,
219 MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
220 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
221 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
222 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
223 },
224 },
225 [MT6893_POWER_DOMAIN_ISP2] = {
226 .name = "isp2",
227 .sta_mask = BIT(13),
228 .ctl_offs = 0x334,
229 .pwr_sta_offs = 0x16c,
230 .pwr_sta2nd_offs = 0x170,
231 .sram_pdn_bits = BIT(8),
232 .sram_pdn_ack_bits = BIT(12),
233 .bp_cfg = {
234 BUS_PROT_WR(INFRA,
235 MT8192_TOP_AXI_PROT_EN_MM_ISP2,
236 MT8192_TOP_AXI_PROT_EN_MM_SET,
237 MT8192_TOP_AXI_PROT_EN_MM_CLR,
238 MT8192_TOP_AXI_PROT_EN_MM_STA1),
239 BUS_PROT_WR(INFRA,
240 MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
241 MT8192_TOP_AXI_PROT_EN_MM_SET,
242 MT8192_TOP_AXI_PROT_EN_MM_CLR,
243 MT8192_TOP_AXI_PROT_EN_MM_STA1),
244 },
245 },
246 [MT6893_POWER_DOMAIN_IPE] = {
247 .name = "ipe",
248 .sta_mask = BIT(14),
249 .ctl_offs = 0x338,
250 .pwr_sta_offs = 0x16c,
251 .pwr_sta2nd_offs = 0x170,
252 .sram_pdn_bits = BIT(8),
253 .sram_pdn_ack_bits = BIT(12),
254 .bp_cfg = {
255 BUS_PROT_WR(INFRA,
256 MT8192_TOP_AXI_PROT_EN_MM_IPE,
257 MT8192_TOP_AXI_PROT_EN_MM_SET,
258 MT8192_TOP_AXI_PROT_EN_MM_CLR,
259 MT8192_TOP_AXI_PROT_EN_MM_STA1),
260 BUS_PROT_WR(INFRA,
261 MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
262 MT8192_TOP_AXI_PROT_EN_MM_SET,
263 MT8192_TOP_AXI_PROT_EN_MM_CLR,
264 MT8192_TOP_AXI_PROT_EN_MM_STA1),
265 },
266 },
267 [MT6893_POWER_DOMAIN_VDEC0] = {
268 .name = "vdec0",
269 .sta_mask = BIT(15),
270 .ctl_offs = 0x33c,
271 .pwr_sta_offs = 0x16c,
272 .pwr_sta2nd_offs = 0x170,
273 .sram_pdn_bits = BIT(8),
274 .sram_pdn_ack_bits = BIT(12),
275 .bp_cfg = {
276 BUS_PROT_WR(INFRA,
277 MT6893_TOP_AXI_PROT_EN_MM_VDEC0_STEP1,
278 MT8192_TOP_AXI_PROT_EN_MM_SET,
279 MT8192_TOP_AXI_PROT_EN_MM_CLR,
280 MT8192_TOP_AXI_PROT_EN_MM_STA1),
281 BUS_PROT_WR(INFRA,
282 MT6893_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2,
283 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
284 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
285 MT8192_TOP_AXI_PROT_EN_MM_STA1),
286 },
287 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
288 },
289 [MT6893_POWER_DOMAIN_VDEC1] = {
290 .name = "vdec1",
291 .sta_mask = BIT(16),
292 .ctl_offs = 0x340,
293 .pwr_sta_offs = 0x16c,
294 .pwr_sta2nd_offs = 0x170,
295 .sram_pdn_bits = BIT(8),
296 .sram_pdn_ack_bits = BIT(12),
297 .bp_cfg = {
298 BUS_PROT_WR(INFRA,
299 MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP1,
300 MT8192_TOP_AXI_PROT_EN_MM_SET,
301 MT8192_TOP_AXI_PROT_EN_MM_CLR,
302 MT8192_TOP_AXI_PROT_EN_MM_STA1),
303 BUS_PROT_WR(INFRA,
304 MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP2,
305 MT8192_TOP_AXI_PROT_EN_MM_SET,
306 MT8192_TOP_AXI_PROT_EN_MM_CLR,
307 MT8192_TOP_AXI_PROT_EN_MM_STA1),
308 },
309 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
310 },
311 [MT6893_POWER_DOMAIN_VENC0] = {
312 .name = "venc0",
313 .sta_mask = BIT(17),
314 .ctl_offs = 0x344,
315 .pwr_sta_offs = 0x16c,
316 .pwr_sta2nd_offs = 0x170,
317 .sram_pdn_bits = BIT(8),
318 .sram_pdn_ack_bits = BIT(12),
319 .bp_cfg = {
320 BUS_PROT_WR(INFRA,
321 MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP1,
322 MT8192_TOP_AXI_PROT_EN_MM_SET,
323 MT8192_TOP_AXI_PROT_EN_MM_CLR,
324 MT8192_TOP_AXI_PROT_EN_MM_STA1),
325 BUS_PROT_WR(INFRA,
326 MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP2,
327 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
328 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
329 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
330 BUS_PROT_WR(INFRA,
331 MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP3,
332 MT8192_TOP_AXI_PROT_EN_MM_SET,
333 MT8192_TOP_AXI_PROT_EN_MM_CLR,
334 MT8192_TOP_AXI_PROT_EN_MM_STA1),
335 BUS_PROT_WR(INFRA,
336 MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP4,
337 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
338 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
339 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
340 },
341 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
342 },
343 [MT6893_POWER_DOMAIN_VENC1] = {
344 .name = "venc1",
345 .sta_mask = BIT(18),
346 .ctl_offs = 0x348,
347 .pwr_sta_offs = 0x16c,
348 .pwr_sta2nd_offs = 0x170,
349 .sram_pdn_bits = BIT(8),
350 .sram_pdn_ack_bits = BIT(12),
351 .bp_cfg = {
352 BUS_PROT_WR(INFRA,
353 MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP1,
354 MT8192_TOP_AXI_PROT_EN_MM_SET,
355 MT8192_TOP_AXI_PROT_EN_MM_CLR,
356 MT8192_TOP_AXI_PROT_EN_MM_STA1),
357 BUS_PROT_WR(INFRA,
358 MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP2,
359 MT8192_TOP_AXI_PROT_EN_MM_SET,
360 MT8192_TOP_AXI_PROT_EN_MM_CLR,
361 MT8192_TOP_AXI_PROT_EN_MM_STA1),
362 },
363 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
364 },
365 [MT6893_POWER_DOMAIN_MDP] = {
366 .name = "mdp",
367 .sta_mask = BIT(19),
368 .ctl_offs = 0x34c,
369 .pwr_sta_offs = 0x16c,
370 .pwr_sta2nd_offs = 0x170,
371 .sram_pdn_bits = BIT(8),
372 .sram_pdn_ack_bits = BIT(12),
373 .bp_cfg = {
374 BUS_PROT_WR(INFRA,
375 MT6893_TOP_AXI_PROT_EN_MDP_STEP1,
376 MT8192_TOP_AXI_PROT_EN_SET,
377 MT8192_TOP_AXI_PROT_EN_CLR,
378 MT8192_TOP_AXI_PROT_EN_STA1),
379 BUS_PROT_WR(INFRA,
380 MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP2,
381 MT8192_TOP_AXI_PROT_EN_MM_SET,
382 MT8192_TOP_AXI_PROT_EN_MM_CLR,
383 MT8192_TOP_AXI_PROT_EN_MM_STA1),
384 BUS_PROT_WR(INFRA,
385 MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP3,
386 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
387 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
388 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
389 BUS_PROT_WR(INFRA,
390 MT6893_TOP_AXI_PROT_EN_MDP_STEP4,
391 MT8192_TOP_AXI_PROT_EN_SET,
392 MT8192_TOP_AXI_PROT_EN_CLR,
393 MT8192_TOP_AXI_PROT_EN_STA1),
394 BUS_PROT_WR(INFRA,
395 MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP5,
396 MT8192_TOP_AXI_PROT_EN_MM_SET,
397 MT8192_TOP_AXI_PROT_EN_MM_CLR,
398 MT8192_TOP_AXI_PROT_EN_MM_STA1),
399 BUS_PROT_WR(INFRA,
400 MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP6,
401 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
402 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
403 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
404 BUS_PROT_WR(INFRA,
405 MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MDP_STEP7,
406 MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
407 MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
408 MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
409 },
410 },
411 [MT6893_POWER_DOMAIN_DISP] = {
412 .name = "disp",
413 .sta_mask = BIT(20),
414 .ctl_offs = 0x350,
415 .pwr_sta_offs = 0x16c,
416 .pwr_sta2nd_offs = 0x170,
417 .sram_pdn_bits = BIT(8),
418 .sram_pdn_ack_bits = BIT(12),
419 .bp_cfg = {
420 BUS_PROT_WR(INFRA,
421 MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP1,
422 MT8192_TOP_AXI_PROT_EN_MM_SET,
423 MT8192_TOP_AXI_PROT_EN_MM_CLR,
424 MT8192_TOP_AXI_PROT_EN_MM_STA1),
425 BUS_PROT_WR(INFRA,
426 MT6893_TOP_AXI_PROT_EN_DISP_STEP2,
427 MT8192_TOP_AXI_PROT_EN_SET,
428 MT8192_TOP_AXI_PROT_EN_CLR,
429 MT8192_TOP_AXI_PROT_EN_STA1),
430 BUS_PROT_WR(INFRA,
431 MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP3,
432 MT8192_TOP_AXI_PROT_EN_MM_SET,
433 MT8192_TOP_AXI_PROT_EN_MM_CLR,
434 MT8192_TOP_AXI_PROT_EN_MM_STA1),
435 BUS_PROT_WR(INFRA,
436 MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_DISP_STEP4,
437 MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
438 MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
439 MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
440 },
441 },
442 [MT6893_POWER_DOMAIN_AUDIO] = {
443 .name = "audio",
444 .sta_mask = BIT(21),
445 .ctl_offs = 0x354,
446 .pwr_sta_offs = 0x16c,
447 .pwr_sta2nd_offs = 0x170,
448 .sram_pdn_bits = BIT(8),
449 .sram_pdn_ack_bits = BIT(12),
450 .bp_cfg = {
451 BUS_PROT_WR(INFRA,
452 MT8192_TOP_AXI_PROT_EN_2_AUDIO,
453 MT8192_TOP_AXI_PROT_EN_2_SET,
454 MT8192_TOP_AXI_PROT_EN_2_CLR,
455 MT8192_TOP_AXI_PROT_EN_2_STA1),
456 },
457 },
458 [MT6893_POWER_DOMAIN_ADSP] = {
459 .name = "audio",
460 .sta_mask = BIT(22),
461 .ctl_offs = 0x358,
462 .pwr_sta_offs = 0x16c,
463 .pwr_sta2nd_offs = 0x170,
464 .sram_pdn_bits = BIT(9),
465 .sram_pdn_ack_bits = BIT(12),
466 .bp_cfg = {
467 BUS_PROT_WR(INFRA,
468 MT6893_TOP_AXI_PROT_EN_2_ADSP,
469 MT8192_TOP_AXI_PROT_EN_2_SET,
470 MT8192_TOP_AXI_PROT_EN_2_CLR,
471 MT8192_TOP_AXI_PROT_EN_2_STA1),
472 },
473 },
474 [MT6893_POWER_DOMAIN_CAM] = {
475 .name = "cam",
476 .sta_mask = BIT(23),
477 .ctl_offs = 0x35c,
478 .pwr_sta_offs = 0x16c,
479 .pwr_sta2nd_offs = 0x170,
480 .sram_pdn_bits = BIT(8),
481 .sram_pdn_ack_bits = BIT(12),
482 .bp_cfg = {
483 BUS_PROT_WR(INFRA,
484 MT6893_TOP_AXI_PROT_EN_2_CAM_STEP1,
485 MT8192_TOP_AXI_PROT_EN_2_SET,
486 MT8192_TOP_AXI_PROT_EN_2_CLR,
487 MT8192_TOP_AXI_PROT_EN_2_STA1),
488 BUS_PROT_WR(INFRA,
489 MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP2,
490 MT8192_TOP_AXI_PROT_EN_MM_SET,
491 MT8192_TOP_AXI_PROT_EN_MM_CLR,
492 MT8192_TOP_AXI_PROT_EN_MM_STA1),
493 BUS_PROT_WR(INFRA,
494 MT6893_TOP_AXI_PROT_EN_1_CAM_STEP3,
495 MT8192_TOP_AXI_PROT_EN_1_SET,
496 MT8192_TOP_AXI_PROT_EN_1_CLR,
497 MT8192_TOP_AXI_PROT_EN_1_STA1),
498 BUS_PROT_WR(INFRA,
499 MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP4,
500 MT8192_TOP_AXI_PROT_EN_MM_SET,
501 MT8192_TOP_AXI_PROT_EN_MM_CLR,
502 MT8192_TOP_AXI_PROT_EN_MM_STA1),
503 },
504 },
505 [MT6893_POWER_DOMAIN_CAM_RAWA] = {
506 .name = "cam_rawa",
507 .sta_mask = BIT(24),
508 .ctl_offs = 0x360,
509 .pwr_sta_offs = 0x16c,
510 .pwr_sta2nd_offs = 0x170,
511 .sram_pdn_bits = BIT(8),
512 .sram_pdn_ack_bits = BIT(12),
513 .bp_cfg = {
514 BUS_PROT_WR(INFRA,
515 MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP1,
516 MT8192_TOP_AXI_PROT_EN_MM_SET,
517 MT8192_TOP_AXI_PROT_EN_MM_CLR,
518 MT8192_TOP_AXI_PROT_EN_MM_STA1),
519 BUS_PROT_WR(INFRA,
520 MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP2,
521 MT8192_TOP_AXI_PROT_EN_MM_SET,
522 MT8192_TOP_AXI_PROT_EN_MM_CLR,
523 MT8192_TOP_AXI_PROT_EN_MM_STA1),
524 },
525 },
526 [MT6893_POWER_DOMAIN_CAM_RAWB] = {
527 .name = "cam_rawb",
528 .sta_mask = BIT(25),
529 .ctl_offs = 0x364,
530 .pwr_sta_offs = 0x16c,
531 .pwr_sta2nd_offs = 0x170,
532 .sram_pdn_bits = BIT(8),
533 .sram_pdn_ack_bits = BIT(12),
534 .bp_cfg = {
535 BUS_PROT_WR(INFRA,
536 MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP1,
537 MT8192_TOP_AXI_PROT_EN_MM_SET,
538 MT8192_TOP_AXI_PROT_EN_MM_CLR,
539 MT8192_TOP_AXI_PROT_EN_MM_STA1),
540 BUS_PROT_WR(INFRA,
541 MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP2,
542 MT8192_TOP_AXI_PROT_EN_MM_SET,
543 MT8192_TOP_AXI_PROT_EN_MM_CLR,
544 MT8192_TOP_AXI_PROT_EN_MM_STA1),
545 },
546 },
547 [MT6893_POWER_DOMAIN_CAM_RAWC] = {
548 .name = "cam_rawc",
549 .sta_mask = BIT(26),
550 .ctl_offs = 0x368,
551 .pwr_sta_offs = 0x16c,
552 .pwr_sta2nd_offs = 0x170,
553 .sram_pdn_bits = BIT(8),
554 .sram_pdn_ack_bits = BIT(12),
555 .bp_cfg = {
556 BUS_PROT_WR(INFRA,
557 MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP1,
558 MT8192_TOP_AXI_PROT_EN_MM_SET,
559 MT8192_TOP_AXI_PROT_EN_MM_CLR,
560 MT8192_TOP_AXI_PROT_EN_MM_STA1),
561 BUS_PROT_WR(INFRA,
562 MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP2,
563 MT8192_TOP_AXI_PROT_EN_MM_SET,
564 MT8192_TOP_AXI_PROT_EN_MM_CLR,
565 MT8192_TOP_AXI_PROT_EN_MM_STA1),
566 },
567 },
568 [MT6893_POWER_DOMAIN_DP_TX] = {
569 .name = "dp_tx",
570 .sta_mask = BIT(27),
571 .ctl_offs = 0x3ac,
572 .pwr_sta_offs = 0x16c,
573 .pwr_sta2nd_offs = 0x170,
574 .sram_pdn_bits = BIT(8),
575 .sram_pdn_ack_bits = BIT(12),
576 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
577 },
578};
579
580static const struct scpsys_soc_data mt6893_scpsys_data = {
581 .domains_data = scpsys_domain_data_mt6893,
582 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6893),
583};
584
585#endif /* __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H */