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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#ifdef dev_fmt
38#undef dev_fmt
39#endif
40
41#define dev_fmt(fmt) "amdgpu: " fmt
42
43#include "amdgpu_ctx.h"
44
45#include <linux/atomic.h>
46#include <linux/wait.h>
47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52#include <linux/pci.h>
53
54#include <drm/ttm/ttm_bo.h>
55#include <drm/ttm/ttm_placement.h>
56
57#include <drm/amdgpu_drm.h>
58#include <drm/drm_gem.h>
59#include <drm/drm_ioctl.h>
60
61#include <kgd_kfd_interface.h>
62#include "dm_pp_interface.h"
63#include "kgd_pp_interface.h"
64
65#include "amd_shared.h"
66#include "amdgpu_utils.h"
67#include "amdgpu_mode.h"
68#include "amdgpu_ih.h"
69#include "amdgpu_irq.h"
70#include "amdgpu_ucode.h"
71#include "amdgpu_ttm.h"
72#include "amdgpu_psp.h"
73#include "amdgpu_gds.h"
74#include "amdgpu_sync.h"
75#include "amdgpu_ring.h"
76#include "amdgpu_vm.h"
77#include "amdgpu_dpm.h"
78#include "amdgpu_acp.h"
79#include "amdgpu_uvd.h"
80#include "amdgpu_vce.h"
81#include "amdgpu_vcn.h"
82#include "amdgpu_jpeg.h"
83#include "amdgpu_vpe.h"
84#include "amdgpu_umsch_mm.h"
85#include "amdgpu_gmc.h"
86#include "amdgpu_gfx.h"
87#include "amdgpu_sdma.h"
88#include "amdgpu_lsdma.h"
89#include "amdgpu_nbio.h"
90#include "amdgpu_hdp.h"
91#include "amdgpu_dm.h"
92#include "amdgpu_virt.h"
93#include "amdgpu_csa.h"
94#include "amdgpu_mes_ctx.h"
95#include "amdgpu_gart.h"
96#include "amdgpu_debugfs.h"
97#include "amdgpu_job.h"
98#include "amdgpu_bo_list.h"
99#include "amdgpu_gem.h"
100#include "amdgpu_doorbell.h"
101#include "amdgpu_amdkfd.h"
102#include "amdgpu_discovery.h"
103#include "amdgpu_mes.h"
104#include "amdgpu_umc.h"
105#include "amdgpu_mmhub.h"
106#include "amdgpu_gfxhub.h"
107#include "amdgpu_df.h"
108#include "amdgpu_smuio.h"
109#include "amdgpu_fdinfo.h"
110#include "amdgpu_mca.h"
111#include "amdgpu_aca.h"
112#include "amdgpu_ras.h"
113#include "amdgpu_cper.h"
114#include "amdgpu_xcp.h"
115#include "amdgpu_seq64.h"
116#include "amdgpu_reg_state.h"
117#include "amdgpu_userq.h"
118#include "amdgpu_eviction_fence.h"
119#if defined(CONFIG_DRM_AMD_ISP)
120#include "amdgpu_isp.h"
121#endif
122
123#define MAX_GPU_INSTANCE 64
124
125#define GFX_SLICE_PERIOD_MS 250
126
127struct amdgpu_gpu_instance {
128 struct amdgpu_device *adev;
129 int mgpu_fan_enabled;
130};
131
132struct amdgpu_mgpu_info {
133 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
134 struct mutex mutex;
135 uint32_t num_gpu;
136 uint32_t num_dgpu;
137 uint32_t num_apu;
138};
139
140enum amdgpu_ss {
141 AMDGPU_SS_DRV_LOAD,
142 AMDGPU_SS_DEV_D0,
143 AMDGPU_SS_DEV_D3,
144 AMDGPU_SS_DRV_UNLOAD
145};
146
147struct amdgpu_hwip_reg_entry {
148 u32 hwip;
149 u32 inst;
150 u32 seg;
151 u32 reg_offset;
152 const char *reg_name;
153};
154
155struct amdgpu_watchdog_timer {
156 bool timeout_fatal_disable;
157 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
158};
159
160#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
161
162/*
163 * Modules parameters.
164 */
165extern int amdgpu_modeset;
166extern unsigned int amdgpu_vram_limit;
167extern int amdgpu_vis_vram_limit;
168extern int amdgpu_gart_size;
169extern int amdgpu_gtt_size;
170extern int amdgpu_moverate;
171extern int amdgpu_audio;
172extern int amdgpu_disp_priority;
173extern int amdgpu_hw_i2c;
174extern int amdgpu_pcie_gen2;
175extern int amdgpu_msi;
176extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
177extern int amdgpu_dpm;
178extern int amdgpu_fw_load_type;
179extern int amdgpu_aspm;
180extern int amdgpu_runtime_pm;
181extern uint amdgpu_ip_block_mask;
182extern int amdgpu_bapm;
183extern int amdgpu_deep_color;
184extern int amdgpu_vm_size;
185extern int amdgpu_vm_block_size;
186extern int amdgpu_vm_fragment_size;
187extern int amdgpu_vm_fault_stop;
188extern int amdgpu_vm_debug;
189extern int amdgpu_vm_update_mode;
190extern int amdgpu_exp_hw_support;
191extern int amdgpu_dc;
192extern int amdgpu_sched_jobs;
193extern int amdgpu_sched_hw_submission;
194extern uint amdgpu_pcie_gen_cap;
195extern uint amdgpu_pcie_lane_cap;
196extern u64 amdgpu_cg_mask;
197extern uint amdgpu_pg_mask;
198extern uint amdgpu_sdma_phase_quantum;
199extern char *amdgpu_disable_cu;
200extern char *amdgpu_virtual_display;
201extern uint amdgpu_pp_feature_mask;
202extern uint amdgpu_force_long_training;
203extern int amdgpu_lbpw;
204extern int amdgpu_compute_multipipe;
205extern int amdgpu_gpu_recovery;
206extern int amdgpu_emu_mode;
207extern uint amdgpu_smu_memory_pool_size;
208extern int amdgpu_smu_pptable_id;
209extern uint amdgpu_dc_feature_mask;
210extern uint amdgpu_freesync_vid_mode;
211extern uint amdgpu_dc_debug_mask;
212extern uint amdgpu_dc_visual_confirm;
213extern int amdgpu_dm_abm_level;
214extern int amdgpu_backlight;
215extern int amdgpu_damage_clips;
216extern struct amdgpu_mgpu_info mgpu_info;
217extern int amdgpu_ras_enable;
218extern uint amdgpu_ras_mask;
219extern int amdgpu_bad_page_threshold;
220extern bool amdgpu_ignore_bad_page_threshold;
221extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
222extern int amdgpu_async_gfx_ring;
223extern int amdgpu_mcbp;
224extern int amdgpu_discovery;
225extern int amdgpu_mes;
226extern int amdgpu_mes_log_enable;
227extern int amdgpu_mes_kiq;
228extern int amdgpu_uni_mes;
229extern int amdgpu_noretry;
230extern int amdgpu_force_asic_type;
231extern int amdgpu_smartshift_bias;
232extern int amdgpu_use_xgmi_p2p;
233extern int amdgpu_mtype_local;
234extern int amdgpu_enforce_isolation;
235#ifdef CONFIG_HSA_AMD
236extern int sched_policy;
237extern bool debug_evictions;
238extern bool no_system_mem_limit;
239extern int halt_if_hws_hang;
240extern uint amdgpu_svm_default_granularity;
241#else
242static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
243static const bool __maybe_unused debug_evictions; /* = false */
244static const bool __maybe_unused no_system_mem_limit;
245static const int __maybe_unused halt_if_hws_hang;
246#endif
247#ifdef CONFIG_HSA_AMD_P2P
248extern bool pcie_p2p;
249#endif
250
251extern int amdgpu_tmz;
252extern int amdgpu_reset_method;
253
254#ifdef CONFIG_DRM_AMDGPU_SI
255extern int amdgpu_si_support;
256#endif
257#ifdef CONFIG_DRM_AMDGPU_CIK
258extern int amdgpu_cik_support;
259#endif
260extern int amdgpu_num_kcq;
261
262#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
263#define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024)
264extern int amdgpu_vcnfw_log;
265extern int amdgpu_sg_display;
266extern int amdgpu_umsch_mm;
267extern int amdgpu_seamless;
268extern int amdgpu_umsch_mm_fwlog;
269
270extern int amdgpu_user_partt_mode;
271extern int amdgpu_agp;
272extern int amdgpu_rebar;
273
274extern int amdgpu_wbrf;
275extern int amdgpu_user_queue;
276
277extern uint amdgpu_hdmi_hpd_debounce_delay_ms;
278
279#define AMDGPU_VM_MAX_NUM_CTX 4096
280#define AMDGPU_SG_THRESHOLD (256*1024*1024)
281#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
282#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
283#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
284#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
285#define AMDGPUFB_CONN_LIMIT 4
286#define AMDGPU_BIOS_NUM_SCRATCH 16
287
288#define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
289
290/* hard reset data */
291#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
292
293/* reset flags */
294#define AMDGPU_RESET_GFX (1 << 0)
295#define AMDGPU_RESET_COMPUTE (1 << 1)
296#define AMDGPU_RESET_DMA (1 << 2)
297#define AMDGPU_RESET_CP (1 << 3)
298#define AMDGPU_RESET_GRBM (1 << 4)
299#define AMDGPU_RESET_DMA1 (1 << 5)
300#define AMDGPU_RESET_RLC (1 << 6)
301#define AMDGPU_RESET_SEM (1 << 7)
302#define AMDGPU_RESET_IH (1 << 8)
303#define AMDGPU_RESET_VMC (1 << 9)
304#define AMDGPU_RESET_MC (1 << 10)
305#define AMDGPU_RESET_DISPLAY (1 << 11)
306#define AMDGPU_RESET_UVD (1 << 12)
307#define AMDGPU_RESET_VCE (1 << 13)
308#define AMDGPU_RESET_VCE1 (1 << 14)
309
310/* reset mask */
311#define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */
312#define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */
313#define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */
314#define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */
315
316/* max cursor sizes (in pixels) */
317#define CIK_CURSOR_WIDTH 128
318#define CIK_CURSOR_HEIGHT 128
319
320/* smart shift bias level limits */
321#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
322#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
323
324/* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
325#define AMDGPU_SWCTF_EXTRA_DELAY 50
326
327struct amdgpu_xcp_mgr;
328struct amdgpu_device;
329struct amdgpu_irq_src;
330struct amdgpu_fpriv;
331struct amdgpu_bo_va_mapping;
332struct kfd_vm_fault_info;
333struct amdgpu_hive_info;
334struct amdgpu_reset_context;
335struct amdgpu_reset_control;
336
337enum amdgpu_cp_irq {
338 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
339 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
340 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
341 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
342 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
343 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
344 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
345 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
346 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
347 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
348
349 AMDGPU_CP_IRQ_LAST
350};
351
352enum amdgpu_thermal_irq {
353 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
354 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
355
356 AMDGPU_THERMAL_IRQ_LAST
357};
358
359enum amdgpu_kiq_irq {
360 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
361 AMDGPU_CP_KIQ_IRQ_LAST
362};
363#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
364#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
365#define MAX_KIQ_REG_TRY 1000
366
367int amdgpu_device_ip_set_clockgating_state(void *dev,
368 enum amd_ip_block_type block_type,
369 enum amd_clockgating_state state);
370int amdgpu_device_ip_set_powergating_state(void *dev,
371 enum amd_ip_block_type block_type,
372 enum amd_powergating_state state);
373void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
374 u64 *flags);
375int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
376 enum amd_ip_block_type block_type);
377bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev,
378 enum amd_ip_block_type block_type);
379bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev,
380 enum amd_ip_block_type block_type);
381int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block);
382
383int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block);
384
385#define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM
386
387struct amdgpu_ip_block_status {
388 bool valid;
389 bool sw;
390 bool hw;
391 bool late_initialized;
392 bool hang;
393};
394
395struct amdgpu_ip_block_version {
396 const enum amd_ip_block_type type;
397 const u32 major;
398 const u32 minor;
399 const u32 rev;
400 const struct amd_ip_funcs *funcs;
401};
402
403struct amdgpu_ip_block {
404 struct amdgpu_ip_block_status status;
405 const struct amdgpu_ip_block_version *version;
406 struct amdgpu_device *adev;
407};
408
409int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
410 enum amd_ip_block_type type,
411 u32 major, u32 minor);
412
413struct amdgpu_ip_block *
414amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
415 enum amd_ip_block_type type);
416
417int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
418 const struct amdgpu_ip_block_version *ip_block_version);
419
420/*
421 * BIOS.
422 */
423bool amdgpu_get_bios(struct amdgpu_device *adev);
424bool amdgpu_read_bios(struct amdgpu_device *adev);
425bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
426 u8 *bios, u32 length_bytes);
427void amdgpu_bios_release(struct amdgpu_device *adev);
428/*
429 * Clocks
430 */
431
432#define AMDGPU_MAX_PPLL 3
433
434struct amdgpu_clock {
435 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
436 struct amdgpu_pll spll;
437 struct amdgpu_pll mpll;
438 /* 10 Khz units */
439 uint32_t default_mclk;
440 uint32_t default_sclk;
441 uint32_t default_dispclk;
442 uint32_t dp_extclk;
443 uint32_t max_pixel_clock;
444};
445
446/* sub-allocation manager, it has to be protected by another lock.
447 * By conception this is an helper for other part of the driver
448 * like the indirect buffer or semaphore, which both have their
449 * locking.
450 *
451 * Principe is simple, we keep a list of sub allocation in offset
452 * order (first entry has offset == 0, last entry has the highest
453 * offset).
454 *
455 * When allocating new object we first check if there is room at
456 * the end total_size - (last_object_offset + last_object_size) >=
457 * alloc_size. If so we allocate new object there.
458 *
459 * When there is not enough room at the end, we start waiting for
460 * each sub object until we reach object_offset+object_size >=
461 * alloc_size, this object then become the sub object we return.
462 *
463 * Alignment can't be bigger than page size.
464 *
465 * Hole are not considered for allocation to keep things simple.
466 * Assumption is that there won't be hole (all object on same
467 * alignment).
468 */
469
470struct amdgpu_sa_manager {
471 struct drm_suballoc_manager base;
472 struct amdgpu_bo *bo;
473 uint64_t gpu_addr;
474 void *cpu_ptr;
475};
476
477/*
478 * IRQS.
479 */
480
481struct amdgpu_flip_work {
482 struct delayed_work flip_work;
483 struct work_struct unpin_work;
484 struct amdgpu_device *adev;
485 int crtc_id;
486 u32 target_vblank;
487 uint64_t base;
488 struct drm_pending_vblank_event *event;
489 struct amdgpu_bo *old_abo;
490 unsigned shared_count;
491 struct dma_fence **shared;
492 struct dma_fence_cb cb;
493 bool async;
494};
495
496/*
497 * file private structure
498 */
499
500struct amdgpu_fpriv {
501 struct amdgpu_vm vm;
502 struct amdgpu_bo_va *prt_va;
503 struct amdgpu_bo_va *csa_va;
504 struct amdgpu_bo_va *seq64_va;
505 struct mutex bo_list_lock;
506 struct idr bo_list_handles;
507 struct amdgpu_ctx_mgr ctx_mgr;
508 struct amdgpu_userq_mgr userq_mgr;
509
510 /* Eviction fence infra */
511 struct amdgpu_eviction_fence_mgr evf_mgr;
512
513 /** GPU partition selection */
514 uint32_t xcp_id;
515};
516
517int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
518
519/*
520 * Writeback
521 */
522#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
523
524/**
525 * amdgpu_wb - This struct is used for small GPU memory allocation.
526 *
527 * This struct is used to allocate a small amount of GPU memory that can be
528 * used to shadow certain states into the memory. This is especially useful for
529 * providing easy CPU access to some states without requiring register access
530 * (e.g., if some block is power gated, reading register may be problematic).
531 *
532 * Note: the term writeback was initially used because many of the amdgpu
533 * components had some level of writeback memory, and this struct initially
534 * described those components.
535 */
536struct amdgpu_wb {
537
538 /**
539 * @wb_obj:
540 *
541 * Buffer Object used for the writeback memory.
542 */
543 struct amdgpu_bo *wb_obj;
544
545 /**
546 * @wb:
547 *
548 * Pointer to the first writeback slot. In terms of CPU address
549 * this value can be accessed directly by using the offset as an index.
550 * For the GPU address, it is necessary to use gpu_addr and the offset.
551 */
552 uint32_t *wb;
553
554 /**
555 * @gpu_addr:
556 *
557 * Writeback base address in the GPU.
558 */
559 uint64_t gpu_addr;
560
561 /**
562 * @num_wb:
563 *
564 * Number of writeback slots reserved for amdgpu.
565 */
566 u32 num_wb;
567
568 /**
569 * @used:
570 *
571 * Track the writeback slot already used.
572 */
573 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
574
575 /**
576 * @lock:
577 *
578 * Protects read and write of the used field array.
579 */
580 spinlock_t lock;
581};
582
583int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
584void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
585
586/*
587 * Benchmarking
588 */
589int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
590
591/*
592 * ASIC specific register table accessible by UMD
593 */
594struct amdgpu_allowed_register_entry {
595 uint32_t reg_offset;
596 bool grbm_indexed;
597};
598
599/**
600 * enum amd_reset_method - Methods for resetting AMD GPU devices
601 *
602 * @AMD_RESET_METHOD_NONE: The device will not be reset.
603 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs.
604 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the
605 * any device.
606 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.)
607 * individually. Suitable only for some discrete GPU, not
608 * available for all ASICs.
609 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs
610 * are reset depends on the ASIC. Notably doesn't reset IPs
611 * shared with the CPU on APUs or the memory controllers (so
612 * VRAM is not lost). Not available on all ASICs.
613 * @AMD_RESET_LINK: Triggers SW-UP link reset on other GPUs
614 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card
615 * but without powering off the PCI bus. Suitable only for
616 * discrete GPUs.
617 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset
618 * and does a secondary bus reset or FLR, depending on what the
619 * underlying hardware supports.
620 *
621 * Methods available for AMD GPU driver for resetting the device. Not all
622 * methods are suitable for every device. User can override the method using
623 * module parameter `reset_method`.
624 */
625enum amd_reset_method {
626 AMD_RESET_METHOD_NONE = -1,
627 AMD_RESET_METHOD_LEGACY = 0,
628 AMD_RESET_METHOD_MODE0,
629 AMD_RESET_METHOD_MODE1,
630 AMD_RESET_METHOD_MODE2,
631 AMD_RESET_METHOD_LINK,
632 AMD_RESET_METHOD_BACO,
633 AMD_RESET_METHOD_PCI,
634 AMD_RESET_METHOD_ON_INIT,
635};
636
637struct amdgpu_video_codec_info {
638 u32 codec_type;
639 u32 max_width;
640 u32 max_height;
641 u32 max_pixels_per_frame;
642 u32 max_level;
643};
644
645#define codec_info_build(type, width, height, level) \
646 .codec_type = type,\
647 .max_width = width,\
648 .max_height = height,\
649 .max_pixels_per_frame = height * width,\
650 .max_level = level,
651
652struct amdgpu_video_codecs {
653 const u32 codec_count;
654 const struct amdgpu_video_codec_info *codec_array;
655};
656
657/*
658 * ASIC specific functions.
659 */
660struct amdgpu_asic_funcs {
661 bool (*read_disabled_bios)(struct amdgpu_device *adev);
662 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
663 u8 *bios, u32 length_bytes);
664 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
665 u32 sh_num, u32 reg_offset, u32 *value);
666 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
667 int (*reset)(struct amdgpu_device *adev);
668 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
669 /* get the reference clock */
670 u32 (*get_xclk)(struct amdgpu_device *adev);
671 /* MM block clocks */
672 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
673 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
674 /* static power management */
675 int (*get_pcie_lanes)(struct amdgpu_device *adev);
676 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
677 /* get config memsize register */
678 u32 (*get_config_memsize)(struct amdgpu_device *adev);
679 /* flush hdp write queue */
680 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
681 /* invalidate hdp read cache */
682 void (*invalidate_hdp)(struct amdgpu_device *adev,
683 struct amdgpu_ring *ring);
684 /* check if the asic needs a full reset of if soft reset will work */
685 bool (*need_full_reset)(struct amdgpu_device *adev);
686 /* initialize doorbell layout for specific asic*/
687 void (*init_doorbell_index)(struct amdgpu_device *adev);
688 /* PCIe bandwidth usage */
689 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
690 uint64_t *count1);
691 /* do we need to reset the asic at init time (e.g., kexec) */
692 bool (*need_reset_on_init)(struct amdgpu_device *adev);
693 /* PCIe replay counter */
694 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
695 /* device supports BACO */
696 int (*supports_baco)(struct amdgpu_device *adev);
697 /* pre asic_init quirks */
698 void (*pre_asic_init)(struct amdgpu_device *adev);
699 /* enter/exit umd stable pstate */
700 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
701 /* query video codecs */
702 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
703 const struct amdgpu_video_codecs **codecs);
704 /* encode "> 32bits" smn addressing */
705 u64 (*encode_ext_smn_addressing)(int ext_id);
706
707 ssize_t (*get_reg_state)(struct amdgpu_device *adev,
708 enum amdgpu_reg_state reg_state, void *buf,
709 size_t max_size);
710};
711
712/*
713 * IOCTL.
714 */
715int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
716 struct drm_file *filp);
717
718int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
719int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
720 struct drm_file *filp);
721int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
722int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
723 struct drm_file *filp);
724
725/* VRAM scratch page for HDP bug, default vram page */
726struct amdgpu_mem_scratch {
727 struct amdgpu_bo *robj;
728 uint32_t *ptr;
729 u64 gpu_addr;
730};
731
732/*
733 * CGS
734 */
735struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
736void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
737
738/*
739 * Core structure, functions and helpers.
740 */
741typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
742typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
743
744typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
745typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
746
747typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
748typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
749
750typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t);
751typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t);
752
753typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
754typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
755
756struct amdgpu_mmio_remap {
757 u32 reg_offset;
758 resource_size_t bus_addr;
759 struct amdgpu_bo *bo;
760};
761
762/* Define the HW IP blocks will be used in driver , add more if necessary */
763enum amd_hw_ip_block_type {
764 GC_HWIP = 1,
765 HDP_HWIP,
766 SDMA0_HWIP,
767 SDMA1_HWIP,
768 SDMA2_HWIP,
769 SDMA3_HWIP,
770 SDMA4_HWIP,
771 SDMA5_HWIP,
772 SDMA6_HWIP,
773 SDMA7_HWIP,
774 LSDMA_HWIP,
775 MMHUB_HWIP,
776 ATHUB_HWIP,
777 NBIO_HWIP,
778 MP0_HWIP,
779 MP1_HWIP,
780 UVD_HWIP,
781 VCN_HWIP = UVD_HWIP,
782 JPEG_HWIP = VCN_HWIP,
783 VCN1_HWIP,
784 VCE_HWIP,
785 VPE_HWIP,
786 DF_HWIP,
787 DCE_HWIP,
788 OSSSYS_HWIP,
789 SMUIO_HWIP,
790 PWR_HWIP,
791 NBIF_HWIP,
792 THM_HWIP,
793 CLK_HWIP,
794 UMC_HWIP,
795 RSMU_HWIP,
796 XGMI_HWIP,
797 DCI_HWIP,
798 PCIE_HWIP,
799 ISP_HWIP,
800 MAX_HWIP
801};
802
803#define HWIP_MAX_INSTANCE 44
804
805#define HW_ID_MAX 300
806#define IP_VERSION_FULL(mj, mn, rv, var, srev) \
807 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev))
808#define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0)
809#define IP_VERSION_MAJ(ver) ((ver) >> 24)
810#define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF)
811#define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF)
812#define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF)
813#define IP_VERSION_SUBREV(ver) ((ver) & 0xF)
814#define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8)
815
816struct amdgpu_ip_map_info {
817 /* Map of logical to actual dev instances/mask */
818 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
819 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
820 enum amd_hw_ip_block_type block,
821 int8_t inst);
822 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
823 enum amd_hw_ip_block_type block,
824 uint32_t mask);
825};
826
827enum amdgpu_uid_type {
828 AMDGPU_UID_TYPE_XCD,
829 AMDGPU_UID_TYPE_AID,
830 AMDGPU_UID_TYPE_SOC,
831 AMDGPU_UID_TYPE_MAX
832};
833
834#define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */
835
836struct amdgpu_uid {
837 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX];
838 struct amdgpu_device *adev;
839};
840
841struct amd_powerplay {
842 void *pp_handle;
843 const struct amd_pm_funcs *pp_funcs;
844};
845
846/* polaris10 kickers */
847#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
848 ((rid == 0xE3) || \
849 (rid == 0xE4) || \
850 (rid == 0xE5) || \
851 (rid == 0xE7) || \
852 (rid == 0xEF))) || \
853 ((did == 0x6FDF) && \
854 ((rid == 0xE7) || \
855 (rid == 0xEF) || \
856 (rid == 0xFF))))
857
858#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
859 ((rid == 0xE1) || \
860 (rid == 0xF7)))
861
862/* polaris11 kickers */
863#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
864 ((rid == 0xE0) || \
865 (rid == 0xE5))) || \
866 ((did == 0x67FF) && \
867 ((rid == 0xCF) || \
868 (rid == 0xEF) || \
869 (rid == 0xFF))))
870
871#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
872 ((rid == 0xE2)))
873
874/* polaris12 kickers */
875#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
876 ((rid == 0xC0) || \
877 (rid == 0xC1) || \
878 (rid == 0xC3) || \
879 (rid == 0xC7))) || \
880 ((did == 0x6981) && \
881 ((rid == 0x00) || \
882 (rid == 0x01) || \
883 (rid == 0x10))))
884
885struct amdgpu_mqd_prop {
886 uint64_t mqd_gpu_addr;
887 uint64_t hqd_base_gpu_addr;
888 uint64_t rptr_gpu_addr;
889 uint64_t wptr_gpu_addr;
890 uint32_t queue_size;
891 bool use_doorbell;
892 uint32_t doorbell_index;
893 uint64_t eop_gpu_addr;
894 uint32_t hqd_pipe_priority;
895 uint32_t hqd_queue_priority;
896 bool allow_tunneling;
897 bool hqd_active;
898 uint64_t shadow_addr;
899 uint64_t gds_bkup_addr;
900 uint64_t csa_addr;
901 uint64_t fence_address;
902 bool tmz_queue;
903 bool kernel_queue;
904};
905
906struct amdgpu_mqd {
907 unsigned mqd_size;
908 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
909 struct amdgpu_mqd_prop *p);
910};
911
912struct amdgpu_pcie_reset_ctx {
913 bool in_link_reset;
914 bool occurs_dpc;
915 bool audio_suspended;
916 struct pci_dev *swus;
917 struct pci_saved_state *swus_pcistate;
918 struct pci_saved_state *swds_pcistate;
919};
920
921/*
922 * Custom Init levels could be defined for different situations where a full
923 * initialization of all hardware blocks are not expected. Sample cases are
924 * custom init sequences after resume after S0i3/S3, reset on initialization,
925 * partial reset of blocks etc. Presently, this defines only two levels. Levels
926 * are described in corresponding struct definitions - amdgpu_init_default,
927 * amdgpu_init_minimal_xgmi.
928 */
929enum amdgpu_init_lvl_id {
930 AMDGPU_INIT_LEVEL_DEFAULT,
931 AMDGPU_INIT_LEVEL_MINIMAL_XGMI,
932 AMDGPU_INIT_LEVEL_RESET_RECOVERY,
933};
934
935struct amdgpu_init_level {
936 enum amdgpu_init_lvl_id level;
937 uint32_t hwini_ip_block_mask;
938};
939
940#define AMDGPU_RESET_MAGIC_NUM 64
941#define AMDGPU_MAX_DF_PERFMONS 4
942struct amdgpu_reset_domain;
943struct amdgpu_fru_info;
944
945enum amdgpu_enforce_isolation_mode {
946 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0,
947 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1,
948 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2,
949 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3,
950};
951
952struct amdgpu_device {
953 struct device *dev;
954 struct pci_dev *pdev;
955 struct drm_device ddev;
956
957#ifdef CONFIG_DRM_AMD_ACP
958 struct amdgpu_acp acp;
959#endif
960 struct amdgpu_hive_info *hive;
961 struct amdgpu_xcp_mgr *xcp_mgr;
962 /* ASIC */
963 enum amd_asic_type asic_type;
964 uint32_t family;
965 uint32_t rev_id;
966 uint32_t external_rev_id;
967 unsigned long flags;
968 unsigned long apu_flags;
969 int usec_timeout;
970 const struct amdgpu_asic_funcs *asic_funcs;
971 bool shutdown;
972 bool need_swiotlb;
973 bool accel_working;
974 struct notifier_block acpi_nb;
975 struct notifier_block pm_nb;
976 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
977 struct debugfs_blob_wrapper debugfs_vbios_blob;
978 struct mutex srbm_mutex;
979 /* GRBM index mutex. Protects concurrent access to GRBM index */
980 struct mutex grbm_idx_mutex;
981 struct dev_pm_domain vga_pm_domain;
982 bool have_disp_power_ref;
983 bool have_atomics_support;
984
985 /* BIOS */
986 bool is_atom_fw;
987 uint8_t *bios;
988 uint32_t bios_size;
989 uint32_t bios_scratch_reg_offset;
990 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
991
992 /* Register/doorbell mmio */
993 resource_size_t rmmio_base;
994 resource_size_t rmmio_size;
995 void __iomem *rmmio;
996 /* protects concurrent MM_INDEX/DATA based register access */
997 spinlock_t mmio_idx_lock;
998 struct amdgpu_mmio_remap rmmio_remap;
999 /* protects concurrent SMC based register access */
1000 spinlock_t smc_idx_lock;
1001 amdgpu_rreg_t smc_rreg;
1002 amdgpu_wreg_t smc_wreg;
1003 /* protects concurrent PCIE register access */
1004 spinlock_t pcie_idx_lock;
1005 amdgpu_rreg_t pcie_rreg;
1006 amdgpu_wreg_t pcie_wreg;
1007 amdgpu_rreg_t pciep_rreg;
1008 amdgpu_wreg_t pciep_wreg;
1009 amdgpu_rreg_ext_t pcie_rreg_ext;
1010 amdgpu_wreg_ext_t pcie_wreg_ext;
1011 amdgpu_rreg64_t pcie_rreg64;
1012 amdgpu_wreg64_t pcie_wreg64;
1013 amdgpu_rreg64_ext_t pcie_rreg64_ext;
1014 amdgpu_wreg64_ext_t pcie_wreg64_ext;
1015 /* protects concurrent UVD register access */
1016 spinlock_t uvd_ctx_idx_lock;
1017 amdgpu_rreg_t uvd_ctx_rreg;
1018 amdgpu_wreg_t uvd_ctx_wreg;
1019 /* protects concurrent DIDT register access */
1020 spinlock_t didt_idx_lock;
1021 amdgpu_rreg_t didt_rreg;
1022 amdgpu_wreg_t didt_wreg;
1023 /* protects concurrent gc_cac register access */
1024 spinlock_t gc_cac_idx_lock;
1025 amdgpu_rreg_t gc_cac_rreg;
1026 amdgpu_wreg_t gc_cac_wreg;
1027 /* protects concurrent se_cac register access */
1028 spinlock_t se_cac_idx_lock;
1029 amdgpu_rreg_t se_cac_rreg;
1030 amdgpu_wreg_t se_cac_wreg;
1031 /* protects concurrent ENDPOINT (audio) register access */
1032 spinlock_t audio_endpt_idx_lock;
1033 amdgpu_block_rreg_t audio_endpt_rreg;
1034 amdgpu_block_wreg_t audio_endpt_wreg;
1035 struct amdgpu_doorbell doorbell;
1036
1037 /* clock/pll info */
1038 struct amdgpu_clock clock;
1039
1040 /* MC */
1041 struct amdgpu_gmc gmc;
1042 struct amdgpu_gart gart;
1043 dma_addr_t dummy_page_addr;
1044 struct amdgpu_vm_manager vm_manager;
1045 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
1046 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
1047
1048 /* memory management */
1049 struct amdgpu_mman mman;
1050 struct amdgpu_mem_scratch mem_scratch;
1051 struct amdgpu_wb wb;
1052 atomic64_t num_bytes_moved;
1053 atomic64_t num_evictions;
1054 atomic64_t num_vram_cpu_page_faults;
1055 atomic_t gpu_reset_counter;
1056 atomic_t vram_lost_counter;
1057
1058 /* data for buffer migration throttling */
1059 struct {
1060 spinlock_t lock;
1061 s64 last_update_us;
1062 s64 accum_us; /* accumulated microseconds */
1063 s64 accum_us_vis; /* for visible VRAM */
1064 u32 log2_max_MBps;
1065 } mm_stats;
1066
1067 /* discovery*/
1068 struct amdgpu_discovery_info discovery;
1069
1070 /* display */
1071 bool enable_virtual_display;
1072 struct amdgpu_vkms_output *amdgpu_vkms_output;
1073 struct amdgpu_mode_info mode_info;
1074 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
1075 struct delayed_work hotplug_work;
1076 struct amdgpu_irq_src crtc_irq;
1077 struct amdgpu_irq_src vline0_irq;
1078 struct amdgpu_irq_src vupdate_irq;
1079 struct amdgpu_irq_src pageflip_irq;
1080 struct amdgpu_irq_src hpd_irq;
1081 struct amdgpu_irq_src dmub_trace_irq;
1082 struct amdgpu_irq_src dmub_outbox_irq;
1083
1084 /* rings */
1085 u64 fence_context;
1086 unsigned num_rings;
1087 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1088 struct dma_fence __rcu *gang_submit;
1089 bool ib_pool_ready;
1090 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
1091 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
1092
1093 /* interrupts */
1094 struct amdgpu_irq irq;
1095
1096 /* powerplay */
1097 struct amd_powerplay powerplay;
1098 struct amdgpu_pm pm;
1099 u64 cg_flags;
1100 u32 pg_flags;
1101
1102 /* nbio */
1103 struct amdgpu_nbio nbio;
1104
1105 /* hdp */
1106 struct amdgpu_hdp hdp;
1107
1108 /* smuio */
1109 struct amdgpu_smuio smuio;
1110
1111 /* mmhub */
1112 struct amdgpu_mmhub mmhub;
1113
1114 /* gfxhub */
1115 struct amdgpu_gfxhub gfxhub;
1116
1117 /* gfx */
1118 struct amdgpu_gfx gfx;
1119
1120 /* sdma */
1121 struct amdgpu_sdma sdma;
1122
1123 /* lsdma */
1124 struct amdgpu_lsdma lsdma;
1125
1126 /* uvd */
1127 struct amdgpu_uvd uvd;
1128
1129 /* vce */
1130 struct amdgpu_vce vce;
1131
1132 /* vcn */
1133 struct amdgpu_vcn vcn;
1134
1135 /* jpeg */
1136 struct amdgpu_jpeg jpeg;
1137
1138 /* vpe */
1139 struct amdgpu_vpe vpe;
1140
1141 /* umsch */
1142 struct amdgpu_umsch_mm umsch_mm;
1143 bool enable_umsch_mm;
1144
1145 /* firmwares */
1146 struct amdgpu_firmware firmware;
1147
1148 /* PSP */
1149 struct psp_context psp;
1150
1151 /* GDS */
1152 struct amdgpu_gds gds;
1153
1154 /* for userq and VM fences */
1155 struct amdgpu_seq64 seq64;
1156
1157 /* UMC */
1158 struct amdgpu_umc umc;
1159
1160 /* display related functionality */
1161 struct amdgpu_display_manager dm;
1162
1163#if defined(CONFIG_DRM_AMD_ISP)
1164 /* isp */
1165 struct amdgpu_isp isp;
1166#endif
1167
1168 /* mes */
1169 bool enable_mes;
1170 bool enable_mes_kiq;
1171 bool enable_uni_mes;
1172 struct amdgpu_mes mes;
1173 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
1174 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM];
1175
1176 /* xarray used to retrieve the user queue fence driver reference
1177 * in the EOP interrupt handler to signal the particular user
1178 * queue fence.
1179 */
1180 struct xarray userq_xa;
1181 /**
1182 * @userq_doorbell_xa: Global user queue map (doorbell index → queue)
1183 * Key: doorbell_index (unique global identifier for the queue)
1184 * Value: struct amdgpu_usermode_queue
1185 */
1186 struct xarray userq_doorbell_xa;
1187
1188 /* df */
1189 struct amdgpu_df df;
1190
1191 /* MCA */
1192 struct amdgpu_mca mca;
1193
1194 /* ACA */
1195 struct amdgpu_aca aca;
1196
1197 /* CPER */
1198 struct amdgpu_cper cper;
1199
1200 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1201 uint32_t harvest_ip_mask;
1202 int num_ip_blocks;
1203 struct mutex mn_lock;
1204 DECLARE_HASHTABLE(mn_hash, 7);
1205
1206 /* tracking pinned memory */
1207 atomic64_t vram_pin_size;
1208 atomic64_t visible_pin_size;
1209 atomic64_t gart_pin_size;
1210
1211 /* soc15 register offset based on ip, instance and segment */
1212 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1213 struct amdgpu_ip_map_info ip_map;
1214
1215 /* delayed work_func for deferring clockgating during resume */
1216 struct delayed_work delayed_init_work;
1217
1218 struct amdgpu_virt virt;
1219
1220 /* record hw reset is performed */
1221 bool has_hw_reset;
1222 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1223
1224 /* s3/s4 mask */
1225 bool in_suspend;
1226 bool in_s3;
1227 bool in_s4;
1228 bool in_s0ix;
1229 suspend_state_t last_suspend_state;
1230
1231 enum pp_mp1_state mp1_state;
1232 struct amdgpu_doorbell_index doorbell_index;
1233
1234 struct mutex notifier_lock;
1235
1236 int asic_reset_res;
1237 struct work_struct xgmi_reset_work;
1238 struct list_head reset_list;
1239
1240 long gfx_timeout;
1241 long sdma_timeout;
1242 long video_timeout;
1243 long compute_timeout;
1244 long psp_timeout;
1245
1246 uint64_t unique_id;
1247 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1248
1249 /* enable runtime pm on the device */
1250 bool in_runpm;
1251 bool has_pr3;
1252
1253 bool ucode_sysfs_en;
1254
1255 struct amdgpu_fru_info *fru_info;
1256 atomic_t throttling_logging_enabled;
1257 struct ratelimit_state throttling_logging_rs;
1258 uint32_t ras_hw_enabled;
1259 uint32_t ras_enabled;
1260 bool ras_default_ecc_enabled;
1261
1262 bool no_hw_access;
1263 struct pci_saved_state *pci_state;
1264 pci_channel_state_t pci_channel_state;
1265
1266 struct amdgpu_pcie_reset_ctx pcie_reset_ctx;
1267
1268 /* Track auto wait count on s_barrier settings */
1269 bool barrier_has_auto_waitcnt;
1270
1271 struct amdgpu_reset_control *reset_cntl;
1272 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1273
1274 bool ram_is_direct_mapped;
1275
1276 struct list_head ras_list;
1277
1278 struct amdgpu_reset_domain *reset_domain;
1279
1280 struct mutex benchmark_mutex;
1281
1282 bool scpm_enabled;
1283 uint32_t scpm_status;
1284
1285 struct work_struct reset_work;
1286
1287 bool dc_enabled;
1288 /* Mask of active clusters */
1289 uint32_t aid_mask;
1290
1291 /* Debug */
1292 bool debug_vm;
1293 bool debug_largebar;
1294 bool debug_disable_soft_recovery;
1295 bool debug_use_vram_fw_buf;
1296 bool debug_enable_ras_aca;
1297 bool debug_exp_resets;
1298 bool debug_disable_gpu_ring_reset;
1299 bool debug_vm_userptr;
1300 bool debug_disable_ce_logs;
1301 bool debug_enable_ce_cs;
1302
1303 /* Protection for the following isolation structure */
1304 struct mutex enforce_isolation_mutex;
1305 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP];
1306 struct amdgpu_isolation {
1307 void *owner;
1308 struct dma_fence *spearhead;
1309 struct amdgpu_sync active;
1310 struct amdgpu_sync prev;
1311 } isolation[MAX_XCP];
1312
1313 struct amdgpu_init_level *init_lvl;
1314
1315 /* This flag is used to determine how VRAM allocations are handled for APUs
1316 * in KFD: VRAM or GTT.
1317 */
1318 bool apu_prefer_gtt;
1319
1320 bool userq_halt_for_enforce_isolation;
1321 struct work_struct userq_reset_work;
1322 struct amdgpu_uid *uid_info;
1323
1324 /* KFD
1325 * Must be last --ends in a flexible-array member.
1326 */
1327 struct amdgpu_kfd_dev kfd;
1328};
1329
1330static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
1331 uint8_t ip, uint8_t inst)
1332{
1333 /* This considers only major/minor/rev and ignores
1334 * subrevision/variant fields.
1335 */
1336 return adev->ip_versions[ip][inst] & ~0xFFU;
1337}
1338
1339static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,
1340 uint8_t ip, uint8_t inst)
1341{
1342 /* This returns full version - major/minor/rev/variant/subrevision */
1343 return adev->ip_versions[ip][inst];
1344}
1345
1346static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1347{
1348 return container_of(ddev, struct amdgpu_device, ddev);
1349}
1350
1351static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1352{
1353 return &adev->ddev;
1354}
1355
1356static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1357{
1358 return container_of(bdev, struct amdgpu_device, mman.bdev);
1359}
1360
1361static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev)
1362{
1363 return !!adev->aid_mask;
1364}
1365
1366int amdgpu_device_init(struct amdgpu_device *adev,
1367 uint32_t flags);
1368void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1369void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1370
1371int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1372
1373void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1374 void *buf, size_t size, bool write);
1375size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1376 void *buf, size_t size, bool write);
1377
1378void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1379 void *buf, size_t size, bool write);
1380uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1381 uint32_t inst, uint32_t reg_addr, char reg_name[],
1382 uint32_t expected_value, uint32_t mask);
1383uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1384 uint32_t reg, uint32_t acc_flags);
1385u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1386 u64 reg_addr);
1387uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
1388 uint32_t reg, uint32_t acc_flags,
1389 uint32_t xcc_id);
1390void amdgpu_device_wreg(struct amdgpu_device *adev,
1391 uint32_t reg, uint32_t v,
1392 uint32_t acc_flags);
1393void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1394 u64 reg_addr, u32 reg_data);
1395void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
1396 uint32_t reg, uint32_t v,
1397 uint32_t acc_flags,
1398 uint32_t xcc_id);
1399void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1400 uint32_t reg, uint32_t v, uint32_t xcc_id);
1401void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1402uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1403
1404u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1405 u32 reg_addr);
1406u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1407 u32 reg_addr);
1408u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
1409 u64 reg_addr);
1410void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1411 u32 reg_addr, u32 reg_data);
1412void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1413 u32 reg_addr, u64 reg_data);
1414void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1415 u64 reg_addr, u64 reg_data);
1416u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1417bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev,
1418 enum amd_asic_type asic_type);
1419bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1420
1421void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1422
1423int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1424 struct amdgpu_reset_context *reset_context);
1425
1426int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1427 struct amdgpu_reset_context *reset_context);
1428
1429int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context);
1430
1431int emu_soc_asic_init(struct amdgpu_device *adev);
1432
1433/*
1434 * Registers read & write functions.
1435 */
1436#define AMDGPU_REGS_NO_KIQ (1<<1)
1437#define AMDGPU_REGS_RLC (1<<2)
1438
1439#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1440#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1441
1442#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0)
1443#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
1444
1445#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1446#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1447
1448#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1449#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1450#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1451#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1452#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1453#define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
1454#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
1455#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1456#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1457#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1458#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1459#define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1460#define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1461#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1462#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1463#define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
1464#define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
1465#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1466#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1467#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1468#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1469#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1470#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1471#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1472#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1473#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1474#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1475#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1476#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1477#define WREG32_P(reg, val, mask) \
1478 do { \
1479 uint32_t tmp_ = RREG32(reg); \
1480 tmp_ &= (mask); \
1481 tmp_ |= ((val) & ~(mask)); \
1482 WREG32(reg, tmp_); \
1483 } while (0)
1484#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1485#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1486#define WREG32_PLL_P(reg, val, mask) \
1487 do { \
1488 uint32_t tmp_ = RREG32_PLL(reg); \
1489 tmp_ &= (mask); \
1490 tmp_ |= ((val) & ~(mask)); \
1491 WREG32_PLL(reg, tmp_); \
1492 } while (0)
1493
1494#define WREG32_SMC_P(_Reg, _Val, _Mask) \
1495 do { \
1496 u32 tmp = RREG32_SMC(_Reg); \
1497 tmp &= (_Mask); \
1498 tmp |= ((_Val) & ~(_Mask)); \
1499 WREG32_SMC(_Reg, tmp); \
1500 } while (0)
1501
1502#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1503
1504#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1505#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1506
1507#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1508 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1509 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1510
1511#define REG_GET_FIELD(value, reg, field) \
1512 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1513
1514#define WREG32_FIELD(reg, field, val) \
1515 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1516
1517#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1518 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1519
1520#define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l))
1521/*
1522 * BIOS helpers.
1523 */
1524#define RBIOS8(i) (adev->bios[i])
1525#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1526#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1527
1528/*
1529 * ASICs macro.
1530 */
1531#define amdgpu_asic_set_vga_state(adev, state) \
1532 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1533#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1534#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1535#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1536#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1537#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1538#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1539#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1540#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1541#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1542#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1543#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1544#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1545#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1546#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1547#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1548#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1549#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1550#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1551#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1552#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1553 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1554#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1555
1556#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))
1557
1558#define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1559#define for_each_inst(i, inst_mask) \
1560 for (i = ffs(inst_mask); i-- != 0; \
1561 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1562
1563/* Common functions */
1564bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1565bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1566int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1567 struct amdgpu_job *job,
1568 struct amdgpu_reset_context *reset_context);
1569void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1570int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1571bool amdgpu_device_need_post(struct amdgpu_device *adev);
1572bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
1573bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1574
1575void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1576 u64 num_vis_bytes);
1577int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1578void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1579 const u32 *registers,
1580 const u32 array_size);
1581
1582int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1583int amdgpu_device_link_reset(struct amdgpu_device *adev);
1584bool amdgpu_device_supports_atpx(struct amdgpu_device *adev);
1585bool amdgpu_device_supports_px(struct amdgpu_device *adev);
1586bool amdgpu_device_supports_boco(struct amdgpu_device *adev);
1587bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev);
1588int amdgpu_device_supports_baco(struct amdgpu_device *adev);
1589void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev);
1590bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1591 struct amdgpu_device *peer_adev);
1592int amdgpu_device_baco_enter(struct amdgpu_device *adev);
1593int amdgpu_device_baco_exit(struct amdgpu_device *adev);
1594
1595void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1596 struct amdgpu_ring *ring);
1597void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1598 struct amdgpu_ring *ring);
1599
1600void amdgpu_device_halt(struct amdgpu_device *adev);
1601u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1602 u32 reg);
1603void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1604 u32 reg, u32 v);
1605struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev);
1606struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1607 struct dma_fence *gang);
1608struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev,
1609 struct amdgpu_ring *ring,
1610 struct amdgpu_job *job);
1611bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1612ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring);
1613ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);
1614
1615/* atpx handler */
1616#if defined(CONFIG_VGA_SWITCHEROO)
1617void amdgpu_register_atpx_handler(void);
1618void amdgpu_unregister_atpx_handler(void);
1619bool amdgpu_has_atpx_dgpu_power_cntl(void);
1620bool amdgpu_is_atpx_hybrid(void);
1621bool amdgpu_has_atpx(void);
1622#else
1623static inline void amdgpu_register_atpx_handler(void) {}
1624static inline void amdgpu_unregister_atpx_handler(void) {}
1625static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1626static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1627static inline bool amdgpu_has_atpx(void) { return false; }
1628#endif
1629
1630/*
1631 * KMS
1632 */
1633extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1634extern const int amdgpu_max_kms_ioctl;
1635
1636int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1637void amdgpu_driver_unload_kms(struct drm_device *dev);
1638int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1639void amdgpu_driver_postclose_kms(struct drm_device *dev,
1640 struct drm_file *file_priv);
1641void amdgpu_driver_release_kms(struct drm_device *dev);
1642
1643int amdgpu_device_prepare(struct drm_device *dev);
1644void amdgpu_device_complete(struct drm_device *dev);
1645int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1646int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1647u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1648int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1649void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1650int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1651 struct drm_file *filp);
1652
1653/*
1654 * functions used by amdgpu_encoder.c
1655 */
1656struct amdgpu_afmt_acr {
1657 u32 clock;
1658
1659 int n_32khz;
1660 int cts_32khz;
1661
1662 int n_44_1khz;
1663 int cts_44_1khz;
1664
1665 int n_48khz;
1666 int cts_48khz;
1667
1668};
1669
1670struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1671
1672/* amdgpu_acpi.c */
1673
1674struct amdgpu_numa_info {
1675 uint64_t size;
1676 int pxm;
1677 int nid;
1678};
1679
1680/* ATCS Device/Driver State */
1681#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1682#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1683#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1684#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1685
1686#if defined(CONFIG_ACPI)
1687int amdgpu_acpi_init(struct amdgpu_device *adev);
1688void amdgpu_acpi_fini(struct amdgpu_device *adev);
1689bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1690bool amdgpu_acpi_is_power_shift_control_supported(void);
1691int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1692 u8 perf_req, bool advertise);
1693int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1694 u8 dev_state, bool drv_state);
1695int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,
1696 enum amdgpu_ss ss_state);
1697int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1698int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1699 u64 *tmr_size);
1700int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1701 struct amdgpu_numa_info *numa_info);
1702
1703void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1704bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1705void amdgpu_acpi_detect(void);
1706void amdgpu_acpi_release(void);
1707#else
1708static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1709static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1710 u64 *tmr_offset, u64 *tmr_size)
1711{
1712 return -EINVAL;
1713}
1714static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1715 int xcc_id,
1716 struct amdgpu_numa_info *numa_info)
1717{
1718 return -EINVAL;
1719}
1720static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1721static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1722static inline void amdgpu_acpi_detect(void) { }
1723static inline void amdgpu_acpi_release(void) { }
1724static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1725static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1726 u8 dev_state, bool drv_state) { return 0; }
1727static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,
1728 enum amdgpu_ss ss_state)
1729{
1730 return 0;
1731}
1732static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { }
1733#endif
1734
1735#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1736bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1737bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1738#else
1739static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1740static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1741#endif
1742
1743#if defined(CONFIG_DRM_AMD_ISP)
1744int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev);
1745#endif
1746
1747void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1748void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1749
1750pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1751 pci_channel_state_t state);
1752pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1753pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1754void amdgpu_pci_resume(struct pci_dev *pdev);
1755
1756bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1757bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1758
1759bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1760
1761int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1762 enum amd_clockgating_state state);
1763int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1764 enum amd_powergating_state state);
1765
1766static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1767{
1768 return amdgpu_gpu_recovery != 0 &&
1769 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1770 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1771 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1772 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1773}
1774
1775#include "amdgpu_object.h"
1776
1777static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1778{
1779 return adev->gmc.tmz_enabled;
1780}
1781
1782int amdgpu_in_reset(struct amdgpu_device *adev);
1783
1784extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1785extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1786extern const struct attribute_group amdgpu_flash_attr_group;
1787
1788void amdgpu_set_init_level(struct amdgpu_device *adev,
1789 enum amdgpu_init_lvl_id lvl);
1790
1791static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev)
1792{
1793 u32 status;
1794 int r;
1795
1796 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status);
1797 if (r || PCI_POSSIBLE_ERROR(status)) {
1798 dev_err(adev->dev, "device lost from bus!");
1799 return -ENODEV;
1800 }
1801
1802 return 0;
1803}
1804
1805void amdgpu_device_set_uid(struct amdgpu_uid *uid_info,
1806 enum amdgpu_uid_type type, uint8_t inst,
1807 uint64_t uid);
1808uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info,
1809 enum amdgpu_uid_type type, uint8_t inst);
1810#endif