tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/arm,pl11x.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Arm PrimeCell Color LCD Controller PL110/PL111
8
9maintainers:
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
12
13description:
14 The Arm Primcell PL010/PL111 is an LCD controller IP, than scans out
15 a framebuffer region in system memory, and creates timed signals for
16 a variety of LCD panels.
17
18# We need a select here so we don't match all nodes with 'arm,primecell'
19select:
20 properties:
21 compatible:
22 contains:
23 enum:
24 - arm,pl110
25 - arm,pl111
26 required:
27 - compatible
28
29properties:
30 compatible:
31 items:
32 - enum:
33 - arm,pl110
34 - arm,pl111
35 - const: arm,primecell
36
37 reg:
38 maxItems: 1
39
40 interrupt-names:
41 oneOf:
42 - const: combined
43 description:
44 The IP provides four individual interrupt lines, but also one
45 combined line. If the integration only connects this line to the
46 interrupt controller, this single interrupt is noted here.
47 - items:
48 - const: mbe # CLCDMBEINTR
49 - const: vcomp # CLCDVCOMPINTR
50 - const: lnbu # CLCDLNBUINTR
51 - const: fuf # CLCDFUFINTR
52
53 interrupts:
54 minItems: 1
55 maxItems: 4
56
57 clock-names:
58 items:
59 - const: clcdclk
60 - const: apb_pclk
61
62 clocks:
63 items:
64 - description: The CLCDCLK reference clock for the controller.
65 - description: The HCLK AHB slave clock for the register access.
66
67 memory-region:
68 maxItems: 1
69 description:
70 Phandle to a node describing memory to be used for the framebuffer.
71 If not present, the framebuffer may be located anywhere in memory.
72
73 max-memory-bandwidth:
74 $ref: /schemas/types.yaml#/definitions/uint32
75 description:
76 Maximum bandwidth in bytes per second that the cell's memory interface
77 can handle.
78 If not present, the memory interface is fast enough to handle all
79 possible video modes.
80
81 resets:
82 maxItems: 1
83
84 port:
85 $ref: /schemas/graph.yaml#/$defs/port-base
86 additionalProperties: false
87
88 description:
89 Output endpoint of the controller, connecting the LCD panel signals.
90
91 properties:
92 endpoint:
93 $ref: /schemas/graph.yaml#/$defs/endpoint-base
94 unevaluatedProperties: false
95
96 properties:
97 arm,pl11x,tft-r0g0b0-pads:
98 $ref: /schemas/types.yaml#/definitions/uint32-array
99 items:
100 - description: index of CLD pad used for first red bit (R0)
101 - description: index of CLD pad used for first green bit (G0)
102 - description: index of CLD pad used for first blue bit (G0)
103 deprecated: true
104 description: |
105 DEPRECATED. An array of three 32-bit values, defining the way
106 CLD[23:0] pads are wired up.
107 The first value contains the index of the "CLD" external pin (pad)
108 used as R0 (first bit of the red component), the second value for
109 green, the third value for blue.
110 See also "LCD panel signal multiplexing details" paragraphs in the
111 PL110/PL111 Technical Reference Manuals.
112 This implicitly defines available color modes, for example:
113 - PL111 TFT 4:4:4 panel:
114 arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
115 - PL110 TFT (1:)5:5:5 panel:
116 arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
117 - PL111 TFT (1:)5:5:5 panel:
118 arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
119 - PL111 TFT 5:6:5 panel:
120 arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
121 - PL110 and PL111 TFT 8:8:8 panel:
122 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
123 - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
124 arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
125
126additionalProperties: false
127
128required:
129 - compatible
130 - reg
131 - clock-names
132 - clocks
133 - port
134
135allOf:
136 - if:
137 properties:
138 interrupts:
139 minItems: 2
140 required:
141 - interrupts
142 then:
143 required:
144 - interrupt-names
145
146examples:
147 - |
148 clcd@10020000 {
149 compatible = "arm,pl111", "arm,primecell";
150 reg = <0x10020000 0x1000>;
151 interrupt-names = "combined";
152 interrupts = <44>;
153 clocks = <&oscclk1>, <&oscclk2>;
154 clock-names = "clcdclk", "apb_pclk";
155 max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
156
157 port {
158 clcd_pads: endpoint {
159 remote-endpoint = <&clcd_panel>;
160 };
161 };
162 };
163
164 panel {
165 compatible = "arm,rtsm-display";
166
167 port {
168 clcd_panel: endpoint {
169 remote-endpoint = <&clcd_pads>;
170 };
171 };
172 };
173...