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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 * Roger Tseng <rogerable@realtek.com>
9 */
10
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/rtsx_pci.h>
14
15#include "rtsx_pcr.h"
16
17static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
18{
19 u8 val;
20
21 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
22 return val & 0x0F;
23}
24
25static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
26{
27 u8 driving_3v3[4][3] = {
28 {0x13, 0x13, 0x13},
29 {0x96, 0x96, 0x96},
30 {0x7F, 0x7F, 0x7F},
31 {0x96, 0x96, 0x96},
32 };
33 u8 driving_1v8[4][3] = {
34 {0x99, 0x99, 0x99},
35 {0xAA, 0xAA, 0xAA},
36 {0xFE, 0xFE, 0xFE},
37 {0xB3, 0xB3, 0xB3},
38 };
39 u8 (*driving)[3], drive_sel;
40
41 if (voltage == OUTPUT_3V3) {
42 driving = driving_3v3;
43 drive_sel = pcr->sd30_drive_sel_3v3;
44 } else {
45 driving = driving_1v8;
46 drive_sel = pcr->sd30_drive_sel_1v8;
47 }
48
49 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
50 0xFF, driving[drive_sel][0]);
51 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
52 0xFF, driving[drive_sel][1]);
53 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
54 0xFF, driving[drive_sel][2]);
55}
56
57static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
58{
59 struct pci_dev *pdev = pcr->pci;
60 u32 reg;
61
62 pci_read_config_dword(pdev, PCR_SETTING_REG1, ®);
63 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
64
65 if (!rtsx_vendor_setting_valid(reg))
66 return;
67
68 pcr->aspm_en = rtsx_reg_to_aspm(reg);
69 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
70 pcr->card_drive_sel &= 0x3F;
71 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
72
73 pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
74 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
75 if (CHK_PCI_PID(pcr, 0x522A))
76 pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
77 if (rtsx_check_mmc_support(reg))
78 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
79 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
80 if (rtsx_reg_check_reverse_socket(reg))
81 pcr->flags |= PCR_REVERSE_SOCKET;
82 if (rtsx_reg_check_cd_reverse(reg))
83 pcr->option.sd_cd_reverse_en = 1;
84 if (rtsx_reg_check_wp_reverse(reg))
85 pcr->option.sd_wp_reverse_en = 1;
86}
87
88static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
89{
90 struct rtsx_cr_option *option = &pcr->option;
91
92 if (CHK_PCI_PID(pcr, 0x522A)) {
93 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
94 | PM_L1_1_EN | PM_L1_2_EN))
95 rtsx_pci_disable_oobs_polling(pcr);
96 else
97 rtsx_pci_enable_oobs_polling(pcr);
98 }
99
100 if (option->ltr_en) {
101 if (option->ltr_enabled)
102 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
103 }
104}
105
106static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
107{
108 u16 cap;
109 struct rtsx_cr_option *option = &pcr->option;
110
111 rts5227_init_from_cfg(pcr);
112 rtsx_pci_init_cmd(pcr);
113
114 /* Configure GPIO as output */
115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
116 /* Reset ASPM state to default value */
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
118 /* Switch LDO3318 source from DV33 to card_3v3 */
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
121 /* LED shine disabled, set initial shine cycle period */
122 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
123 /* Configure LTR */
124 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
125 if (cap & PCI_EXP_DEVCTL2_LTR_EN)
126 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
127 /* Configure OBFF */
128 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
129 /* Configure driving */
130 rts5227_fill_driving(pcr, OUTPUT_3V3);
131 /* Configure force_clock_req */
132 if (pcr->flags & PCR_REVERSE_SOCKET)
133 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
134 else {
135 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x20, option->sd_cd_reverse_en << 5);
136 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x10, option->sd_wp_reverse_en << 4);
137 }
138
139 if (CHK_PCI_PID(pcr, 0x522A))
140 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_AUTOLOAD_CFG1,
141 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
142
143 if (pcr->rtd3_en) {
144 if (CHK_PCI_PID(pcr, 0x522A)) {
145 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PM_CTRL3, 0x01, 0x01);
146 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PME_FORCE_CTL, 0x30, 0x30);
147 } else {
148 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x01, 0x01);
149 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PME_FORCE_CTL, 0xFF, 0x33);
150 }
151 } else {
152 if (CHK_PCI_PID(pcr, 0x522A)) {
153 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PM_CTRL3, 0x01, 0x00);
154 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PME_FORCE_CTL, 0x30, 0x20);
155 } else {
156 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PME_FORCE_CTL, 0xFF, 0x30);
157 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x01, 0x00);
158 }
159 }
160
161 if (option->force_clkreq_0)
162 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
163 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
164 else
165 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
166 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
167
168 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
169
170 return rtsx_pci_send_cmd(pcr, 100);
171}
172
173static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
174{
175 int err;
176
177 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
178 if (err < 0)
179 return err;
180
181 /* Optimize RX sensitivity */
182 return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
183}
184
185static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
186{
187 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
188}
189
190static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
191{
192 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
193}
194
195static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
196{
197 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
198}
199
200static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
201{
202 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
203}
204
205static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
206{
207 int err;
208
209 if (pcr->option.ocp_en)
210 rtsx_pci_enable_ocp(pcr);
211
212 rtsx_pci_init_cmd(pcr);
213 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
214 SD_POWER_MASK, SD_PARTIAL_POWER_ON);
215
216 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
217 LDO3318_PWR_MASK, 0x02);
218
219 err = rtsx_pci_send_cmd(pcr, 100);
220 if (err < 0)
221 return err;
222
223 /* To avoid too large in-rush current */
224 msleep(20);
225 rtsx_pci_init_cmd(pcr);
226 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
227 SD_POWER_MASK, SD_POWER_ON);
228
229 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
230 LDO3318_PWR_MASK, 0x06);
231
232 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
233 SD_OUTPUT_EN, SD_OUTPUT_EN);
234 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
235 MS_OUTPUT_EN, MS_OUTPUT_EN);
236 return rtsx_pci_send_cmd(pcr, 100);
237}
238
239static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
240{
241 if (pcr->option.ocp_en)
242 rtsx_pci_disable_ocp(pcr);
243
244 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
245 PMOS_STRG_MASK, SD_POWER_OFF | PMOS_STRG_400mA);
246 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
247
248 return 0;
249}
250
251static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
252{
253 int err;
254
255 if (voltage == OUTPUT_3V3) {
256 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
257 if (err < 0)
258 return err;
259 } else if (voltage == OUTPUT_1V8) {
260 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
261 if (err < 0)
262 return err;
263 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
264 if (err < 0)
265 return err;
266 } else {
267 return -EINVAL;
268 }
269
270 /* set pad drive */
271 rtsx_pci_init_cmd(pcr);
272 rts5227_fill_driving(pcr, voltage);
273 return rtsx_pci_send_cmd(pcr, 100);
274}
275
276static const struct pcr_ops rts5227_pcr_ops = {
277 .fetch_vendor_settings = rts5227_fetch_vendor_settings,
278 .extra_init_hw = rts5227_extra_init_hw,
279 .optimize_phy = rts5227_optimize_phy,
280 .turn_on_led = rts5227_turn_on_led,
281 .turn_off_led = rts5227_turn_off_led,
282 .enable_auto_blink = rts5227_enable_auto_blink,
283 .disable_auto_blink = rts5227_disable_auto_blink,
284 .card_power_on = rts5227_card_power_on,
285 .card_power_off = rts5227_card_power_off,
286 .switch_output_voltage = rts5227_switch_output_voltage,
287 .cd_deglitch = NULL,
288 .conv_clk_and_div_n = NULL,
289};
290
291/* SD Pull Control Enable:
292 * SD_DAT[3:0] ==> pull up
293 * SD_CD ==> pull up
294 * SD_WP ==> pull up
295 * SD_CMD ==> pull up
296 * SD_CLK ==> pull down
297 */
298static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
299 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
300 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
301 0,
302};
303
304/* SD Pull Control Disable:
305 * SD_DAT[3:0] ==> pull down
306 * SD_CD ==> pull up
307 * SD_WP ==> pull down
308 * SD_CMD ==> pull down
309 * SD_CLK ==> pull down
310 */
311static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
312 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
313 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
314 0,
315};
316
317/* MS Pull Control Enable:
318 * MS CD ==> pull up
319 * others ==> pull down
320 */
321static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
322 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
323 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
324 0,
325};
326
327/* MS Pull Control Disable:
328 * MS CD ==> pull up
329 * others ==> pull down
330 */
331static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
332 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
333 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
334 0,
335};
336
337void rts5227_init_params(struct rtsx_pcr *pcr)
338{
339 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
340 pcr->num_slots = 2;
341 pcr->ops = &rts5227_pcr_ops;
342
343 pcr->flags = 0;
344 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
345 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
346 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
347 pcr->aspm_en = ASPM_L1_EN;
348 pcr->aspm_mode = ASPM_MODE_CFG;
349 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
350 pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
351
352 pcr->ic_version = rts5227_get_ic_version(pcr);
353 pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
354 pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
355 pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
356 pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
357
358 pcr->reg_pm_ctrl3 = PM_CTRL3;
359 pcr->option.sd_cd_reverse_en = 0;
360 pcr->option.sd_wp_reverse_en = 0;
361}
362
363static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
364{
365 int err;
366
367 err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
368 0x00);
369 if (err < 0)
370 return err;
371
372 if (is_version(pcr, 0x522A, IC_VER_A)) {
373 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
374 PHY_RCR2_INIT_27S);
375 if (err)
376 return err;
377
378 rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
379 rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
380 rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
381 rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
382 }
383
384 return 0;
385}
386
387static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
388{
389 rts5227_extra_init_hw(pcr);
390
391 /* Power down OCP for power consumption */
392 if (!pcr->card_exist)
393 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
394 OC_POWER_DOWN);
395
396 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
397 FUNC_FORCE_UPME_XMT_DBG);
398 rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
399 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
400 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
401
402 return 0;
403}
404
405static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
406{
407 int err;
408
409 if (voltage == OUTPUT_3V3) {
410 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
411 if (err < 0)
412 return err;
413 } else if (voltage == OUTPUT_1V8) {
414 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
415 if (err < 0)
416 return err;
417 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
418 if (err < 0)
419 return err;
420 } else {
421 return -EINVAL;
422 }
423
424 /* set pad drive */
425 rtsx_pci_init_cmd(pcr);
426 rts5227_fill_driving(pcr, voltage);
427 return rtsx_pci_send_cmd(pcr, 100);
428}
429
430static void rts522a_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
431{
432 /* Set relink_time to 0 */
433 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
434 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
435 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
436 RELINK_TIME_MASK, 0);
437
438 rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3,
439 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
440
441 if (!runtime) {
442 rtsx_pci_write_register(pcr, RTS522A_AUTOLOAD_CFG1,
443 CD_RESUME_EN_MASK, 0);
444 rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, 0x01, 0x00);
445 rtsx_pci_write_register(pcr, RTS522A_PME_FORCE_CTL, 0x30, 0x20);
446 }
447
448 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
449}
450
451
452static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
453{
454 struct rtsx_cr_option *option = &pcr->option;
455 int aspm_L1_1, aspm_L1_2;
456 u8 val = 0;
457
458 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
459 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
460
461 if (active) {
462 /* run, latency: 60us */
463 if (aspm_L1_1)
464 val = option->ltr_l1off_snooze_sspwrgate;
465 } else {
466 /* l1off, latency: 300us */
467 if (aspm_L1_2)
468 val = option->ltr_l1off_sspwrgate;
469 }
470
471 rtsx_set_l1off_sub(pcr, val);
472}
473
474/* rts522a operations mainly derived from rts5227, except phy/hw init setting.
475 */
476static const struct pcr_ops rts522a_pcr_ops = {
477 .fetch_vendor_settings = rts5227_fetch_vendor_settings,
478 .extra_init_hw = rts522a_extra_init_hw,
479 .optimize_phy = rts522a_optimize_phy,
480 .turn_on_led = rts5227_turn_on_led,
481 .turn_off_led = rts5227_turn_off_led,
482 .enable_auto_blink = rts5227_enable_auto_blink,
483 .disable_auto_blink = rts5227_disable_auto_blink,
484 .card_power_on = rts5227_card_power_on,
485 .card_power_off = rts5227_card_power_off,
486 .switch_output_voltage = rts522a_switch_output_voltage,
487 .force_power_down = rts522a_force_power_down,
488 .cd_deglitch = NULL,
489 .conv_clk_and_div_n = NULL,
490 .set_l1off_cfg_sub_d0 = rts522a_set_l1off_cfg_sub_d0,
491};
492
493void rts522a_init_params(struct rtsx_pcr *pcr)
494{
495 struct rtsx_cr_option *option = &pcr->option;
496
497 rts5227_init_params(pcr);
498 pcr->ops = &rts522a_pcr_ops;
499 pcr->aspm_mode = ASPM_MODE_REG;
500 pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
501 pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
502
503 option->dev_flags = LTR_L1SS_PWR_GATE_EN;
504 option->ltr_en = true;
505
506 /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
507 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
508 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
509 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
510 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
511 option->ltr_l1off_sspwrgate = 0x7F;
512 option->ltr_l1off_snooze_sspwrgate = 0x78;
513
514 pcr->option.ocp_en = 1;
515 if (pcr->option.ocp_en)
516 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
517 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
518 pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
519}