tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, Linaro Limited
5 *
6 */
7
8#include <linux/interconnect-provider.h>
9#include <linux/module.h>
10#include <linux/mod_devicetable.h>
11#include <linux/platform_device.h>
12#include <dt-bindings/interconnect/qcom,sm8350.h>
13
14#include "bcm-voter.h"
15#include "icc-rpmh.h"
16
17static struct qcom_icc_node qhm_qspi;
18static struct qcom_icc_node qhm_qup0;
19static struct qcom_icc_node qhm_qup1;
20static struct qcom_icc_node qhm_qup2;
21static struct qcom_icc_node qnm_a1noc_cfg;
22static struct qcom_icc_node xm_sdc4;
23static struct qcom_icc_node xm_ufs_mem;
24static struct qcom_icc_node xm_usb3_0;
25static struct qcom_icc_node xm_usb3_1;
26static struct qcom_icc_node qhm_qdss_bam;
27static struct qcom_icc_node qnm_a2noc_cfg;
28static struct qcom_icc_node qxm_crypto;
29static struct qcom_icc_node qxm_ipa;
30static struct qcom_icc_node xm_pcie3_0;
31static struct qcom_icc_node xm_pcie3_1;
32static struct qcom_icc_node xm_qdss_etr;
33static struct qcom_icc_node xm_sdc2;
34static struct qcom_icc_node xm_ufs_card;
35static struct qcom_icc_node qnm_gemnoc_cnoc;
36static struct qcom_icc_node qnm_gemnoc_pcie;
37static struct qcom_icc_node xm_qdss_dap;
38static struct qcom_icc_node qnm_cnoc_dc_noc;
39static struct qcom_icc_node alm_gpu_tcu;
40static struct qcom_icc_node alm_sys_tcu;
41static struct qcom_icc_node chm_apps;
42static struct qcom_icc_node qnm_cmpnoc;
43static struct qcom_icc_node qnm_gemnoc_cfg;
44static struct qcom_icc_node qnm_gpu;
45static struct qcom_icc_node qnm_mnoc_hf;
46static struct qcom_icc_node qnm_mnoc_sf;
47static struct qcom_icc_node qnm_pcie;
48static struct qcom_icc_node qnm_snoc_gc;
49static struct qcom_icc_node qnm_snoc_sf;
50static struct qcom_icc_node qhm_config_noc;
51static struct qcom_icc_node llcc_mc;
52static struct qcom_icc_node qnm_camnoc_hf;
53static struct qcom_icc_node qnm_camnoc_icp;
54static struct qcom_icc_node qnm_camnoc_sf;
55static struct qcom_icc_node qnm_mnoc_cfg;
56static struct qcom_icc_node qnm_video0;
57static struct qcom_icc_node qnm_video1;
58static struct qcom_icc_node qnm_video_cvp;
59static struct qcom_icc_node qxm_mdp0;
60static struct qcom_icc_node qxm_mdp1;
61static struct qcom_icc_node qxm_rot;
62static struct qcom_icc_node qhm_nsp_noc_config;
63static struct qcom_icc_node qxm_nsp;
64static struct qcom_icc_node qnm_aggre1_noc;
65static struct qcom_icc_node qnm_aggre2_noc;
66static struct qcom_icc_node qnm_snoc_cfg;
67static struct qcom_icc_node qxm_pimem;
68static struct qcom_icc_node xm_gic;
69static struct qcom_icc_node qns_a1noc_snoc;
70static struct qcom_icc_node srvc_aggre1_noc;
71static struct qcom_icc_node qns_a2noc_snoc;
72static struct qcom_icc_node qns_pcie_mem_noc;
73static struct qcom_icc_node srvc_aggre2_noc;
74static struct qcom_icc_node qhs_ahb2phy0;
75static struct qcom_icc_node qhs_ahb2phy1;
76static struct qcom_icc_node qhs_aoss;
77static struct qcom_icc_node qhs_apss;
78static struct qcom_icc_node qhs_camera_cfg;
79static struct qcom_icc_node qhs_clk_ctl;
80static struct qcom_icc_node qhs_compute_cfg;
81static struct qcom_icc_node qhs_cpr_cx;
82static struct qcom_icc_node qhs_cpr_mmcx;
83static struct qcom_icc_node qhs_cpr_mx;
84static struct qcom_icc_node qhs_crypto0_cfg;
85static struct qcom_icc_node qhs_cx_rdpm;
86static struct qcom_icc_node qhs_dcc_cfg;
87static struct qcom_icc_node qhs_display_cfg;
88static struct qcom_icc_node qhs_gpuss_cfg;
89static struct qcom_icc_node qhs_hwkm;
90static struct qcom_icc_node qhs_imem_cfg;
91static struct qcom_icc_node qhs_ipa;
92static struct qcom_icc_node qhs_ipc_router;
93static struct qcom_icc_node qhs_lpass_cfg;
94static struct qcom_icc_node qhs_mss_cfg;
95static struct qcom_icc_node qhs_mx_rdpm;
96static struct qcom_icc_node qhs_pcie0_cfg;
97static struct qcom_icc_node qhs_pcie1_cfg;
98static struct qcom_icc_node qhs_pdm;
99static struct qcom_icc_node qhs_pimem_cfg;
100static struct qcom_icc_node qhs_pka_wrapper_cfg;
101static struct qcom_icc_node qhs_pmu_wrapper_cfg;
102static struct qcom_icc_node qhs_qdss_cfg;
103static struct qcom_icc_node qhs_qspi;
104static struct qcom_icc_node qhs_qup0;
105static struct qcom_icc_node qhs_qup1;
106static struct qcom_icc_node qhs_qup2;
107static struct qcom_icc_node qhs_sdc2;
108static struct qcom_icc_node qhs_sdc4;
109static struct qcom_icc_node qhs_security;
110static struct qcom_icc_node qhs_spss_cfg;
111static struct qcom_icc_node qhs_tcsr;
112static struct qcom_icc_node qhs_tlmm;
113static struct qcom_icc_node qhs_ufs_card_cfg;
114static struct qcom_icc_node qhs_ufs_mem_cfg;
115static struct qcom_icc_node qhs_usb3_0;
116static struct qcom_icc_node qhs_usb3_1;
117static struct qcom_icc_node qhs_venus_cfg;
118static struct qcom_icc_node qhs_vsense_ctrl_cfg;
119static struct qcom_icc_node qns_a1_noc_cfg;
120static struct qcom_icc_node qns_a2_noc_cfg;
121static struct qcom_icc_node qns_ddrss_cfg;
122static struct qcom_icc_node qns_mnoc_cfg;
123static struct qcom_icc_node qns_snoc_cfg;
124static struct qcom_icc_node qxs_boot_imem;
125static struct qcom_icc_node qxs_imem;
126static struct qcom_icc_node qxs_pimem;
127static struct qcom_icc_node srvc_cnoc;
128static struct qcom_icc_node xs_pcie_0;
129static struct qcom_icc_node xs_pcie_1;
130static struct qcom_icc_node xs_qdss_stm;
131static struct qcom_icc_node xs_sys_tcu_cfg;
132static struct qcom_icc_node qhs_llcc;
133static struct qcom_icc_node qns_gemnoc;
134static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
135static struct qcom_icc_node qhs_modem_ms_mpu_cfg;
136static struct qcom_icc_node qns_gem_noc_cnoc;
137static struct qcom_icc_node qns_llcc;
138static struct qcom_icc_node qns_pcie;
139static struct qcom_icc_node srvc_even_gemnoc;
140static struct qcom_icc_node srvc_odd_gemnoc;
141static struct qcom_icc_node srvc_sys_gemnoc;
142static struct qcom_icc_node qhs_lpass_core;
143static struct qcom_icc_node qhs_lpass_lpi;
144static struct qcom_icc_node qhs_lpass_mpu;
145static struct qcom_icc_node qhs_lpass_top;
146static struct qcom_icc_node srvc_niu_aml_noc;
147static struct qcom_icc_node srvc_niu_lpass_agnoc;
148static struct qcom_icc_node ebi;
149static struct qcom_icc_node qns_mem_noc_hf;
150static struct qcom_icc_node qns_mem_noc_sf;
151static struct qcom_icc_node srvc_mnoc;
152static struct qcom_icc_node qns_nsp_gemnoc;
153static struct qcom_icc_node service_nsp_noc;
154static struct qcom_icc_node qns_gemnoc_gc;
155static struct qcom_icc_node qns_gemnoc_sf;
156static struct qcom_icc_node srvc_snoc;
157
158static struct qcom_icc_node qhm_qspi = {
159 .name = "qhm_qspi",
160 .channels = 1,
161 .buswidth = 4,
162 .num_links = 1,
163 .link_nodes = { &qns_a1noc_snoc },
164};
165
166static struct qcom_icc_node qhm_qup0 = {
167 .name = "qhm_qup0",
168 .channels = 1,
169 .buswidth = 4,
170 .num_links = 1,
171 .link_nodes = { &qns_a2noc_snoc },
172};
173
174static struct qcom_icc_node qhm_qup1 = {
175 .name = "qhm_qup1",
176 .channels = 1,
177 .buswidth = 4,
178 .num_links = 1,
179 .link_nodes = { &qns_a1noc_snoc },
180};
181
182static struct qcom_icc_node qhm_qup2 = {
183 .name = "qhm_qup2",
184 .channels = 1,
185 .buswidth = 4,
186 .num_links = 1,
187 .link_nodes = { &qns_a2noc_snoc },
188};
189
190static struct qcom_icc_node qnm_a1noc_cfg = {
191 .name = "qnm_a1noc_cfg",
192 .channels = 1,
193 .buswidth = 4,
194 .num_links = 1,
195 .link_nodes = { &srvc_aggre1_noc },
196};
197
198static struct qcom_icc_node xm_sdc4 = {
199 .name = "xm_sdc4",
200 .channels = 1,
201 .buswidth = 8,
202 .num_links = 1,
203 .link_nodes = { &qns_a1noc_snoc },
204};
205
206static struct qcom_icc_node xm_ufs_mem = {
207 .name = "xm_ufs_mem",
208 .channels = 1,
209 .buswidth = 8,
210 .num_links = 1,
211 .link_nodes = { &qns_a1noc_snoc },
212};
213
214static struct qcom_icc_node xm_usb3_0 = {
215 .name = "xm_usb3_0",
216 .channels = 1,
217 .buswidth = 8,
218 .num_links = 1,
219 .link_nodes = { &qns_a1noc_snoc },
220};
221
222static struct qcom_icc_node xm_usb3_1 = {
223 .name = "xm_usb3_1",
224 .channels = 1,
225 .buswidth = 8,
226 .num_links = 1,
227 .link_nodes = { &qns_a1noc_snoc },
228};
229
230static struct qcom_icc_node qhm_qdss_bam = {
231 .name = "qhm_qdss_bam",
232 .channels = 1,
233 .buswidth = 4,
234 .num_links = 1,
235 .link_nodes = { &qns_a2noc_snoc },
236};
237
238static struct qcom_icc_node qnm_a2noc_cfg = {
239 .name = "qnm_a2noc_cfg",
240 .channels = 1,
241 .buswidth = 4,
242 .num_links = 1,
243 .link_nodes = { &srvc_aggre2_noc },
244};
245
246static struct qcom_icc_node qxm_crypto = {
247 .name = "qxm_crypto",
248 .channels = 1,
249 .buswidth = 8,
250 .num_links = 1,
251 .link_nodes = { &qns_a2noc_snoc },
252};
253
254static struct qcom_icc_node qxm_ipa = {
255 .name = "qxm_ipa",
256 .channels = 1,
257 .buswidth = 8,
258 .num_links = 1,
259 .link_nodes = { &qns_a2noc_snoc },
260};
261
262static struct qcom_icc_node xm_pcie3_0 = {
263 .name = "xm_pcie3_0",
264 .channels = 1,
265 .buswidth = 8,
266 .num_links = 1,
267 .link_nodes = { &qns_pcie_mem_noc },
268};
269
270static struct qcom_icc_node xm_pcie3_1 = {
271 .name = "xm_pcie3_1",
272 .channels = 1,
273 .buswidth = 8,
274 .num_links = 1,
275 .link_nodes = { &qns_pcie_mem_noc },
276};
277
278static struct qcom_icc_node xm_qdss_etr = {
279 .name = "xm_qdss_etr",
280 .channels = 1,
281 .buswidth = 8,
282 .num_links = 1,
283 .link_nodes = { &qns_a2noc_snoc },
284};
285
286static struct qcom_icc_node xm_sdc2 = {
287 .name = "xm_sdc2",
288 .channels = 1,
289 .buswidth = 8,
290 .num_links = 1,
291 .link_nodes = { &qns_a2noc_snoc },
292};
293
294static struct qcom_icc_node xm_ufs_card = {
295 .name = "xm_ufs_card",
296 .channels = 1,
297 .buswidth = 8,
298 .num_links = 1,
299 .link_nodes = { &qns_a2noc_snoc },
300};
301
302static struct qcom_icc_node qnm_gemnoc_cnoc = {
303 .name = "qnm_gemnoc_cnoc",
304 .channels = 1,
305 .buswidth = 16,
306 .num_links = 56,
307 .link_nodes = { &qhs_ahb2phy0,
308 &qhs_ahb2phy1,
309 &qhs_aoss,
310 &qhs_apss,
311 &qhs_camera_cfg,
312 &qhs_clk_ctl,
313 &qhs_compute_cfg,
314 &qhs_cpr_cx,
315 &qhs_cpr_mmcx,
316 &qhs_cpr_mx,
317 &qhs_crypto0_cfg,
318 &qhs_cx_rdpm,
319 &qhs_dcc_cfg,
320 &qhs_display_cfg,
321 &qhs_gpuss_cfg,
322 &qhs_hwkm,
323 &qhs_imem_cfg,
324 &qhs_ipa,
325 &qhs_ipc_router,
326 &qhs_lpass_cfg,
327 &qhs_mss_cfg,
328 &qhs_mx_rdpm,
329 &qhs_pcie0_cfg,
330 &qhs_pcie1_cfg,
331 &qhs_pdm,
332 &qhs_pimem_cfg,
333 &qhs_pka_wrapper_cfg,
334 &qhs_pmu_wrapper_cfg,
335 &qhs_qdss_cfg,
336 &qhs_qspi,
337 &qhs_qup0,
338 &qhs_qup1,
339 &qhs_qup2,
340 &qhs_sdc2,
341 &qhs_sdc4,
342 &qhs_security,
343 &qhs_spss_cfg,
344 &qhs_tcsr,
345 &qhs_tlmm,
346 &qhs_ufs_card_cfg,
347 &qhs_ufs_mem_cfg,
348 &qhs_usb3_0,
349 &qhs_usb3_1,
350 &qhs_venus_cfg,
351 &qhs_vsense_ctrl_cfg,
352 &qns_a1_noc_cfg,
353 &qns_a2_noc_cfg,
354 &qns_ddrss_cfg,
355 &qns_mnoc_cfg,
356 &qns_snoc_cfg,
357 &qxs_boot_imem,
358 &qxs_imem,
359 &qxs_pimem,
360 &srvc_cnoc,
361 &xs_qdss_stm,
362 &xs_sys_tcu_cfg },
363};
364
365static struct qcom_icc_node qnm_gemnoc_pcie = {
366 .name = "qnm_gemnoc_pcie",
367 .channels = 1,
368 .buswidth = 8,
369 .num_links = 2,
370 .link_nodes = { &xs_pcie_0,
371 &xs_pcie_1 },
372};
373
374static struct qcom_icc_node xm_qdss_dap = {
375 .name = "xm_qdss_dap",
376 .channels = 1,
377 .buswidth = 8,
378 .num_links = 56,
379 .link_nodes = { &qhs_ahb2phy0,
380 &qhs_ahb2phy1,
381 &qhs_aoss,
382 &qhs_apss,
383 &qhs_camera_cfg,
384 &qhs_clk_ctl,
385 &qhs_compute_cfg,
386 &qhs_cpr_cx,
387 &qhs_cpr_mmcx,
388 &qhs_cpr_mx,
389 &qhs_crypto0_cfg,
390 &qhs_cx_rdpm,
391 &qhs_dcc_cfg,
392 &qhs_display_cfg,
393 &qhs_gpuss_cfg,
394 &qhs_hwkm,
395 &qhs_imem_cfg,
396 &qhs_ipa,
397 &qhs_ipc_router,
398 &qhs_lpass_cfg,
399 &qhs_mss_cfg,
400 &qhs_mx_rdpm,
401 &qhs_pcie0_cfg,
402 &qhs_pcie1_cfg,
403 &qhs_pdm,
404 &qhs_pimem_cfg,
405 &qhs_pka_wrapper_cfg,
406 &qhs_pmu_wrapper_cfg,
407 &qhs_qdss_cfg,
408 &qhs_qspi,
409 &qhs_qup0,
410 &qhs_qup1,
411 &qhs_qup2,
412 &qhs_sdc2,
413 &qhs_sdc4,
414 &qhs_security,
415 &qhs_spss_cfg,
416 &qhs_tcsr,
417 &qhs_tlmm,
418 &qhs_ufs_card_cfg,
419 &qhs_ufs_mem_cfg,
420 &qhs_usb3_0,
421 &qhs_usb3_1,
422 &qhs_venus_cfg,
423 &qhs_vsense_ctrl_cfg,
424 &qns_a1_noc_cfg,
425 &qns_a2_noc_cfg,
426 &qns_ddrss_cfg,
427 &qns_mnoc_cfg,
428 &qns_snoc_cfg,
429 &qxs_boot_imem,
430 &qxs_imem,
431 &qxs_pimem,
432 &srvc_cnoc,
433 &xs_qdss_stm,
434 &xs_sys_tcu_cfg },
435};
436
437static struct qcom_icc_node qnm_cnoc_dc_noc = {
438 .name = "qnm_cnoc_dc_noc",
439 .channels = 1,
440 .buswidth = 4,
441 .num_links = 2,
442 .link_nodes = { &qhs_llcc,
443 &qns_gemnoc },
444};
445
446static struct qcom_icc_node alm_gpu_tcu = {
447 .name = "alm_gpu_tcu",
448 .channels = 1,
449 .buswidth = 8,
450 .num_links = 2,
451 .link_nodes = { &qns_gem_noc_cnoc,
452 &qns_llcc },
453};
454
455static struct qcom_icc_node alm_sys_tcu = {
456 .name = "alm_sys_tcu",
457 .channels = 1,
458 .buswidth = 8,
459 .num_links = 2,
460 .link_nodes = { &qns_gem_noc_cnoc,
461 &qns_llcc },
462};
463
464static struct qcom_icc_node chm_apps = {
465 .name = "chm_apps",
466 .channels = 2,
467 .buswidth = 32,
468 .num_links = 3,
469 .link_nodes = { &qns_gem_noc_cnoc,
470 &qns_llcc,
471 &qns_pcie },
472};
473
474static struct qcom_icc_node qnm_cmpnoc = {
475 .name = "qnm_cmpnoc",
476 .channels = 2,
477 .buswidth = 32,
478 .num_links = 2,
479 .link_nodes = { &qns_gem_noc_cnoc,
480 &qns_llcc },
481};
482
483static struct qcom_icc_node qnm_gemnoc_cfg = {
484 .name = "qnm_gemnoc_cfg",
485 .channels = 1,
486 .buswidth = 4,
487 .num_links = 5,
488 .link_nodes = { &qhs_mdsp_ms_mpu_cfg,
489 &qhs_modem_ms_mpu_cfg,
490 &srvc_even_gemnoc,
491 &srvc_odd_gemnoc,
492 &srvc_sys_gemnoc },
493};
494
495static struct qcom_icc_node qnm_gpu = {
496 .name = "qnm_gpu",
497 .channels = 2,
498 .buswidth = 32,
499 .num_links = 2,
500 .link_nodes = { &qns_gem_noc_cnoc,
501 &qns_llcc },
502};
503
504static struct qcom_icc_node qnm_mnoc_hf = {
505 .name = "qnm_mnoc_hf",
506 .channels = 2,
507 .buswidth = 32,
508 .num_links = 1,
509 .link_nodes = { &qns_llcc },
510};
511
512static struct qcom_icc_node qnm_mnoc_sf = {
513 .name = "qnm_mnoc_sf",
514 .channels = 2,
515 .buswidth = 32,
516 .num_links = 2,
517 .link_nodes = { &qns_gem_noc_cnoc,
518 &qns_llcc },
519};
520
521static struct qcom_icc_node qnm_pcie = {
522 .name = "qnm_pcie",
523 .channels = 1,
524 .buswidth = 16,
525 .num_links = 2,
526 .link_nodes = { &qns_gem_noc_cnoc,
527 &qns_llcc },
528};
529
530static struct qcom_icc_node qnm_snoc_gc = {
531 .name = "qnm_snoc_gc",
532 .channels = 1,
533 .buswidth = 8,
534 .num_links = 1,
535 .link_nodes = { &qns_llcc },
536};
537
538static struct qcom_icc_node qnm_snoc_sf = {
539 .name = "qnm_snoc_sf",
540 .channels = 1,
541 .buswidth = 16,
542 .num_links = 3,
543 .link_nodes = { &qns_gem_noc_cnoc,
544 &qns_llcc,
545 &qns_pcie },
546};
547
548static struct qcom_icc_node qhm_config_noc = {
549 .name = "qhm_config_noc",
550 .channels = 1,
551 .buswidth = 4,
552 .num_links = 6,
553 .link_nodes = { &qhs_lpass_core,
554 &qhs_lpass_lpi,
555 &qhs_lpass_mpu,
556 &qhs_lpass_top,
557 &srvc_niu_aml_noc,
558 &srvc_niu_lpass_agnoc },
559};
560
561static struct qcom_icc_node llcc_mc = {
562 .name = "llcc_mc",
563 .channels = 4,
564 .buswidth = 4,
565 .num_links = 1,
566 .link_nodes = { &ebi },
567};
568
569static struct qcom_icc_node qnm_camnoc_hf = {
570 .name = "qnm_camnoc_hf",
571 .channels = 2,
572 .buswidth = 32,
573 .num_links = 1,
574 .link_nodes = { &qns_mem_noc_hf },
575};
576
577static struct qcom_icc_node qnm_camnoc_icp = {
578 .name = "qnm_camnoc_icp",
579 .channels = 1,
580 .buswidth = 8,
581 .num_links = 1,
582 .link_nodes = { &qns_mem_noc_sf },
583};
584
585static struct qcom_icc_node qnm_camnoc_sf = {
586 .name = "qnm_camnoc_sf",
587 .channels = 2,
588 .buswidth = 32,
589 .num_links = 1,
590 .link_nodes = { &qns_mem_noc_sf },
591};
592
593static struct qcom_icc_node qnm_mnoc_cfg = {
594 .name = "qnm_mnoc_cfg",
595 .channels = 1,
596 .buswidth = 4,
597 .num_links = 1,
598 .link_nodes = { &srvc_mnoc },
599};
600
601static struct qcom_icc_node qnm_video0 = {
602 .name = "qnm_video0",
603 .channels = 1,
604 .buswidth = 32,
605 .num_links = 1,
606 .link_nodes = { &qns_mem_noc_sf },
607};
608
609static struct qcom_icc_node qnm_video1 = {
610 .name = "qnm_video1",
611 .channels = 1,
612 .buswidth = 32,
613 .num_links = 1,
614 .link_nodes = { &qns_mem_noc_sf },
615};
616
617static struct qcom_icc_node qnm_video_cvp = {
618 .name = "qnm_video_cvp",
619 .channels = 1,
620 .buswidth = 32,
621 .num_links = 1,
622 .link_nodes = { &qns_mem_noc_sf },
623};
624
625static struct qcom_icc_node qxm_mdp0 = {
626 .name = "qxm_mdp0",
627 .channels = 1,
628 .buswidth = 32,
629 .num_links = 1,
630 .link_nodes = { &qns_mem_noc_hf },
631};
632
633static struct qcom_icc_node qxm_mdp1 = {
634 .name = "qxm_mdp1",
635 .channels = 1,
636 .buswidth = 32,
637 .num_links = 1,
638 .link_nodes = { &qns_mem_noc_hf },
639};
640
641static struct qcom_icc_node qxm_rot = {
642 .name = "qxm_rot",
643 .channels = 1,
644 .buswidth = 32,
645 .num_links = 1,
646 .link_nodes = { &qns_mem_noc_sf },
647};
648
649static struct qcom_icc_node qhm_nsp_noc_config = {
650 .name = "qhm_nsp_noc_config",
651 .channels = 1,
652 .buswidth = 4,
653 .num_links = 1,
654 .link_nodes = { &service_nsp_noc },
655};
656
657static struct qcom_icc_node qxm_nsp = {
658 .name = "qxm_nsp",
659 .channels = 2,
660 .buswidth = 32,
661 .num_links = 1,
662 .link_nodes = { &qns_nsp_gemnoc },
663};
664
665static struct qcom_icc_node qnm_aggre1_noc = {
666 .name = "qnm_aggre1_noc",
667 .channels = 1,
668 .buswidth = 16,
669 .num_links = 1,
670 .link_nodes = { &qns_gemnoc_sf },
671};
672
673static struct qcom_icc_node qnm_aggre2_noc = {
674 .name = "qnm_aggre2_noc",
675 .channels = 1,
676 .buswidth = 16,
677 .num_links = 1,
678 .link_nodes = { &qns_gemnoc_sf },
679};
680
681static struct qcom_icc_node qnm_snoc_cfg = {
682 .name = "qnm_snoc_cfg",
683 .channels = 1,
684 .buswidth = 4,
685 .num_links = 1,
686 .link_nodes = { &srvc_snoc },
687};
688
689static struct qcom_icc_node qxm_pimem = {
690 .name = "qxm_pimem",
691 .channels = 1,
692 .buswidth = 8,
693 .num_links = 1,
694 .link_nodes = { &qns_gemnoc_gc },
695};
696
697static struct qcom_icc_node xm_gic = {
698 .name = "xm_gic",
699 .channels = 1,
700 .buswidth = 8,
701 .num_links = 1,
702 .link_nodes = { &qns_gemnoc_gc },
703};
704
705static struct qcom_icc_node qns_a1noc_snoc = {
706 .name = "qns_a1noc_snoc",
707 .channels = 1,
708 .buswidth = 16,
709 .num_links = 1,
710 .link_nodes = { &qnm_aggre1_noc },
711};
712
713static struct qcom_icc_node srvc_aggre1_noc = {
714 .name = "srvc_aggre1_noc",
715 .channels = 1,
716 .buswidth = 4,
717};
718
719static struct qcom_icc_node qns_a2noc_snoc = {
720 .name = "qns_a2noc_snoc",
721 .channels = 1,
722 .buswidth = 16,
723 .num_links = 1,
724 .link_nodes = { &qnm_aggre2_noc },
725};
726
727static struct qcom_icc_node qns_pcie_mem_noc = {
728 .name = "qns_pcie_mem_noc",
729 .channels = 1,
730 .buswidth = 16,
731 .num_links = 1,
732 .link_nodes = { &qnm_pcie },
733};
734
735static struct qcom_icc_node srvc_aggre2_noc = {
736 .name = "srvc_aggre2_noc",
737 .channels = 1,
738 .buswidth = 4,
739};
740
741static struct qcom_icc_node qhs_ahb2phy0 = {
742 .name = "qhs_ahb2phy0",
743 .channels = 1,
744 .buswidth = 4,
745};
746
747static struct qcom_icc_node qhs_ahb2phy1 = {
748 .name = "qhs_ahb2phy1",
749 .channels = 1,
750 .buswidth = 4,
751};
752
753static struct qcom_icc_node qhs_aoss = {
754 .name = "qhs_aoss",
755 .channels = 1,
756 .buswidth = 4,
757};
758
759static struct qcom_icc_node qhs_apss = {
760 .name = "qhs_apss",
761 .channels = 1,
762 .buswidth = 8,
763};
764
765static struct qcom_icc_node qhs_camera_cfg = {
766 .name = "qhs_camera_cfg",
767 .channels = 1,
768 .buswidth = 4,
769};
770
771static struct qcom_icc_node qhs_clk_ctl = {
772 .name = "qhs_clk_ctl",
773 .channels = 1,
774 .buswidth = 4,
775};
776
777static struct qcom_icc_node qhs_compute_cfg = {
778 .name = "qhs_compute_cfg",
779 .channels = 1,
780 .buswidth = 4,
781};
782
783static struct qcom_icc_node qhs_cpr_cx = {
784 .name = "qhs_cpr_cx",
785 .channels = 1,
786 .buswidth = 4,
787};
788
789static struct qcom_icc_node qhs_cpr_mmcx = {
790 .name = "qhs_cpr_mmcx",
791 .channels = 1,
792 .buswidth = 4,
793};
794
795static struct qcom_icc_node qhs_cpr_mx = {
796 .name = "qhs_cpr_mx",
797 .channels = 1,
798 .buswidth = 4,
799};
800
801static struct qcom_icc_node qhs_crypto0_cfg = {
802 .name = "qhs_crypto0_cfg",
803 .channels = 1,
804 .buswidth = 4,
805};
806
807static struct qcom_icc_node qhs_cx_rdpm = {
808 .name = "qhs_cx_rdpm",
809 .channels = 1,
810 .buswidth = 4,
811};
812
813static struct qcom_icc_node qhs_dcc_cfg = {
814 .name = "qhs_dcc_cfg",
815 .channels = 1,
816 .buswidth = 4,
817};
818
819static struct qcom_icc_node qhs_display_cfg = {
820 .name = "qhs_display_cfg",
821 .channels = 1,
822 .buswidth = 4,
823};
824
825static struct qcom_icc_node qhs_gpuss_cfg = {
826 .name = "qhs_gpuss_cfg",
827 .channels = 1,
828 .buswidth = 8,
829};
830
831static struct qcom_icc_node qhs_hwkm = {
832 .name = "qhs_hwkm",
833 .channels = 1,
834 .buswidth = 4,
835};
836
837static struct qcom_icc_node qhs_imem_cfg = {
838 .name = "qhs_imem_cfg",
839 .channels = 1,
840 .buswidth = 4,
841};
842
843static struct qcom_icc_node qhs_ipa = {
844 .name = "qhs_ipa",
845 .channels = 1,
846 .buswidth = 4,
847};
848
849static struct qcom_icc_node qhs_ipc_router = {
850 .name = "qhs_ipc_router",
851 .channels = 1,
852 .buswidth = 4,
853};
854
855static struct qcom_icc_node qhs_lpass_cfg = {
856 .name = "qhs_lpass_cfg",
857 .channels = 1,
858 .buswidth = 4,
859 .num_links = 1,
860 .link_nodes = { &qhm_config_noc },
861};
862
863static struct qcom_icc_node qhs_mss_cfg = {
864 .name = "qhs_mss_cfg",
865 .channels = 1,
866 .buswidth = 4,
867};
868
869static struct qcom_icc_node qhs_mx_rdpm = {
870 .name = "qhs_mx_rdpm",
871 .channels = 1,
872 .buswidth = 4,
873};
874
875static struct qcom_icc_node qhs_pcie0_cfg = {
876 .name = "qhs_pcie0_cfg",
877 .channels = 1,
878 .buswidth = 4,
879};
880
881static struct qcom_icc_node qhs_pcie1_cfg = {
882 .name = "qhs_pcie1_cfg",
883 .channels = 1,
884 .buswidth = 4,
885};
886
887static struct qcom_icc_node qhs_pdm = {
888 .name = "qhs_pdm",
889 .channels = 1,
890 .buswidth = 4,
891};
892
893static struct qcom_icc_node qhs_pimem_cfg = {
894 .name = "qhs_pimem_cfg",
895 .channels = 1,
896 .buswidth = 4,
897};
898
899static struct qcom_icc_node qhs_pka_wrapper_cfg = {
900 .name = "qhs_pka_wrapper_cfg",
901 .channels = 1,
902 .buswidth = 4,
903};
904
905static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
906 .name = "qhs_pmu_wrapper_cfg",
907 .channels = 1,
908 .buswidth = 4,
909};
910
911static struct qcom_icc_node qhs_qdss_cfg = {
912 .name = "qhs_qdss_cfg",
913 .channels = 1,
914 .buswidth = 4,
915};
916
917static struct qcom_icc_node qhs_qspi = {
918 .name = "qhs_qspi",
919 .channels = 1,
920 .buswidth = 4,
921};
922
923static struct qcom_icc_node qhs_qup0 = {
924 .name = "qhs_qup0",
925 .channels = 1,
926 .buswidth = 4,
927};
928
929static struct qcom_icc_node qhs_qup1 = {
930 .name = "qhs_qup1",
931 .channels = 1,
932 .buswidth = 4,
933};
934
935static struct qcom_icc_node qhs_qup2 = {
936 .name = "qhs_qup2",
937 .channels = 1,
938 .buswidth = 4,
939};
940
941static struct qcom_icc_node qhs_sdc2 = {
942 .name = "qhs_sdc2",
943 .channels = 1,
944 .buswidth = 4,
945};
946
947static struct qcom_icc_node qhs_sdc4 = {
948 .name = "qhs_sdc4",
949 .channels = 1,
950 .buswidth = 4,
951};
952
953static struct qcom_icc_node qhs_security = {
954 .name = "qhs_security",
955 .channels = 1,
956 .buswidth = 4,
957};
958
959static struct qcom_icc_node qhs_spss_cfg = {
960 .name = "qhs_spss_cfg",
961 .channels = 1,
962 .buswidth = 4,
963};
964
965static struct qcom_icc_node qhs_tcsr = {
966 .name = "qhs_tcsr",
967 .channels = 1,
968 .buswidth = 4,
969};
970
971static struct qcom_icc_node qhs_tlmm = {
972 .name = "qhs_tlmm",
973 .channels = 1,
974 .buswidth = 4,
975};
976
977static struct qcom_icc_node qhs_ufs_card_cfg = {
978 .name = "qhs_ufs_card_cfg",
979 .channels = 1,
980 .buswidth = 4,
981};
982
983static struct qcom_icc_node qhs_ufs_mem_cfg = {
984 .name = "qhs_ufs_mem_cfg",
985 .channels = 1,
986 .buswidth = 4,
987};
988
989static struct qcom_icc_node qhs_usb3_0 = {
990 .name = "qhs_usb3_0",
991 .channels = 1,
992 .buswidth = 4,
993};
994
995static struct qcom_icc_node qhs_usb3_1 = {
996 .name = "qhs_usb3_1",
997 .channels = 1,
998 .buswidth = 4,
999};
1000
1001static struct qcom_icc_node qhs_venus_cfg = {
1002 .name = "qhs_venus_cfg",
1003 .channels = 1,
1004 .buswidth = 4,
1005};
1006
1007static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1008 .name = "qhs_vsense_ctrl_cfg",
1009 .channels = 1,
1010 .buswidth = 4,
1011};
1012
1013static struct qcom_icc_node qns_a1_noc_cfg = {
1014 .name = "qns_a1_noc_cfg",
1015 .channels = 1,
1016 .buswidth = 4,
1017};
1018
1019static struct qcom_icc_node qns_a2_noc_cfg = {
1020 .name = "qns_a2_noc_cfg",
1021 .channels = 1,
1022 .buswidth = 4,
1023};
1024
1025static struct qcom_icc_node qns_ddrss_cfg = {
1026 .name = "qns_ddrss_cfg",
1027 .channels = 1,
1028 .buswidth = 4,
1029};
1030
1031static struct qcom_icc_node qns_mnoc_cfg = {
1032 .name = "qns_mnoc_cfg",
1033 .channels = 1,
1034 .buswidth = 4,
1035};
1036
1037static struct qcom_icc_node qns_snoc_cfg = {
1038 .name = "qns_snoc_cfg",
1039 .channels = 1,
1040 .buswidth = 4,
1041};
1042
1043static struct qcom_icc_node qxs_boot_imem = {
1044 .name = "qxs_boot_imem",
1045 .channels = 1,
1046 .buswidth = 8,
1047};
1048
1049static struct qcom_icc_node qxs_imem = {
1050 .name = "qxs_imem",
1051 .channels = 1,
1052 .buswidth = 8,
1053};
1054
1055static struct qcom_icc_node qxs_pimem = {
1056 .name = "qxs_pimem",
1057 .channels = 1,
1058 .buswidth = 8,
1059};
1060
1061static struct qcom_icc_node srvc_cnoc = {
1062 .name = "srvc_cnoc",
1063 .channels = 1,
1064 .buswidth = 4,
1065};
1066
1067static struct qcom_icc_node xs_pcie_0 = {
1068 .name = "xs_pcie_0",
1069 .channels = 1,
1070 .buswidth = 8,
1071};
1072
1073static struct qcom_icc_node xs_pcie_1 = {
1074 .name = "xs_pcie_1",
1075 .channels = 1,
1076 .buswidth = 8,
1077};
1078
1079static struct qcom_icc_node xs_qdss_stm = {
1080 .name = "xs_qdss_stm",
1081 .channels = 1,
1082 .buswidth = 4,
1083};
1084
1085static struct qcom_icc_node xs_sys_tcu_cfg = {
1086 .name = "xs_sys_tcu_cfg",
1087 .channels = 1,
1088 .buswidth = 8,
1089};
1090
1091static struct qcom_icc_node qhs_llcc = {
1092 .name = "qhs_llcc",
1093 .channels = 1,
1094 .buswidth = 4,
1095};
1096
1097static struct qcom_icc_node qns_gemnoc = {
1098 .name = "qns_gemnoc",
1099 .channels = 1,
1100 .buswidth = 4,
1101};
1102
1103static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1104 .name = "qhs_mdsp_ms_mpu_cfg",
1105 .channels = 1,
1106 .buswidth = 4,
1107};
1108
1109static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
1110 .name = "qhs_modem_ms_mpu_cfg",
1111 .channels = 1,
1112 .buswidth = 4,
1113};
1114
1115static struct qcom_icc_node qns_gem_noc_cnoc = {
1116 .name = "qns_gem_noc_cnoc",
1117 .channels = 1,
1118 .buswidth = 16,
1119 .num_links = 1,
1120 .link_nodes = { &qnm_gemnoc_cnoc },
1121};
1122
1123static struct qcom_icc_node qns_llcc = {
1124 .name = "qns_llcc",
1125 .channels = 4,
1126 .buswidth = 16,
1127 .num_links = 1,
1128 .link_nodes = { &llcc_mc },
1129};
1130
1131static struct qcom_icc_node qns_pcie = {
1132 .name = "qns_pcie",
1133 .channels = 1,
1134 .buswidth = 8,
1135};
1136
1137static struct qcom_icc_node srvc_even_gemnoc = {
1138 .name = "srvc_even_gemnoc",
1139 .channels = 1,
1140 .buswidth = 4,
1141};
1142
1143static struct qcom_icc_node srvc_odd_gemnoc = {
1144 .name = "srvc_odd_gemnoc",
1145 .channels = 1,
1146 .buswidth = 4,
1147};
1148
1149static struct qcom_icc_node srvc_sys_gemnoc = {
1150 .name = "srvc_sys_gemnoc",
1151 .channels = 1,
1152 .buswidth = 4,
1153};
1154
1155static struct qcom_icc_node qhs_lpass_core = {
1156 .name = "qhs_lpass_core",
1157 .channels = 1,
1158 .buswidth = 4,
1159};
1160
1161static struct qcom_icc_node qhs_lpass_lpi = {
1162 .name = "qhs_lpass_lpi",
1163 .channels = 1,
1164 .buswidth = 4,
1165};
1166
1167static struct qcom_icc_node qhs_lpass_mpu = {
1168 .name = "qhs_lpass_mpu",
1169 .channels = 1,
1170 .buswidth = 4,
1171};
1172
1173static struct qcom_icc_node qhs_lpass_top = {
1174 .name = "qhs_lpass_top",
1175 .channels = 1,
1176 .buswidth = 4,
1177};
1178
1179static struct qcom_icc_node srvc_niu_aml_noc = {
1180 .name = "srvc_niu_aml_noc",
1181 .channels = 1,
1182 .buswidth = 4,
1183};
1184
1185static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1186 .name = "srvc_niu_lpass_agnoc",
1187 .channels = 1,
1188 .buswidth = 4,
1189};
1190
1191static struct qcom_icc_node ebi = {
1192 .name = "ebi",
1193 .channels = 4,
1194 .buswidth = 4,
1195};
1196
1197static struct qcom_icc_node qns_mem_noc_hf = {
1198 .name = "qns_mem_noc_hf",
1199 .channels = 2,
1200 .buswidth = 32,
1201 .num_links = 1,
1202 .link_nodes = { &qnm_mnoc_hf },
1203};
1204
1205static struct qcom_icc_node qns_mem_noc_sf = {
1206 .name = "qns_mem_noc_sf",
1207 .channels = 2,
1208 .buswidth = 32,
1209 .num_links = 1,
1210 .link_nodes = { &qnm_mnoc_sf },
1211};
1212
1213static struct qcom_icc_node srvc_mnoc = {
1214 .name = "srvc_mnoc",
1215 .channels = 1,
1216 .buswidth = 4,
1217};
1218
1219static struct qcom_icc_node qns_nsp_gemnoc = {
1220 .name = "qns_nsp_gemnoc",
1221 .channels = 2,
1222 .buswidth = 32,
1223 .num_links = 1,
1224 .link_nodes = { &qnm_cmpnoc },
1225};
1226
1227static struct qcom_icc_node service_nsp_noc = {
1228 .name = "service_nsp_noc",
1229 .channels = 1,
1230 .buswidth = 4,
1231};
1232
1233static struct qcom_icc_node qns_gemnoc_gc = {
1234 .name = "qns_gemnoc_gc",
1235 .channels = 1,
1236 .buswidth = 8,
1237 .num_links = 1,
1238 .link_nodes = { &qnm_snoc_gc },
1239};
1240
1241static struct qcom_icc_node qns_gemnoc_sf = {
1242 .name = "qns_gemnoc_sf",
1243 .channels = 1,
1244 .buswidth = 16,
1245 .num_links = 1,
1246 .link_nodes = { &qnm_snoc_sf },
1247};
1248
1249static struct qcom_icc_node srvc_snoc = {
1250 .name = "srvc_snoc",
1251 .channels = 1,
1252 .buswidth = 4,
1253};
1254
1255static struct qcom_icc_bcm bcm_acv = {
1256 .name = "ACV",
1257 .enable_mask = BIT(3),
1258 .keepalive = false,
1259 .num_nodes = 1,
1260 .nodes = { &ebi },
1261};
1262
1263static struct qcom_icc_bcm bcm_ce0 = {
1264 .name = "CE0",
1265 .keepalive = false,
1266 .num_nodes = 1,
1267 .nodes = { &qxm_crypto },
1268};
1269
1270static struct qcom_icc_bcm bcm_cn0 = {
1271 .name = "CN0",
1272 .keepalive = true,
1273 .num_nodes = 2,
1274 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1275};
1276
1277static struct qcom_icc_bcm bcm_cn1 = {
1278 .name = "CN1",
1279 .keepalive = false,
1280 .num_nodes = 47,
1281 .nodes = { &xm_qdss_dap,
1282 &qhs_ahb2phy0,
1283 &qhs_ahb2phy1,
1284 &qhs_aoss,
1285 &qhs_apss,
1286 &qhs_camera_cfg,
1287 &qhs_clk_ctl,
1288 &qhs_compute_cfg,
1289 &qhs_cpr_cx,
1290 &qhs_cpr_mmcx,
1291 &qhs_cpr_mx,
1292 &qhs_crypto0_cfg,
1293 &qhs_cx_rdpm,
1294 &qhs_dcc_cfg,
1295 &qhs_display_cfg,
1296 &qhs_gpuss_cfg,
1297 &qhs_hwkm,
1298 &qhs_imem_cfg,
1299 &qhs_ipa,
1300 &qhs_ipc_router,
1301 &qhs_mss_cfg,
1302 &qhs_mx_rdpm,
1303 &qhs_pcie0_cfg,
1304 &qhs_pcie1_cfg,
1305 &qhs_pimem_cfg,
1306 &qhs_pka_wrapper_cfg,
1307 &qhs_pmu_wrapper_cfg,
1308 &qhs_qdss_cfg,
1309 &qhs_qup0,
1310 &qhs_qup1,
1311 &qhs_qup2,
1312 &qhs_security,
1313 &qhs_spss_cfg,
1314 &qhs_tcsr,
1315 &qhs_tlmm,
1316 &qhs_ufs_card_cfg,
1317 &qhs_ufs_mem_cfg,
1318 &qhs_usb3_0,
1319 &qhs_usb3_1,
1320 &qhs_venus_cfg,
1321 &qhs_vsense_ctrl_cfg,
1322 &qns_a1_noc_cfg,
1323 &qns_a2_noc_cfg,
1324 &qns_ddrss_cfg,
1325 &qns_mnoc_cfg,
1326 &qns_snoc_cfg,
1327 &srvc_cnoc
1328 },
1329};
1330
1331static struct qcom_icc_bcm bcm_cn2 = {
1332 .name = "CN2",
1333 .keepalive = false,
1334 .num_nodes = 5,
1335 .nodes = { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4 },
1336};
1337
1338static struct qcom_icc_bcm bcm_co0 = {
1339 .name = "CO0",
1340 .keepalive = false,
1341 .num_nodes = 1,
1342 .nodes = { &qns_nsp_gemnoc },
1343};
1344
1345static struct qcom_icc_bcm bcm_co3 = {
1346 .name = "CO3",
1347 .keepalive = false,
1348 .num_nodes = 1,
1349 .nodes = { &qxm_nsp },
1350};
1351
1352static struct qcom_icc_bcm bcm_mc0 = {
1353 .name = "MC0",
1354 .keepalive = true,
1355 .num_nodes = 1,
1356 .nodes = { &ebi },
1357};
1358
1359static struct qcom_icc_bcm bcm_mm0 = {
1360 .name = "MM0",
1361 .keepalive = true,
1362 .num_nodes = 1,
1363 .nodes = { &qns_mem_noc_hf },
1364};
1365
1366static struct qcom_icc_bcm bcm_mm1 = {
1367 .name = "MM1",
1368 .keepalive = false,
1369 .num_nodes = 3,
1370 .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 },
1371};
1372
1373static struct qcom_icc_bcm bcm_mm4 = {
1374 .name = "MM4",
1375 .keepalive = false,
1376 .num_nodes = 1,
1377 .nodes = { &qns_mem_noc_sf },
1378};
1379
1380static struct qcom_icc_bcm bcm_mm5 = {
1381 .name = "MM5",
1382 .keepalive = false,
1383 .num_nodes = 6,
1384 .nodes = { &qnm_camnoc_icp,
1385 &qnm_camnoc_sf,
1386 &qnm_video0,
1387 &qnm_video1,
1388 &qnm_video_cvp,
1389 &qxm_rot
1390 },
1391};
1392
1393static struct qcom_icc_bcm bcm_sh0 = {
1394 .name = "SH0",
1395 .keepalive = true,
1396 .num_nodes = 1,
1397 .nodes = { &qns_llcc },
1398};
1399
1400static struct qcom_icc_bcm bcm_sh2 = {
1401 .name = "SH2",
1402 .keepalive = false,
1403 .num_nodes = 2,
1404 .nodes = { &alm_gpu_tcu, &alm_sys_tcu },
1405};
1406
1407static struct qcom_icc_bcm bcm_sh3 = {
1408 .name = "SH3",
1409 .keepalive = false,
1410 .num_nodes = 1,
1411 .nodes = { &qnm_cmpnoc },
1412};
1413
1414static struct qcom_icc_bcm bcm_sh4 = {
1415 .name = "SH4",
1416 .keepalive = false,
1417 .num_nodes = 1,
1418 .nodes = { &chm_apps },
1419};
1420
1421static struct qcom_icc_bcm bcm_sn0 = {
1422 .name = "SN0",
1423 .keepalive = true,
1424 .num_nodes = 1,
1425 .nodes = { &qns_gemnoc_sf },
1426};
1427
1428static struct qcom_icc_bcm bcm_sn2 = {
1429 .name = "SN2",
1430 .keepalive = false,
1431 .num_nodes = 1,
1432 .nodes = { &qns_gemnoc_gc },
1433};
1434
1435static struct qcom_icc_bcm bcm_sn3 = {
1436 .name = "SN3",
1437 .keepalive = false,
1438 .num_nodes = 1,
1439 .nodes = { &qxs_pimem },
1440};
1441
1442static struct qcom_icc_bcm bcm_sn4 = {
1443 .name = "SN4",
1444 .keepalive = false,
1445 .num_nodes = 1,
1446 .nodes = { &xs_qdss_stm },
1447};
1448
1449static struct qcom_icc_bcm bcm_sn5 = {
1450 .name = "SN5",
1451 .keepalive = false,
1452 .num_nodes = 1,
1453 .nodes = { &xm_pcie3_0 },
1454};
1455
1456static struct qcom_icc_bcm bcm_sn6 = {
1457 .name = "SN6",
1458 .keepalive = false,
1459 .num_nodes = 1,
1460 .nodes = { &xm_pcie3_1 },
1461};
1462
1463static struct qcom_icc_bcm bcm_sn7 = {
1464 .name = "SN7",
1465 .keepalive = false,
1466 .num_nodes = 1,
1467 .nodes = { &qnm_aggre1_noc },
1468};
1469
1470static struct qcom_icc_bcm bcm_sn8 = {
1471 .name = "SN8",
1472 .keepalive = false,
1473 .num_nodes = 1,
1474 .nodes = { &qnm_aggre2_noc },
1475};
1476
1477static struct qcom_icc_bcm bcm_sn14 = {
1478 .name = "SN14",
1479 .keepalive = false,
1480 .num_nodes = 1,
1481 .nodes = { &qns_pcie_mem_noc },
1482};
1483
1484static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1485};
1486
1487static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1488 [MASTER_QSPI_0] = &qhm_qspi,
1489 [MASTER_QUP_1] = &qhm_qup1,
1490 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
1491 [MASTER_SDCC_4] = &xm_sdc4,
1492 [MASTER_UFS_MEM] = &xm_ufs_mem,
1493 [MASTER_USB3_0] = &xm_usb3_0,
1494 [MASTER_USB3_1] = &xm_usb3_1,
1495 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1496 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1497};
1498
1499static const struct qcom_icc_desc sm8350_aggre1_noc = {
1500 .nodes = aggre1_noc_nodes,
1501 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1502 .bcms = aggre1_noc_bcms,
1503 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1504};
1505
1506static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1507 &bcm_ce0,
1508 &bcm_sn5,
1509 &bcm_sn6,
1510 &bcm_sn14,
1511};
1512
1513static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1514 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1515 [MASTER_QUP_0] = &qhm_qup0,
1516 [MASTER_QUP_2] = &qhm_qup2,
1517 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
1518 [MASTER_CRYPTO] = &qxm_crypto,
1519 [MASTER_IPA] = &qxm_ipa,
1520 [MASTER_PCIE_0] = &xm_pcie3_0,
1521 [MASTER_PCIE_1] = &xm_pcie3_1,
1522 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1523 [MASTER_SDCC_2] = &xm_sdc2,
1524 [MASTER_UFS_CARD] = &xm_ufs_card,
1525 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1526 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1527 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1528};
1529
1530static const struct qcom_icc_desc sm8350_aggre2_noc = {
1531 .nodes = aggre2_noc_nodes,
1532 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1533 .bcms = aggre2_noc_bcms,
1534 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1535};
1536
1537static struct qcom_icc_bcm * const config_noc_bcms[] = {
1538 &bcm_cn0,
1539 &bcm_cn1,
1540 &bcm_cn2,
1541 &bcm_sn3,
1542 &bcm_sn4,
1543};
1544
1545static struct qcom_icc_node * const config_noc_nodes[] = {
1546 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1547 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1548 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1549 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1550 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1551 [SLAVE_AOSS] = &qhs_aoss,
1552 [SLAVE_APPSS] = &qhs_apss,
1553 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1554 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1555 [SLAVE_CDSP_CFG] = &qhs_compute_cfg,
1556 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1557 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1558 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1559 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1560 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1561 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1562 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1563 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1564 [SLAVE_HWKM] = &qhs_hwkm,
1565 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1566 [SLAVE_IPA_CFG] = &qhs_ipa,
1567 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1568 [SLAVE_LPASS] = &qhs_lpass_cfg,
1569 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1570 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1571 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1572 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1573 [SLAVE_PDM] = &qhs_pdm,
1574 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1575 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
1576 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
1577 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1578 [SLAVE_QSPI_0] = &qhs_qspi,
1579 [SLAVE_QUP_0] = &qhs_qup0,
1580 [SLAVE_QUP_1] = &qhs_qup1,
1581 [SLAVE_QUP_2] = &qhs_qup2,
1582 [SLAVE_SDCC_2] = &qhs_sdc2,
1583 [SLAVE_SDCC_4] = &qhs_sdc4,
1584 [SLAVE_SECURITY] = &qhs_security,
1585 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1586 [SLAVE_TCSR] = &qhs_tcsr,
1587 [SLAVE_TLMM] = &qhs_tlmm,
1588 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
1589 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1590 [SLAVE_USB3_0] = &qhs_usb3_0,
1591 [SLAVE_USB3_1] = &qhs_usb3_1,
1592 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1593 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1594 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
1595 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
1596 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1597 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
1598 [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1599 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1600 [SLAVE_IMEM] = &qxs_imem,
1601 [SLAVE_PIMEM] = &qxs_pimem,
1602 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1603 [SLAVE_PCIE_0] = &xs_pcie_0,
1604 [SLAVE_PCIE_1] = &xs_pcie_1,
1605 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1606 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1607};
1608
1609static const struct qcom_icc_desc sm8350_config_noc = {
1610 .nodes = config_noc_nodes,
1611 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1612 .bcms = config_noc_bcms,
1613 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1614};
1615
1616static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1617};
1618
1619static struct qcom_icc_node * const dc_noc_nodes[] = {
1620 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
1621 [SLAVE_LLCC_CFG] = &qhs_llcc,
1622 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
1623};
1624
1625static const struct qcom_icc_desc sm8350_dc_noc = {
1626 .nodes = dc_noc_nodes,
1627 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1628 .bcms = dc_noc_bcms,
1629 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
1630};
1631
1632static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1633 &bcm_sh0,
1634 &bcm_sh2,
1635 &bcm_sh3,
1636 &bcm_sh4,
1637};
1638
1639static struct qcom_icc_node * const gem_noc_nodes[] = {
1640 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1641 [MASTER_SYS_TCU] = &alm_sys_tcu,
1642 [MASTER_APPSS_PROC] = &chm_apps,
1643 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1644 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
1645 [MASTER_GFX3D] = &qnm_gpu,
1646 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1647 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1648 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1649 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1650 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1651 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1652 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
1653 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1654 [SLAVE_LLCC] = &qns_llcc,
1655 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1656 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
1657 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
1658 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
1659};
1660
1661static const struct qcom_icc_desc sm8350_gem_noc = {
1662 .nodes = gem_noc_nodes,
1663 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1664 .bcms = gem_noc_bcms,
1665 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1666};
1667
1668static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1669};
1670
1671static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1672 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1673 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1674 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1675 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1676 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1677 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1678 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1679};
1680
1681static const struct qcom_icc_desc sm8350_lpass_ag_noc = {
1682 .nodes = lpass_ag_noc_nodes,
1683 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1684 .bcms = lpass_ag_noc_bcms,
1685 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1686};
1687
1688static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1689 &bcm_acv,
1690 &bcm_mc0,
1691};
1692
1693static struct qcom_icc_node * const mc_virt_nodes[] = {
1694 [MASTER_LLCC] = &llcc_mc,
1695 [SLAVE_EBI1] = &ebi,
1696};
1697
1698static const struct qcom_icc_desc sm8350_mc_virt = {
1699 .nodes = mc_virt_nodes,
1700 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1701 .bcms = mc_virt_bcms,
1702 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1703};
1704
1705static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1706 &bcm_mm0,
1707 &bcm_mm1,
1708 &bcm_mm4,
1709 &bcm_mm5,
1710};
1711
1712static struct qcom_icc_node * const mmss_noc_nodes[] = {
1713 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1714 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1715 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1716 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
1717 [MASTER_VIDEO_P0] = &qnm_video0,
1718 [MASTER_VIDEO_P1] = &qnm_video1,
1719 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
1720 [MASTER_MDP0] = &qxm_mdp0,
1721 [MASTER_MDP1] = &qxm_mdp1,
1722 [MASTER_ROTATOR] = &qxm_rot,
1723 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1724 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1725 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1726};
1727
1728static const struct qcom_icc_desc sm8350_mmss_noc = {
1729 .nodes = mmss_noc_nodes,
1730 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1731 .bcms = mmss_noc_bcms,
1732 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1733};
1734
1735static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1736 &bcm_co0,
1737 &bcm_co3,
1738};
1739
1740static struct qcom_icc_node * const nsp_noc_nodes[] = {
1741 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
1742 [MASTER_CDSP_PROC] = &qxm_nsp,
1743 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1744 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
1745};
1746
1747static const struct qcom_icc_desc sm8350_compute_noc = {
1748 .nodes = nsp_noc_nodes,
1749 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1750 .bcms = nsp_noc_bcms,
1751 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1752};
1753
1754static struct qcom_icc_bcm * const system_noc_bcms[] = {
1755 &bcm_sn0,
1756 &bcm_sn2,
1757 &bcm_sn7,
1758 &bcm_sn8,
1759};
1760
1761static struct qcom_icc_node * const system_noc_nodes[] = {
1762 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1763 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1764 [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
1765 [MASTER_PIMEM] = &qxm_pimem,
1766 [MASTER_GIC] = &xm_gic,
1767 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1768 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1769 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1770};
1771
1772static const struct qcom_icc_desc sm8350_system_noc = {
1773 .nodes = system_noc_nodes,
1774 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1775 .bcms = system_noc_bcms,
1776 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1777};
1778
1779static const struct of_device_id qnoc_of_match[] = {
1780 { .compatible = "qcom,sm8350-aggre1-noc", .data = &sm8350_aggre1_noc},
1781 { .compatible = "qcom,sm8350-aggre2-noc", .data = &sm8350_aggre2_noc},
1782 { .compatible = "qcom,sm8350-config-noc", .data = &sm8350_config_noc},
1783 { .compatible = "qcom,sm8350-dc-noc", .data = &sm8350_dc_noc},
1784 { .compatible = "qcom,sm8350-gem-noc", .data = &sm8350_gem_noc},
1785 { .compatible = "qcom,sm8350-lpass-ag-noc", .data = &sm8350_lpass_ag_noc},
1786 { .compatible = "qcom,sm8350-mc-virt", .data = &sm8350_mc_virt},
1787 { .compatible = "qcom,sm8350-mmss-noc", .data = &sm8350_mmss_noc},
1788 { .compatible = "qcom,sm8350-compute-noc", .data = &sm8350_compute_noc},
1789 { .compatible = "qcom,sm8350-system-noc", .data = &sm8350_system_noc},
1790 { }
1791};
1792MODULE_DEVICE_TABLE(of, qnoc_of_match);
1793
1794static struct platform_driver qnoc_driver = {
1795 .probe = qcom_icc_rpmh_probe,
1796 .remove = qcom_icc_rpmh_remove,
1797 .driver = {
1798 .name = "qnoc-sm8350",
1799 .of_match_table = qnoc_of_match,
1800 .sync_state = icc_sync_state,
1801 },
1802};
1803module_platform_driver(qnoc_driver);
1804
1805MODULE_DESCRIPTION("SM8350 NoC driver");
1806MODULE_LICENSE("GPL v2");