tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2-peripheral-props.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Peripheral Properties for Qualcomm External Bus Interface 2 (EBI2)
8
9maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11
12properties:
13 # SLOW chip selects
14 qcom,xmem-recovery-cycles:
15 $ref: /schemas/types.yaml#/definitions/uint32
16 description: >
17 The time the memory continues to drive the data bus after OE
18 is de-asserted, in order to avoid contention on the data bus.
19 They are inserted when reading one CS and switching to another
20 CS or read followed by write on the same CS. Minimum value is
21 actually 1, so a value of 0 will still yield 1 recovery cycle.
22 minimum: 0
23 maximum: 15
24
25 qcom,xmem-write-hold-cycles:
26 $ref: /schemas/types.yaml#/definitions/uint32
27 description: >
28 The extra cycles inserted after every write minimum 1. The
29 data out is driven from the time WE is asserted until CS is
30 asserted. With a hold of 1 (value = 0), the CS stays active
31 for 1 extra cycle, etc.
32 minimum: 0
33 maximum: 15
34
35 qcom,xmem-write-delta-cycles:
36 $ref: /schemas/types.yaml#/definitions/uint32
37 description: >
38 The initial latency for write cycles inserted for the first
39 write to a page or burst memory.
40 minimum: 0
41 maximum: 255
42
43 qcom,xmem-read-delta-cycles:
44 $ref: /schemas/types.yaml#/definitions/uint32
45 description: >
46 The initial latency for read cycles inserted for the first
47 read to a page or burst memory.
48 minimum: 0
49 maximum: 255
50
51 qcom,xmem-write-wait-cycles:
52 $ref: /schemas/types.yaml#/definitions/uint32
53 description: >
54 The number of wait cycles for every write access.
55 minimum: 0
56 maximum: 15
57
58 qcom,xmem-read-wait-cycles:
59 $ref: /schemas/types.yaml#/definitions/uint32
60 description: >
61 The number of wait cycles for every read access.
62 minimum: 0
63 maximum: 15
64
65 # FAST chip selects
66 qcom,xmem-address-hold-enable:
67 $ref: /schemas/types.yaml#/definitions/uint32
68 description: >
69 Holds the address for an extra cycle to meet hold time
70 requirements with ADV assertion, when set to 1.
71 enum: [ 0, 1 ]
72
73 qcom,xmem-adv-to-oe-recovery-cycles:
74 $ref: /schemas/types.yaml#/definitions/uint32
75 description: >
76 The number of cycles elapsed before an OE assertion, with
77 respect to the cycle where ADV (address valid) is asserted.
78 minimum: 0
79 maximum: 3
80
81 qcom,xmem-read-hold-cycles:
82 $ref: /schemas/types.yaml#/definitions/uint32
83 description: >
84 The length in cycles of the first segment of a read transfer.
85 For a single read transfer this will be the time from CS
86 assertion to OE assertion.
87 minimum: 0
88 maximum: 15
89
90additionalProperties: true