tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2/*
3 * Copyright (c) 2022, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
5 * Copyright (c) 2024, Linaro Ltd.
6 */
7
8#ifndef _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H
9#define _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H
10
11/* DISP_CC clocks */
12#define DISP_CC_ESYNC0_CLK 0
13#define DISP_CC_ESYNC0_CLK_SRC 1
14#define DISP_CC_ESYNC1_CLK 2
15#define DISP_CC_ESYNC1_CLK_SRC 3
16#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4
17#define DISP_CC_MDSS_AHB1_CLK 5
18#define DISP_CC_MDSS_AHB_CLK 6
19#define DISP_CC_MDSS_AHB_CLK_SRC 7
20#define DISP_CC_MDSS_BYTE0_CLK 8
21#define DISP_CC_MDSS_BYTE0_CLK_SRC 9
22#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 10
23#define DISP_CC_MDSS_BYTE0_INTF_CLK 11
24#define DISP_CC_MDSS_BYTE1_CLK 12
25#define DISP_CC_MDSS_BYTE1_CLK_SRC 13
26#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 14
27#define DISP_CC_MDSS_BYTE1_INTF_CLK 15
28#define DISP_CC_MDSS_DPTX0_AUX_CLK 16
29#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 17
30#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 18
31#define DISP_CC_MDSS_DPTX0_LINK_CLK 19
32#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 20
33#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 21
34#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 22
35#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 23
36#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 24
37#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 25
38#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 26
39#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 27
40#define DISP_CC_MDSS_DPTX1_AUX_CLK 28
41#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 29
42#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 30
43#define DISP_CC_MDSS_DPTX1_LINK_CLK 31
44#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 32
45#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 33
46#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 34
47#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 35
48#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 36
49#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 37
50#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 38
51#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 39
52#define DISP_CC_MDSS_DPTX2_AUX_CLK 40
53#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 41
54#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 42
55#define DISP_CC_MDSS_DPTX2_LINK_CLK 43
56#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 44
57#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 45
58#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 46
59#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 47
60#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 48
61#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 49
62#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 50
63#define DISP_CC_MDSS_DPTX3_AUX_CLK 51
64#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 52
65#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 53
66#define DISP_CC_MDSS_DPTX3_LINK_CLK 54
67#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 55
68#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 56
69#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 57
70#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 58
71#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 59
72#define DISP_CC_MDSS_ESC0_CLK 60
73#define DISP_CC_MDSS_ESC0_CLK_SRC 61
74#define DISP_CC_MDSS_ESC1_CLK 62
75#define DISP_CC_MDSS_ESC1_CLK_SRC 63
76#define DISP_CC_MDSS_MDP1_CLK 64
77#define DISP_CC_MDSS_MDP_CLK 65
78#define DISP_CC_MDSS_MDP_CLK_SRC 66
79#define DISP_CC_MDSS_MDP_LUT1_CLK 67
80#define DISP_CC_MDSS_MDP_LUT_CLK 68
81#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 69
82#define DISP_CC_MDSS_PCLK0_CLK 70
83#define DISP_CC_MDSS_PCLK0_CLK_SRC 71
84#define DISP_CC_MDSS_PCLK1_CLK 72
85#define DISP_CC_MDSS_PCLK1_CLK_SRC 73
86#define DISP_CC_MDSS_PCLK2_CLK 74
87#define DISP_CC_MDSS_PCLK2_CLK_SRC 75
88#define DISP_CC_MDSS_RSCC_AHB_CLK 76
89#define DISP_CC_MDSS_RSCC_VSYNC_CLK 77
90#define DISP_CC_MDSS_VSYNC1_CLK 78
91#define DISP_CC_MDSS_VSYNC_CLK 79
92#define DISP_CC_MDSS_VSYNC_CLK_SRC 80
93#define DISP_CC_OSC_CLK 81
94#define DISP_CC_OSC_CLK_SRC 82
95#define DISP_CC_PLL0 83
96#define DISP_CC_PLL1 84
97#define DISP_CC_PLL2 85
98#define DISP_CC_SLEEP_CLK 86
99#define DISP_CC_SLEEP_CLK_SRC 87
100#define DISP_CC_XO_CLK 88
101#define DISP_CC_XO_CLK_SRC 89
102
103/* DISP_CC resets */
104#define DISP_CC_MDSS_CORE_BCR 0
105#define DISP_CC_MDSS_CORE_INT2_BCR 1
106#define DISP_CC_MDSS_RSCC_BCR 2
107
108/* DISP_CC GDSCR */
109#define MDSS_GDSC 0
110#define MDSS_INT2_GDSC 1
111
112#endif