tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
3 */
4#ifndef __QCOM_SCM_INT_H
5#define __QCOM_SCM_INT_H
6
7struct device;
8struct qcom_tzmem_pool;
9
10enum qcom_scm_convention {
11 SMC_CONVENTION_UNKNOWN,
12 SMC_CONVENTION_LEGACY,
13 SMC_CONVENTION_ARM_32,
14 SMC_CONVENTION_ARM_64,
15};
16
17extern enum qcom_scm_convention qcom_scm_convention;
18
19#define MAX_QCOM_SCM_ARGS 10
20#define MAX_QCOM_SCM_RETS 3
21
22enum qcom_scm_arg_types {
23 QCOM_SCM_VAL,
24 QCOM_SCM_RO,
25 QCOM_SCM_RW,
26 QCOM_SCM_BUFVAL,
27};
28
29#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
30 (((a) & 0x3) << 4) | \
31 (((b) & 0x3) << 6) | \
32 (((c) & 0x3) << 8) | \
33 (((d) & 0x3) << 10) | \
34 (((e) & 0x3) << 12) | \
35 (((f) & 0x3) << 14) | \
36 (((g) & 0x3) << 16) | \
37 (((h) & 0x3) << 18) | \
38 (((i) & 0x3) << 20) | \
39 (((j) & 0x3) << 22) | \
40 ((num) & 0xf))
41
42#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
43
44
45/**
46 * struct qcom_scm_desc
47 * @svc: Service identifier
48 * @cmd: Command identifier
49 * @arginfo: Metadata describing the arguments in args[]
50 * @args: The array of arguments for the secure syscall
51 * @owner: Owner identifier
52 */
53struct qcom_scm_desc {
54 u32 svc;
55 u32 cmd;
56 u32 arginfo;
57 u64 args[MAX_QCOM_SCM_ARGS];
58 u32 owner;
59};
60
61/**
62 * struct qcom_scm_res
63 * @result: The values returned by the secure syscall
64 */
65struct qcom_scm_res {
66 u64 result[MAX_QCOM_SCM_RETS];
67};
68
69int qcom_scm_wait_for_wq_completion(u32 wq_ctx);
70int scm_get_wq_ctx(u32 *wq_ctx, u32 *flags, u32 *more_pending);
71
72#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
73int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
74 enum qcom_scm_convention qcom_convention,
75 struct qcom_scm_res *res, bool atomic);
76#define scm_smc_call(dev, desc, res, atomic) \
77 __scm_smc_call((dev), (desc), qcom_scm_convention, (res), (atomic))
78
79#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))
80int scm_legacy_call_atomic(struct device *dev, const struct qcom_scm_desc *desc,
81 struct qcom_scm_res *res);
82int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
83 struct qcom_scm_res *res);
84
85struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void);
86int qcom_scm_shm_bridge_enable(struct device *scm_dev);
87
88#define QCOM_SCM_SVC_BOOT 0x01
89#define QCOM_SCM_BOOT_SET_ADDR 0x01
90#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
91#define QCOM_SCM_BOOT_SDI_CONFIG 0x09
92#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
93#define QCOM_SCM_BOOT_SET_ADDR_MC 0x11
94#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
95#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
96#define QCOM_SCM_BOOT_MAX_CPUS 4
97#define QCOM_SCM_BOOT_MC_FLAG_AARCH64 BIT(0)
98#define QCOM_SCM_BOOT_MC_FLAG_COLDBOOT BIT(1)
99#define QCOM_SCM_BOOT_MC_FLAG_WARMBOOT BIT(2)
100
101#define QCOM_SCM_SVC_PIL 0x02
102#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
103#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
104#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
105#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
106#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
107#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
108
109#define QCOM_SCM_SVC_IO 0x05
110#define QCOM_SCM_IO_READ 0x01
111#define QCOM_SCM_IO_WRITE 0x02
112
113#define QCOM_SCM_SVC_INFO 0x06
114#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
115
116#define QCOM_SCM_SVC_MP 0x0c
117#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
118#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
119#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
120#define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE 0x05
121#define QCOM_SCM_MP_VIDEO_VAR 0x08
122#define QCOM_SCM_MP_ASSIGN 0x16
123#define QCOM_SCM_MP_CP_SMMU_APERTURE_ID 0x1b
124#define QCOM_SCM_MP_SHM_BRIDGE_ENABLE 0x1c
125#define QCOM_SCM_MP_SHM_BRIDGE_DELETE 0x1d
126#define QCOM_SCM_MP_SHM_BRIDGE_CREATE 0x1e
127
128#define QCOM_SCM_SVC_OCMEM 0x0f
129#define QCOM_SCM_OCMEM_LOCK_CMD 0x01
130#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
131
132#define QCOM_SCM_SVC_ES 0x10 /* Enterprise Security */
133#define QCOM_SCM_ES_INVALIDATE_ICE_KEY 0x03
134#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY 0x04
135#define QCOM_SCM_ES_DERIVE_SW_SECRET 0x07
136#define QCOM_SCM_ES_GENERATE_ICE_KEY 0x08
137#define QCOM_SCM_ES_PREPARE_ICE_KEY 0x09
138#define QCOM_SCM_ES_IMPORT_ICE_KEY 0x0a
139
140#define QCOM_SCM_SVC_HDCP 0x11
141#define QCOM_SCM_HDCP_INVOKE 0x01
142
143#define QCOM_SCM_SVC_LMH 0x13
144#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01
145#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10
146
147#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
148#define QCOM_SCM_SMMU_PT_FORMAT 0x01
149#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
150#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
151
152#define QCOM_SCM_SVC_WAITQ 0x24
153#define QCOM_SCM_WAITQ_RESUME 0x02
154#define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03
155
156#define QCOM_SCM_SVC_GPU 0x28
157#define QCOM_SCM_SVC_GPU_INIT_REGS 0x01
158
159/* ARM_SMCCC_OWNER_TRUSTED_OS calls */
160
161#define QCOM_SCM_SVC_SMCINVOKE 0x06
162#define QCOM_SCM_SMCINVOKE_INVOKE_LEGACY 0x00
163#define QCOM_SCM_SMCINVOKE_CB_RSP 0x01
164#define QCOM_SCM_SMCINVOKE_INVOKE 0x02
165
166/* common error codes */
167#define QCOM_SCM_V2_EBUSY -12
168#define QCOM_SCM_ENOMEM -5
169#define QCOM_SCM_EOPNOTSUPP -4
170#define QCOM_SCM_EINVAL_ADDR -3
171#define QCOM_SCM_EINVAL_ARG -2
172#define QCOM_SCM_ERROR -1
173#define QCOM_SCM_INTERRUPTED 1
174#define QCOM_SCM_WAITQ_SLEEP 2
175
176static inline int qcom_scm_remap_error(int err)
177{
178 switch (err) {
179 case QCOM_SCM_ERROR:
180 return -EIO;
181 case QCOM_SCM_EINVAL_ADDR:
182 case QCOM_SCM_EINVAL_ARG:
183 return -EINVAL;
184 case QCOM_SCM_EOPNOTSUPP:
185 return -EOPNOTSUPP;
186 case QCOM_SCM_ENOMEM:
187 return -ENOMEM;
188 case QCOM_SCM_V2_EBUSY:
189 return -EBUSY;
190 }
191 return -EINVAL;
192}
193
194#endif