tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
3#define DT_BINDINGS_MEMORY_TEGRA210_MC_H
4
5#define TEGRA_SWGROUP_PTC 0
6#define TEGRA_SWGROUP_DC 1
7#define TEGRA_SWGROUP_DCB 2
8#define TEGRA_SWGROUP_AFI 3
9#define TEGRA_SWGROUP_AVPC 4
10#define TEGRA_SWGROUP_HDA 5
11#define TEGRA_SWGROUP_HC 6
12#define TEGRA_SWGROUP_NVENC 7
13#define TEGRA_SWGROUP_PPCS 8
14#define TEGRA_SWGROUP_SATA 9
15#define TEGRA_SWGROUP_MPCORE 10
16#define TEGRA_SWGROUP_ISP2 11
17#define TEGRA_SWGROUP_XUSB_HOST 12
18#define TEGRA_SWGROUP_XUSB_DEV 13
19#define TEGRA_SWGROUP_ISP2B 14
20#define TEGRA_SWGROUP_TSEC 15
21#define TEGRA_SWGROUP_A9AVP 16
22#define TEGRA_SWGROUP_GPU 17
23#define TEGRA_SWGROUP_SDMMC1A 18
24#define TEGRA_SWGROUP_SDMMC2A 19
25#define TEGRA_SWGROUP_SDMMC3A 20
26#define TEGRA_SWGROUP_SDMMC4A 21
27#define TEGRA_SWGROUP_VIC 22
28#define TEGRA_SWGROUP_VI 23
29#define TEGRA_SWGROUP_NVDEC 24
30#define TEGRA_SWGROUP_APE 25
31#define TEGRA_SWGROUP_NVJPG 26
32#define TEGRA_SWGROUP_SE 27
33#define TEGRA_SWGROUP_AXIAP 28
34#define TEGRA_SWGROUP_ETR 29
35#define TEGRA_SWGROUP_TSECB 30
36#define TEGRA_SWGROUP_NV 31
37#define TEGRA_SWGROUP_NV2 32
38#define TEGRA_SWGROUP_PPCS1 33
39#define TEGRA_SWGROUP_DC1 34
40#define TEGRA_SWGROUP_PPCS2 35
41#define TEGRA_SWGROUP_HC1 36
42#define TEGRA_SWGROUP_SE1 37
43#define TEGRA_SWGROUP_TSEC1 38
44#define TEGRA_SWGROUP_TSECB1 39
45#define TEGRA_SWGROUP_NVDEC1 40
46
47#define TEGRA210_MC_RESET_AFI 0
48#define TEGRA210_MC_RESET_AVPC 1
49#define TEGRA210_MC_RESET_DC 2
50#define TEGRA210_MC_RESET_DCB 3
51#define TEGRA210_MC_RESET_HC 4
52#define TEGRA210_MC_RESET_HDA 5
53#define TEGRA210_MC_RESET_ISP2 6
54#define TEGRA210_MC_RESET_MPCORE 7
55#define TEGRA210_MC_RESET_NVENC 8
56#define TEGRA210_MC_RESET_PPCS 9
57#define TEGRA210_MC_RESET_SATA 10
58#define TEGRA210_MC_RESET_VI 11
59#define TEGRA210_MC_RESET_VIC 12
60#define TEGRA210_MC_RESET_XUSB_HOST 13
61#define TEGRA210_MC_RESET_XUSB_DEV 14
62#define TEGRA210_MC_RESET_A9AVP 15
63#define TEGRA210_MC_RESET_TSEC 16
64#define TEGRA210_MC_RESET_SDMMC1 17
65#define TEGRA210_MC_RESET_SDMMC2 18
66#define TEGRA210_MC_RESET_SDMMC3 19
67#define TEGRA210_MC_RESET_SDMMC4 20
68#define TEGRA210_MC_RESET_ISP2B 21
69#define TEGRA210_MC_RESET_GPU 22
70#define TEGRA210_MC_RESET_NVDEC 23
71#define TEGRA210_MC_RESET_APE 24
72#define TEGRA210_MC_RESET_SE 25
73#define TEGRA210_MC_RESET_NVJPG 26
74#define TEGRA210_MC_RESET_AXIAP 27
75#define TEGRA210_MC_RESET_ETR 28
76#define TEGRA210_MC_RESET_TSECB 29
77
78#define TEGRA210_MC_PTCR 0
79#define TEGRA210_MC_DISPLAY0A 1
80#define TEGRA210_MC_DISPLAY0AB 2
81#define TEGRA210_MC_DISPLAY0B 3
82#define TEGRA210_MC_DISPLAY0BB 4
83#define TEGRA210_MC_DISPLAY0C 5
84#define TEGRA210_MC_DISPLAY0CB 6
85#define TEGRA210_MC_AFIR 14
86#define TEGRA210_MC_AVPCARM7R 15
87#define TEGRA210_MC_DISPLAYHC 16
88#define TEGRA210_MC_DISPLAYHCB 17
89#define TEGRA210_MC_HDAR 21
90#define TEGRA210_MC_HOST1XDMAR 22
91#define TEGRA210_MC_HOST1XR 23
92#define TEGRA210_MC_NVENCSRD 28
93#define TEGRA210_MC_PPCSAHBDMAR 29
94#define TEGRA210_MC_PPCSAHBSLVR 30
95#define TEGRA210_MC_SATAR 31
96#define TEGRA210_MC_MPCORER 39
97#define TEGRA210_MC_NVENCSWR 43
98#define TEGRA210_MC_AFIW 49
99#define TEGRA210_MC_AVPCARM7W 50
100#define TEGRA210_MC_HDAW 53
101#define TEGRA210_MC_HOST1XW 54
102#define TEGRA210_MC_MPCOREW 57
103#define TEGRA210_MC_PPCSAHBDMAW 59
104#define TEGRA210_MC_PPCSAHBSLVW 60
105#define TEGRA210_MC_SATAW 61
106#define TEGRA210_MC_ISPRA 68
107#define TEGRA210_MC_ISPWA 70
108#define TEGRA210_MC_ISPWB 71
109#define TEGRA210_MC_XUSB_HOSTR 74
110#define TEGRA210_MC_XUSB_HOSTW 75
111#define TEGRA210_MC_XUSB_DEVR 76
112#define TEGRA210_MC_XUSB_DEVW 77
113#define TEGRA210_MC_ISPRAB 78
114#define TEGRA210_MC_ISPWAB 80
115#define TEGRA210_MC_ISPWBB 81
116#define TEGRA210_MC_TSECSRD 84
117#define TEGRA210_MC_TSECSWR 85
118#define TEGRA210_MC_A9AVPSCR 86
119#define TEGRA210_MC_A9AVPSCW 87
120#define TEGRA210_MC_GPUSRD 88
121#define TEGRA210_MC_GPUSWR 89
122#define TEGRA210_MC_DISPLAYT 90
123#define TEGRA210_MC_SDMMCRA 96
124#define TEGRA210_MC_SDMMCRAA 97
125#define TEGRA210_MC_SDMMCR 98
126#define TEGRA210_MC_SDMMCRAB 99
127#define TEGRA210_MC_SDMMCWA 100
128#define TEGRA210_MC_SDMMCWAA 101
129#define TEGRA210_MC_SDMMCW 102
130#define TEGRA210_MC_SDMMCWAB 103
131#define TEGRA210_MC_VICSRD 108
132#define TEGRA210_MC_VICSWR 109
133#define TEGRA210_MC_VIW 114
134#define TEGRA210_MC_DISPLAYD 115
135#define TEGRA210_MC_NVDECSRD 120
136#define TEGRA210_MC_NVDECSWR 121
137#define TEGRA210_MC_APER 122
138#define TEGRA210_MC_APEW 123
139#define TEGRA210_MC_NVJPGRD 126
140#define TEGRA210_MC_NVJPGWR 127
141#define TEGRA210_MC_SESRD 128
142#define TEGRA210_MC_SESWR 129
143#define TEGRA210_MC_AXIAPR 130
144#define TEGRA210_MC_AXIAPW 131
145#define TEGRA210_MC_ETRR 132
146#define TEGRA210_MC_ETRW 133
147#define TEGRA210_MC_TSECSRDB 134
148#define TEGRA210_MC_TSECSWRB 135
149#define TEGRA210_MC_GPUSRD2 136
150#define TEGRA210_MC_GPUSWR2 137
151
152#endif