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Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-cpu-intc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Atheros ath79 CPU interrupt controller
8
9maintainers:
10 - Alban Bedel <albeu@free.fr>
11
12description:
13 On most SoC the IRQ controller need to flush the DDR FIFO before running the
14 interrupt handler of some devices. This is configured using the
15 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
16
17properties:
18 compatible:
19 oneOf:
20 - items:
21 - const: qca,ar9132-cpu-intc
22 - const: qca,ar7100-cpu-intc
23 - items:
24 - const: qca,ar7100-cpu-intc
25
26 interrupt-controller: true
27
28 '#interrupt-cells':
29 const: 1
30
31 qca,ddr-wb-channel-interrupts:
32 description: List of interrupts needing a write buffer flush
33 $ref: /schemas/types.yaml#/definitions/uint32-array
34
35 qca,ddr-wb-channels:
36 description: List of write buffer channel phandles for each interrupt
37 $ref: /schemas/types.yaml#/definitions/phandle-array
38
39required:
40 - compatible
41 - interrupt-controller
42 - '#interrupt-cells'
43
44additionalProperties: false
45
46examples:
47 - |
48 interrupt-controller {
49 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
50
51 interrupt-controller;
52 #interrupt-cells = <1>;
53
54 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
55 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
56 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
57 };
58
59 ddr_ctrl: memory-controller {
60 #qca,ddr-wb-channel-cells = <1>;
61 };