tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Maxim MAX77705 definitions.
4 *
5 * Copyright (C) 2015 Samsung Electronics, Inc.
6 * Copyright (C) 2025 Dzmitry Sankouski <dsankouski@gmail.com>
7 */
8
9#ifndef __MAX77705_CHARGER_H
10#define __MAX77705_CHARGER_H __FILE__
11
12#include <linux/regmap.h>
13
14/* MAX77705_CHG_REG_CHG_INT */
15#define MAX77705_BYP_I (0)
16#define MAX77705_INP_LIMIT_I (1)
17#define MAX77705_BATP_I (2)
18#define MAX77705_BAT_I (3)
19#define MAX77705_CHG_I (4)
20#define MAX77705_WCIN_I (5)
21#define MAX77705_CHGIN_I (6)
22#define MAX77705_AICL_I (7)
23
24/* MAX77705_CHG_REG_CHG_INT_OK */
25#define MAX77705_BYP_OK BIT(MAX77705_BYP_I)
26#define MAX77705_DISQBAT_OK BIT(MAX77705_INP_LIMIT_I)
27#define MAX77705_BATP_OK BIT(MAX77705_BATP_I)
28#define MAX77705_BAT_OK BIT(MAX77705_BAT_I)
29#define MAX77705_CHG_OK BIT(MAX77705_CHG_I)
30#define MAX77705_WCIN_OK BIT(MAX77705_WCIN_I)
31#define MAX77705_CHGIN_OK BIT(MAX77705_CHGIN_I)
32#define MAX77705_AICL_OK BIT(MAX77705_AICL_I)
33
34/* MAX77705_CHG_REG_DETAILS_00 */
35#define MAX77705_BATP_DTLS BIT(0)
36#define MAX77705_WCIN_DTLS GENMASK(4, 3)
37#define MAX77705_WCIN_DTLS_SHIFT 3
38#define MAX77705_CHGIN_DTLS GENMASK(6, 5)
39#define MAX77705_CHGIN_DTLS_SHIFT 5
40
41/* MAX77705_CHG_REG_DETAILS_01 */
42#define MAX77705_CHG_DTLS GENMASK(3, 0)
43#define MAX77705_CHG_DTLS_SHIFT 0
44#define MAX77705_BAT_DTLS GENMASK(6, 4)
45#define MAX77705_BAT_DTLS_SHIFT 4
46
47/* MAX77705_CHG_REG_DETAILS_02 */
48#define MAX77705_BYP_DTLS GENMASK(3, 0)
49#define MAX77705_BYP_DTLS_SHIFT 0
50
51/* MAX77705_CHG_REG_CNFG_00 */
52#define MAX77705_CHG_SHIFT 0
53#define MAX77705_UNO_SHIFT 1
54#define MAX77705_OTG_SHIFT 1
55#define MAX77705_BUCK_SHIFT 2
56#define MAX77705_BOOST_SHIFT 3
57#define MAX77705_WDTEN_SHIFT 4
58#define MAX77705_CHG_MASK BIT(MAX77705_CHG_SHIFT)
59#define MAX77705_UNO_MASK BIT(MAX77705_UNO_SHIFT)
60#define MAX77705_OTG_MASK BIT(MAX77705_OTG_SHIFT)
61#define MAX77705_BUCK_MASK BIT(MAX77705_BUCK_SHIFT)
62#define MAX77705_BOOST_MASK BIT(MAX77705_BOOST_SHIFT)
63#define MAX77705_WDTEN_MASK BIT(MAX77705_WDTEN_SHIFT)
64#define MAX77705_UNO_CTRL (MAX77705_UNO_MASK | MAX77705_BOOST_MASK)
65#define MAX77705_OTG_CTRL (MAX77705_OTG_MASK | MAX77705_BOOST_MASK)
66
67/* MAX77705_CHG_REG_CNFG_01 */
68#define MAX77705_FCHGTIME_DISABLE 0
69#define MAX77705_CHG_RSTRT_DISABLE 0x3
70
71#define MAX77705_CHG_PQEN_DISABLE 0
72#define MAX77705_CHG_PQEN_ENABLE 1
73
74/* MAX77705_CHG_REG_CNFG_02 */
75#define MAX77705_OTG_ILIM_500 0
76#define MAX77705_OTG_ILIM_900 1
77#define MAX77705_OTG_ILIM_1200 2
78#define MAX77705_OTG_ILIM_1500 3
79
80/* MAX77705_CHG_REG_CNFG_03 */
81#define MAX77705_TO_ITH_150MA 0
82#define MAX77705_TO_TIME_30M 3
83#define MAX77705_SYS_TRACK_ENABLE 0
84#define MAX77705_SYS_TRACK_DISABLE 1
85
86/* MAX77705_CHG_REG_CNFG_04 */
87#define MAX77705_CHG_MINVSYS_SHIFT 6
88#define MAX77705_CHG_MINVSYS_MASK GENMASK(7, 6)
89
90/* MAX77705_CHG_REG_CNFG_05 */
91#define MAX77705_B2SOVRC_DISABLE 0
92#define MAX77705_B2SOVRC_4_5A 6
93#define MAX77705_B2SOVRC_4_8A 8
94#define MAX77705_B2SOVRC_5_0A 9
95
96/* MAX77705_CHG_CNFG_06 */
97#define MAX77705_WDTCLR_SHIFT 0
98#define MAX77705_WDTCLR_MASK GENMASK(1, 0)
99#define MAX77705_WDTCLR 1
100#define MAX77705_CHGPROT_UNLOCKED 3
101#define MAX77705_SLOWEST_LX_SLOPE 3
102
103/* MAX77705_CHG_REG_CNFG_07 */
104#define MAX77705_CHG_FMBST 4
105#define MAX77705_REG_FMBST_SHIFT 2
106#define MAX77705_REG_FMBST_MASK BIT(MAX77705_REG_FMBST_SHIFT)
107#define MAX77705_REG_FGSRC_SHIFT 1
108#define MAX77705_REG_FGSRC_MASK BIT(MAX77705_REG_FGSRC_SHIFT)
109
110/* MAX77705_CHG_REG_CNFG_08 */
111#define MAX77705_CHG_FSW_3MHz 0
112#define MAX77705_CHG_FSW_2MHz 1
113#define MAX77705_CHG_FSW_1_5MHz 2
114
115/* MAX77705_CHG_REG_CNFG_09 */
116#define MAX77705_CHG_DISABLE 0
117
118/* MAX77705_CHG_REG_CNFG_12 */
119/* REG=4.5V, UVLO=4.7V */
120#define MAX77705_VCHGIN_4_5 0
121/* REG=4.5V, UVLO=4.7V */
122#define MAX77705_WCIN_4_5 0
123#define MAX77705_DISABLE_SKIP 1
124#define MAX77705_AUTO_SKIP 0
125
126#define AICL_WORK_DELAY_MS 100
127
128/* uA */
129#define MAX77705_CURRENT_CHGIN_STEP 25000
130#define MAX77705_CURRENT_CHG_STEP 50000
131#define MAX77705_CURRENT_CHGIN_MIN 100000
132#define MAX77705_CURRENT_CHGIN_MAX 3200000
133
134enum max77705_field_idx {
135 MAX77705_CHGPROT,
136 MAX77705_CHG_EN,
137 MAX77705_CHG_CC_LIM,
138 MAX77705_CHG_CHGIN_LIM,
139 MAX77705_CHG_CV_PRM,
140 MAX77705_CHG_PQEN,
141 MAX77705_CHG_RSTRT,
142 MAX77705_CHG_WCIN,
143 MAX77705_FCHGTIME,
144 MAX77705_LX_SLOPE,
145 MAX77705_MODE,
146 MAX77705_OTG_ILIM,
147 MAX77705_REG_B2SOVRC,
148 MAX77705_REG_DISKIP,
149 MAX77705_REG_FSW,
150 MAX77705_SYS_TRACK,
151 MAX77705_TO,
152 MAX77705_TO_TIME,
153 MAX77705_VBYPSET,
154 MAX77705_VCHGIN,
155 MAX77705_WCIN,
156 MAX77705_N_REGMAP_FIELDS,
157};
158
159static const struct reg_field max77705_reg_field[MAX77705_N_REGMAP_FIELDS] = {
160 [MAX77705_MODE] = REG_FIELD(MAX77705_CHG_REG_CNFG_00, 0, 3),
161 [MAX77705_FCHGTIME] = REG_FIELD(MAX77705_CHG_REG_CNFG_01, 0, 2),
162 [MAX77705_CHG_RSTRT] = REG_FIELD(MAX77705_CHG_REG_CNFG_01, 4, 5),
163 [MAX77705_CHG_PQEN] = REG_FIELD(MAX77705_CHG_REG_CNFG_01, 7, 7),
164 [MAX77705_CHG_CC_LIM] = REG_FIELD(MAX77705_CHG_REG_CNFG_02, 0, 5),
165 [MAX77705_OTG_ILIM] = REG_FIELD(MAX77705_CHG_REG_CNFG_02, 6, 7),
166 [MAX77705_TO] = REG_FIELD(MAX77705_CHG_REG_CNFG_03, 0, 2),
167 [MAX77705_TO_TIME] = REG_FIELD(MAX77705_CHG_REG_CNFG_03, 3, 5),
168 [MAX77705_SYS_TRACK] = REG_FIELD(MAX77705_CHG_REG_CNFG_03, 7, 7),
169 [MAX77705_CHG_CV_PRM] = REG_FIELD(MAX77705_CHG_REG_CNFG_04, 0, 5),
170 [MAX77705_REG_B2SOVRC] = REG_FIELD(MAX77705_CHG_REG_CNFG_05, 0, 3),
171 [MAX77705_CHGPROT] = REG_FIELD(MAX77705_CHG_REG_CNFG_06, 2, 3),
172 [MAX77705_LX_SLOPE] = REG_FIELD(MAX77705_CHG_REG_CNFG_06, 5, 6),
173 [MAX77705_REG_FSW] = REG_FIELD(MAX77705_CHG_REG_CNFG_08, 0, 1),
174 [MAX77705_CHG_CHGIN_LIM] = REG_FIELD(MAX77705_CHG_REG_CNFG_09, 0, 6),
175 [MAX77705_CHG_EN] = REG_FIELD(MAX77705_CHG_REG_CNFG_09, 7, 7),
176 [MAX77705_CHG_WCIN] = REG_FIELD(MAX77705_CHG_REG_CNFG_10, 0, 5),
177 [MAX77705_VBYPSET] = REG_FIELD(MAX77705_CHG_REG_CNFG_11, 0, 6),
178 [MAX77705_REG_DISKIP] = REG_FIELD(MAX77705_CHG_REG_CNFG_12, 0, 0),
179 [MAX77705_WCIN] = REG_FIELD(MAX77705_CHG_REG_CNFG_12, 1, 2),
180 [MAX77705_VCHGIN] = REG_FIELD(MAX77705_CHG_REG_CNFG_12, 3, 4),
181};
182
183struct max77705_charger_data {
184 struct device *dev;
185 struct regmap *regmap;
186 struct regmap_field *rfield[MAX77705_N_REGMAP_FIELDS];
187 struct power_supply_battery_info *bat_info;
188 struct workqueue_struct *wqueue;
189 struct work_struct chgin_work;
190 struct power_supply *psy_chg;
191};
192
193#endif /* __MAX77705_CHARGER_H */