tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2/*
3 * Author: Yinbo Zhu <zhuyinbo@loongson.cn>
4 * Copyright (C) 2022-2023 Loongson Technology Corporation Limited
5 */
6
7#ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H
8#define __DT_BINDINGS_CLOCK_LOONGSON2_H
9
10#define LOONGSON2_REF_100M 0
11#define LOONGSON2_NODE_PLL 1
12#define LOONGSON2_DDR_PLL 2
13#define LOONGSON2_DC_PLL 3
14#define LOONGSON2_PIX0_PLL 4
15#define LOONGSON2_PIX1_PLL 5
16#define LOONGSON2_NODE_CLK 6
17#define LOONGSON2_HDA_CLK 7
18#define LOONGSON2_GPU_CLK 8
19#define LOONGSON2_DDR_CLK 9
20#define LOONGSON2_GMAC_CLK 10
21#define LOONGSON2_DC_CLK 11
22#define LOONGSON2_APB_CLK 12
23#define LOONGSON2_USB_CLK 13
24#define LOONGSON2_SATA_CLK 14
25#define LOONGSON2_PIX0_CLK 15
26#define LOONGSON2_PIX1_CLK 16
27#define LOONGSON2_BOOT_CLK 17
28#define LOONGSON2_OUT0_GATE 18
29#define LOONGSON2_GMAC_GATE 19
30#define LOONGSON2_RIO_GATE 20
31#define LOONGSON2_DC_GATE 21
32#define LOONGSON2_GPU_GATE 22
33#define LOONGSON2_DDR_GATE 23
34#define LOONGSON2_HDA_GATE 24
35#define LOONGSON2_NODE_GATE 25
36#define LOONGSON2_EMMC_GATE 26
37#define LOONGSON2_PIX0_GATE 27
38#define LOONGSON2_PIX1_GATE 28
39#define LOONGSON2_OUT0_CLK 29
40#define LOONGSON2_RIO_CLK 30
41#define LOONGSON2_EMMC_CLK 31
42#define LOONGSON2_DES_CLK 32
43#define LOONGSON2_I2S_CLK 33
44#define LOONGSON2_MISC_CLK 34
45
46#define LS2K0300_CLK_STABLE 0
47#define LS2K0300_NODE_PLL 1
48#define LS2K0300_DDR_PLL 2
49#define LS2K0300_PIX_PLL 3
50#define LS2K0300_CLK_THSENS 4
51#define LS2K0300_CLK_NODE_DIV 5
52#define LS2K0300_CLK_NODE_PLL_GATE 6
53#define LS2K0300_CLK_NODE_SCALE 7
54#define LS2K0300_CLK_NODE_GATE 8
55#define LS2K0300_CLK_GMAC_DIV 9
56#define LS2K0300_CLK_GMAC_GATE 10
57#define LS2K0300_CLK_I2S_DIV 11
58#define LS2K0300_CLK_I2S_SCALE 12
59#define LS2K0300_CLK_I2S_GATE 13
60#define LS2K0300_CLK_DDR_DIV 14
61#define LS2K0300_CLK_DDR_GATE 15
62#define LS2K0300_CLK_NET_DIV 16
63#define LS2K0300_CLK_NET_GATE 17
64#define LS2K0300_CLK_DEV_DIV 18
65#define LS2K0300_CLK_DEV_GATE 19
66#define LS2K0300_CLK_PIX_DIV 20
67#define LS2K0300_CLK_PIX_PLL_GATE 21
68#define LS2K0300_CLK_PIX_SCALE 22
69#define LS2K0300_CLK_PIX_GATE 23
70#define LS2K0300_CLK_GMACBP_DIV 24
71#define LS2K0300_CLK_GMACBP_GATE 25
72#define LS2K0300_CLK_USB_SCALE 26
73#define LS2K0300_CLK_USB_GATE 27
74#define LS2K0300_CLK_APB_SCALE 28
75#define LS2K0300_CLK_APB_GATE 29
76#define LS2K0300_CLK_BOOT_SCALE 30
77#define LS2K0300_CLK_BOOT_GATE 31
78#define LS2K0300_CLK_SDIO_SCALE 32
79#define LS2K0300_CLK_SDIO_GATE 33
80#define LS2K0300_CLK_GMAC_IN 34
81
82#endif