Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
4 *
5 * Authors:
6 * Peter Pan <peterpandong@micron.com>
7 */
8#ifndef __LINUX_MTD_SPINAND_H
9#define __LINUX_MTD_SPINAND_H
10
11#include <linux/mutex.h>
12#include <linux/bitops.h>
13#include <linux/device.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/nand.h>
16#include <linux/spi/spi.h>
17#include <linux/spi/spi-mem.h>
18
19/**
20 * Standard SPI NAND flash operations
21 */
22
23#define SPINAND_RESET_1S_0_0_OP \
24 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \
25 SPI_MEM_OP_NO_ADDR, \
26 SPI_MEM_OP_NO_DUMMY, \
27 SPI_MEM_OP_NO_DATA)
28
29#define SPINAND_WR_EN_DIS_1S_0_0_OP(enable) \
30 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \
31 SPI_MEM_OP_NO_ADDR, \
32 SPI_MEM_OP_NO_DUMMY, \
33 SPI_MEM_OP_NO_DATA)
34
35#define SPINAND_READID_1S_1S_1S_OP(naddr, ndummy, buf, len) \
36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
37 SPI_MEM_OP_ADDR(naddr, 0, 1), \
38 SPI_MEM_OP_DUMMY(ndummy, 1), \
39 SPI_MEM_OP_DATA_IN(len, buf, 1))
40
41#define SPINAND_SET_FEATURE_1S_1S_1S_OP(reg, valptr) \
42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
43 SPI_MEM_OP_ADDR(1, reg, 1), \
44 SPI_MEM_OP_NO_DUMMY, \
45 SPI_MEM_OP_DATA_OUT(1, valptr, 1))
46
47#define SPINAND_GET_FEATURE_1S_1S_1S_OP(reg, valptr) \
48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \
49 SPI_MEM_OP_ADDR(1, reg, 1), \
50 SPI_MEM_OP_NO_DUMMY, \
51 SPI_MEM_OP_DATA_IN(1, valptr, 1))
52
53#define SPINAND_BLK_ERASE_1S_1S_0_OP(addr) \
54 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \
55 SPI_MEM_OP_ADDR(3, addr, 1), \
56 SPI_MEM_OP_NO_DUMMY, \
57 SPI_MEM_OP_NO_DATA)
58
59#define SPINAND_PAGE_READ_1S_1S_0_OP(addr) \
60 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \
61 SPI_MEM_OP_ADDR(3, addr, 1), \
62 SPI_MEM_OP_NO_DUMMY, \
63 SPI_MEM_OP_NO_DATA)
64
65#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \
66 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
67 SPI_MEM_OP_ADDR(2, addr, 1), \
68 SPI_MEM_OP_DUMMY(ndummy, 1), \
69 SPI_MEM_OP_DATA_IN(len, buf, 1), \
70 SPI_MEM_OP_MAX_FREQ(freq))
71
72#define SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \
73 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
74 SPI_MEM_OP_ADDR(2, addr, 1), \
75 SPI_MEM_OP_DUMMY(ndummy, 1), \
76 SPI_MEM_OP_DATA_IN(len, buf, 1), \
77 SPI_MEM_OP_MAX_FREQ(freq))
78
79#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \
80 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
81 SPI_MEM_OP_ADDR(3, addr, 1), \
82 SPI_MEM_OP_DUMMY(ndummy, 1), \
83 SPI_MEM_OP_DATA_IN(len, buf, 1), \
84 SPI_MEM_OP_MAX_FREQ(freq))
85
86#define SPINAND_PAGE_READ_FROM_CACHE_FAST_3A_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \
87 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
88 SPI_MEM_OP_ADDR(3, addr, 1), \
89 SPI_MEM_OP_DUMMY(ndummy, 1), \
90 SPI_MEM_OP_DATA_IN(len, buf, 1), \
91 SPI_MEM_OP_MAX_FREQ(freq))
92
93#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_1D_OP(addr, ndummy, buf, len, freq) \
94 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \
95 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
96 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
97 SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \
98 SPI_MEM_OP_MAX_FREQ(freq))
99
100#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(addr, ndummy, buf, len, freq) \
101 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
102 SPI_MEM_OP_ADDR(2, addr, 1), \
103 SPI_MEM_OP_DUMMY(ndummy, 1), \
104 SPI_MEM_OP_DATA_IN(len, buf, 2), \
105 SPI_MEM_OP_MAX_FREQ(freq))
106
107#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_2S_OP(addr, ndummy, buf, len, freq) \
108 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
109 SPI_MEM_OP_ADDR(3, addr, 1), \
110 SPI_MEM_OP_DUMMY(ndummy, 1), \
111 SPI_MEM_OP_DATA_IN(len, buf, 2), \
112 SPI_MEM_OP_MAX_FREQ(freq))
113
114#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_2D_OP(addr, ndummy, buf, len, freq) \
115 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3d, 1), \
116 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
117 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
118 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
119 SPI_MEM_OP_MAX_FREQ(freq))
120
121#define SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(addr, ndummy, buf, len, freq) \
122 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
123 SPI_MEM_OP_ADDR(2, addr, 2), \
124 SPI_MEM_OP_DUMMY(ndummy, 2), \
125 SPI_MEM_OP_DATA_IN(len, buf, 2), \
126 SPI_MEM_OP_MAX_FREQ(freq))
127
128#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_2S_2S_OP(addr, ndummy, buf, len, freq) \
129 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
130 SPI_MEM_OP_ADDR(3, addr, 2), \
131 SPI_MEM_OP_DUMMY(ndummy, 2), \
132 SPI_MEM_OP_DATA_IN(len, buf, 2), \
133 SPI_MEM_OP_MAX_FREQ(freq))
134
135#define SPINAND_PAGE_READ_FROM_CACHE_1S_2D_2D_OP(addr, ndummy, buf, len, freq) \
136 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \
137 SPI_MEM_DTR_OP_ADDR(2, addr, 2), \
138 SPI_MEM_DTR_OP_DUMMY(ndummy, 2), \
139 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
140 SPI_MEM_OP_MAX_FREQ(freq))
141
142#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(addr, ndummy, buf, len, freq) \
143 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
144 SPI_MEM_OP_ADDR(2, addr, 1), \
145 SPI_MEM_OP_DUMMY(ndummy, 1), \
146 SPI_MEM_OP_DATA_IN(len, buf, 4), \
147 SPI_MEM_OP_MAX_FREQ(freq))
148
149#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_4S_OP(addr, ndummy, buf, len, freq) \
150 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
151 SPI_MEM_OP_ADDR(3, addr, 1), \
152 SPI_MEM_OP_DUMMY(ndummy, 1), \
153 SPI_MEM_OP_DATA_IN(len, buf, 4), \
154 SPI_MEM_OP_MAX_FREQ(freq))
155
156#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_4D_OP(addr, ndummy, buf, len, freq) \
157 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \
158 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
159 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
160 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
161 SPI_MEM_OP_MAX_FREQ(freq))
162
163#define SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(addr, ndummy, buf, len, freq) \
164 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
165 SPI_MEM_OP_ADDR(2, addr, 4), \
166 SPI_MEM_OP_DUMMY(ndummy, 4), \
167 SPI_MEM_OP_DATA_IN(len, buf, 4), \
168 SPI_MEM_OP_MAX_FREQ(freq))
169
170#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_4S_4S_OP(addr, ndummy, buf, len, freq) \
171 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
172 SPI_MEM_OP_ADDR(3, addr, 4), \
173 SPI_MEM_OP_DUMMY(ndummy, 4), \
174 SPI_MEM_OP_DATA_IN(len, buf, 4), \
175 SPI_MEM_OP_MAX_FREQ(freq))
176
177#define SPINAND_PAGE_READ_FROM_CACHE_1S_4D_4D_OP(addr, ndummy, buf, len, freq) \
178 SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \
179 SPI_MEM_DTR_OP_ADDR(2, addr, 4), \
180 SPI_MEM_DTR_OP_DUMMY(ndummy, 4), \
181 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
182 SPI_MEM_OP_MAX_FREQ(freq))
183
184#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_8S_OP(addr, ndummy, buf, len, freq) \
185 SPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1), \
186 SPI_MEM_OP_ADDR(2, addr, 1), \
187 SPI_MEM_OP_DUMMY(ndummy, 1), \
188 SPI_MEM_OP_DATA_IN(len, buf, 8), \
189 SPI_MEM_OP_MAX_FREQ(freq))
190
191#define SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(addr, ndummy, buf, len, freq) \
192 SPI_MEM_OP(SPI_MEM_OP_CMD(0xcb, 1), \
193 SPI_MEM_OP_ADDR(2, addr, 8), \
194 SPI_MEM_OP_DUMMY(ndummy, 8), \
195 SPI_MEM_OP_DATA_IN(len, buf, 8), \
196 SPI_MEM_OP_MAX_FREQ(freq))
197
198#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(addr, ndummy, buf, len, freq) \
199 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9d, 1), \
200 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
201 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
202 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \
203 SPI_MEM_OP_MAX_FREQ(freq))
204
205#define SPINAND_PROG_EXEC_1S_1S_0_OP(addr) \
206 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
207 SPI_MEM_OP_ADDR(3, addr, 1), \
208 SPI_MEM_OP_NO_DUMMY, \
209 SPI_MEM_OP_NO_DATA)
210
211#define SPINAND_PROG_LOAD_1S_1S_1S_OP(reset, addr, buf, len) \
212 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \
213 SPI_MEM_OP_ADDR(2, addr, 1), \
214 SPI_MEM_OP_NO_DUMMY, \
215 SPI_MEM_OP_DATA_OUT(len, buf, 1))
216
217#define SPINAND_PROG_LOAD_1S_1S_4S_OP(reset, addr, buf, len) \
218 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \
219 SPI_MEM_OP_ADDR(2, addr, 1), \
220 SPI_MEM_OP_NO_DUMMY, \
221 SPI_MEM_OP_DATA_OUT(len, buf, 4))
222
223#define SPINAND_PROG_LOAD_1S_1S_8S_OP(addr, buf, len) \
224 SPI_MEM_OP(SPI_MEM_OP_CMD(0x82, 1), \
225 SPI_MEM_OP_ADDR(2, addr, 1), \
226 SPI_MEM_OP_NO_DUMMY, \
227 SPI_MEM_OP_DATA_OUT(len, buf, 8))
228
229#define SPINAND_PROG_LOAD_1S_8S_8S_OP(reset, addr, buf, len) \
230 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0xc2 : 0xc4, 1), \
231 SPI_MEM_OP_ADDR(2, addr, 8), \
232 SPI_MEM_OP_NO_DUMMY, \
233 SPI_MEM_OP_DATA_OUT(len, buf, 8))
234
235/**
236 * Standard SPI NAND flash commands
237 */
238#define SPINAND_CMD_PROG_LOAD_X4 0x32
239#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34
240
241/* feature register */
242#define REG_BLOCK_LOCK 0xa0
243#define BL_ALL_UNLOCKED 0x00
244
245/* configuration register */
246#define REG_CFG 0xb0
247#define CFG_OTP_ENABLE BIT(6)
248#define CFG_ECC_ENABLE BIT(4)
249#define CFG_QUAD_ENABLE BIT(0)
250
251/* status register */
252#define REG_STATUS 0xc0
253#define STATUS_BUSY BIT(0)
254#define STATUS_ERASE_FAILED BIT(2)
255#define STATUS_PROG_FAILED BIT(3)
256#define STATUS_ECC_MASK GENMASK(5, 4)
257#define STATUS_ECC_NO_BITFLIPS (0 << 4)
258#define STATUS_ECC_HAS_BITFLIPS (1 << 4)
259#define STATUS_ECC_UNCOR_ERROR (2 << 4)
260
261struct spinand_op;
262struct spinand_device;
263
264#define SPINAND_MAX_ID_LEN 5
265/*
266 * For erase, write and read operation, we got the following timings :
267 * tBERS (erase) 1ms to 4ms
268 * tPROG 300us to 400us
269 * tREAD 25us to 100us
270 * In order to minimize latency, the min value is divided by 4 for the
271 * initial delay, and dividing by 20 for the poll delay.
272 * For reset, 5us/10us/500us if the device is respectively
273 * reading/programming/erasing when the RESET occurs. Since we always
274 * issue a RESET when the device is IDLE, 5us is selected for both initial
275 * and poll delay.
276 */
277#define SPINAND_READ_INITIAL_DELAY_US 6
278#define SPINAND_READ_POLL_DELAY_US 5
279#define SPINAND_RESET_INITIAL_DELAY_US 5
280#define SPINAND_RESET_POLL_DELAY_US 5
281#define SPINAND_WRITE_INITIAL_DELAY_US 75
282#define SPINAND_WRITE_POLL_DELAY_US 15
283#define SPINAND_ERASE_INITIAL_DELAY_US 250
284#define SPINAND_ERASE_POLL_DELAY_US 50
285
286#define SPINAND_WAITRDY_TIMEOUT_MS 400
287
288/**
289 * struct spinand_id - SPI NAND id structure
290 * @data: buffer containing the id bytes. Currently 4 bytes large, but can
291 * be extended if required
292 * @len: ID length
293 */
294struct spinand_id {
295 u8 data[SPINAND_MAX_ID_LEN];
296 int len;
297};
298
299enum spinand_readid_method {
300 SPINAND_READID_METHOD_OPCODE,
301 SPINAND_READID_METHOD_OPCODE_ADDR,
302 SPINAND_READID_METHOD_OPCODE_DUMMY,
303};
304
305/**
306 * struct spinand_devid - SPI NAND device id structure
307 * @id: device id of current chip
308 * @len: number of bytes in device id
309 * @method: method to read chip id
310 * There are 3 possible variants:
311 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
312 * after read_id opcode.
313 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
314 * read_id opcode + 1-byte address.
315 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
316 * read_id opcode + 1 dummy byte.
317 */
318struct spinand_devid {
319 const u8 *id;
320 const u8 len;
321 const enum spinand_readid_method method;
322};
323
324/**
325 * struct manufacurer_ops - SPI NAND manufacturer specific operations
326 * @init: initialize a SPI NAND device
327 * @cleanup: cleanup a SPI NAND device
328 *
329 * Each SPI NAND manufacturer driver should implement this interface so that
330 * NAND chips coming from this vendor can be initialized properly.
331 */
332struct spinand_manufacturer_ops {
333 int (*init)(struct spinand_device *spinand);
334 void (*cleanup)(struct spinand_device *spinand);
335};
336
337/**
338 * struct spinand_manufacturer - SPI NAND manufacturer instance
339 * @id: manufacturer ID
340 * @name: manufacturer name
341 * @devid_len: number of bytes in device ID
342 * @chips: supported SPI NANDs under current manufacturer
343 * @nchips: number of SPI NANDs available in chips array
344 * @ops: manufacturer operations
345 */
346struct spinand_manufacturer {
347 u8 id;
348 char *name;
349 const struct spinand_info *chips;
350 const size_t nchips;
351 const struct spinand_manufacturer_ops *ops;
352};
353
354/* SPI NAND manufacturers */
355extern const struct spinand_manufacturer alliancememory_spinand_manufacturer;
356extern const struct spinand_manufacturer ato_spinand_manufacturer;
357extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
358extern const struct spinand_manufacturer fmsh_spinand_manufacturer;
359extern const struct spinand_manufacturer foresee_spinand_manufacturer;
360extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
361extern const struct spinand_manufacturer macronix_spinand_manufacturer;
362extern const struct spinand_manufacturer micron_spinand_manufacturer;
363extern const struct spinand_manufacturer paragon_spinand_manufacturer;
364extern const struct spinand_manufacturer skyhigh_spinand_manufacturer;
365extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
366extern const struct spinand_manufacturer winbond_spinand_manufacturer;
367extern const struct spinand_manufacturer xtx_spinand_manufacturer;
368
369/**
370 * struct spinand_op_variants - SPI NAND operation variants
371 * @ops: the list of variants for a given operation
372 * @nops: the number of variants
373 *
374 * Some operations like read-from-cache/write-to-cache have several variants
375 * depending on the number of IO lines you use to transfer data or address
376 * cycles. This structure is a way to describe the different variants supported
377 * by a chip and let the core pick the best one based on the SPI mem controller
378 * capabilities.
379 */
380struct spinand_op_variants {
381 const struct spi_mem_op *ops;
382 unsigned int nops;
383};
384
385#define SPINAND_OP_VARIANTS(name, ...) \
386 const struct spinand_op_variants name = { \
387 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \
388 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \
389 sizeof(struct spi_mem_op), \
390 }
391
392/**
393 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
394 * chip
395 * @get_status: get the ECC status. Should return a positive number encoding
396 * the number of corrected bitflips if correction was possible or
397 * -EBADMSG if there are uncorrectable errors. I can also return
398 * other negative error codes if the error is not caused by
399 * uncorrectable bitflips
400 * @ooblayout: the OOB layout used by the on-die ECC implementation
401 */
402struct spinand_ecc_info {
403 int (*get_status)(struct spinand_device *spinand, u8 status);
404 const struct mtd_ooblayout_ops *ooblayout;
405};
406
407#define SPINAND_HAS_QE_BIT BIT(0)
408#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
409#define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2)
410#define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3)
411#define SPINAND_NO_RAW_ACCESS BIT(4)
412
413/**
414 * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
415 * @status: status of the last wait operation that will be used in case
416 * ->get_status() is not populated by the spinand device.
417 */
418struct spinand_ondie_ecc_conf {
419 u8 status;
420};
421
422/**
423 * struct spinand_otp_layout - structure to describe the SPI NAND OTP area
424 * @npages: number of pages in the OTP
425 * @start_page: start page of the user/factory OTP area.
426 */
427struct spinand_otp_layout {
428 unsigned int npages;
429 unsigned int start_page;
430};
431
432/**
433 * struct spinand_fact_otp_ops - SPI NAND OTP methods for factory area
434 * @info: get the OTP area information
435 * @read: read from the SPI NAND OTP area
436 */
437struct spinand_fact_otp_ops {
438 int (*info)(struct spinand_device *spinand, size_t len,
439 struct otp_info *buf, size_t *retlen);
440 int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
441 size_t *retlen, u8 *buf);
442};
443
444/**
445 * struct spinand_user_otp_ops - SPI NAND OTP methods for user area
446 * @info: get the OTP area information
447 * @lock: lock an OTP region
448 * @erase: erase an OTP region
449 * @read: read from the SPI NAND OTP area
450 * @write: write to the SPI NAND OTP area
451 */
452struct spinand_user_otp_ops {
453 int (*info)(struct spinand_device *spinand, size_t len,
454 struct otp_info *buf, size_t *retlen);
455 int (*lock)(struct spinand_device *spinand, loff_t from, size_t len);
456 int (*erase)(struct spinand_device *spinand, loff_t from, size_t len);
457 int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
458 size_t *retlen, u8 *buf);
459 int (*write)(struct spinand_device *spinand, loff_t from, size_t len,
460 size_t *retlen, const u8 *buf);
461};
462
463/**
464 * struct spinand_fact_otp - SPI NAND OTP grouping structure for factory area
465 * @layout: OTP region layout
466 * @ops: OTP access ops
467 */
468struct spinand_fact_otp {
469 const struct spinand_otp_layout layout;
470 const struct spinand_fact_otp_ops *ops;
471};
472
473/**
474 * struct spinand_user_otp - SPI NAND OTP grouping structure for user area
475 * @layout: OTP region layout
476 * @ops: OTP access ops
477 */
478struct spinand_user_otp {
479 const struct spinand_otp_layout layout;
480 const struct spinand_user_otp_ops *ops;
481};
482
483/**
484 * struct spinand_info - Structure used to describe SPI NAND chips
485 * @model: model name
486 * @devid: device ID
487 * @flags: OR-ing of the SPINAND_XXX flags
488 * @memorg: memory organization
489 * @eccreq: ECC requirements
490 * @eccinfo: on-die ECC info
491 * @op_variants: operations variants
492 * @op_variants.read_cache: variants of the read-cache operation
493 * @op_variants.write_cache: variants of the write-cache operation
494 * @op_variants.update_cache: variants of the update-cache operation
495 * @select_target: function used to select a target/die. Required only for
496 * multi-die chips
497 * @configure_chip: Align the chip configuration with the core settings
498 * @set_cont_read: enable/disable continuous cached reads
499 * @fact_otp: SPI NAND factory OTP info.
500 * @user_otp: SPI NAND user OTP info.
501 * @read_retries: the number of read retry modes supported
502 * @set_read_retry: enable/disable read retry for data recovery
503 *
504 * Each SPI NAND manufacturer driver should have a spinand_info table
505 * describing all the chips supported by the driver.
506 */
507struct spinand_info {
508 const char *model;
509 struct spinand_devid devid;
510 u32 flags;
511 struct nand_memory_organization memorg;
512 struct nand_ecc_props eccreq;
513 struct spinand_ecc_info eccinfo;
514 struct {
515 const struct spinand_op_variants *read_cache;
516 const struct spinand_op_variants *write_cache;
517 const struct spinand_op_variants *update_cache;
518 } op_variants;
519 int (*select_target)(struct spinand_device *spinand,
520 unsigned int target);
521 int (*configure_chip)(struct spinand_device *spinand);
522 int (*set_cont_read)(struct spinand_device *spinand,
523 bool enable);
524 struct spinand_fact_otp fact_otp;
525 struct spinand_user_otp user_otp;
526 unsigned int read_retries;
527 int (*set_read_retry)(struct spinand_device *spinand,
528 unsigned int read_retry);
529};
530
531#define SPINAND_ID(__method, ...) \
532 { \
533 .id = (const u8[]){ __VA_ARGS__ }, \
534 .len = sizeof((u8[]){ __VA_ARGS__ }), \
535 .method = __method, \
536 }
537
538#define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
539 { \
540 .read_cache = __read, \
541 .write_cache = __write, \
542 .update_cache = __update, \
543 }
544
545#define SPINAND_ECCINFO(__ooblayout, __get_status) \
546 .eccinfo = { \
547 .ooblayout = __ooblayout, \
548 .get_status = __get_status, \
549 }
550
551#define SPINAND_SELECT_TARGET(__func) \
552 .select_target = __func
553
554#define SPINAND_CONFIGURE_CHIP(__configure_chip) \
555 .configure_chip = __configure_chip
556
557#define SPINAND_CONT_READ(__set_cont_read) \
558 .set_cont_read = __set_cont_read
559
560#define SPINAND_FACT_OTP_INFO(__npages, __start_page, __ops) \
561 .fact_otp = { \
562 .layout = { \
563 .npages = __npages, \
564 .start_page = __start_page, \
565 }, \
566 .ops = __ops, \
567 }
568
569#define SPINAND_USER_OTP_INFO(__npages, __start_page, __ops) \
570 .user_otp = { \
571 .layout = { \
572 .npages = __npages, \
573 .start_page = __start_page, \
574 }, \
575 .ops = __ops, \
576 }
577
578#define SPINAND_READ_RETRY(__read_retries, __set_read_retry) \
579 .read_retries = __read_retries, \
580 .set_read_retry = __set_read_retry
581
582#define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \
583 __flags, ...) \
584 { \
585 .model = __model, \
586 .devid = __id, \
587 .memorg = __memorg, \
588 .eccreq = __eccreq, \
589 .op_variants = __op_variants, \
590 .flags = __flags, \
591 __VA_ARGS__ \
592 }
593
594struct spinand_dirmap {
595 struct spi_mem_dirmap_desc *wdesc;
596 struct spi_mem_dirmap_desc *rdesc;
597 struct spi_mem_dirmap_desc *wdesc_ecc;
598 struct spi_mem_dirmap_desc *rdesc_ecc;
599};
600
601/**
602 * struct spinand_device - SPI NAND device instance
603 * @base: NAND device instance
604 * @spimem: pointer to the SPI mem object
605 * @lock: lock used to serialize accesses to the NAND
606 * @id: NAND ID as returned by READ_ID
607 * @flags: NAND flags
608 * @op_templates: various SPI mem op templates
609 * @op_templates.read_cache: read cache op template
610 * @op_templates.write_cache: write cache op template
611 * @op_templates.update_cache: update cache op template
612 * @select_target: select a specific target/die. Usually called before sending
613 * a command addressing a page or an eraseblock embedded in
614 * this die. Only required if your chip exposes several dies
615 * @cur_target: currently selected target/die
616 * @eccinfo: on-die ECC information
617 * @cfg_cache: config register cache. One entry per die
618 * @databuf: bounce buffer for data
619 * @oobbuf: bounce buffer for OOB data
620 * @scratchbuf: buffer used for everything but page accesses. This is needed
621 * because the spi-mem interface explicitly requests that buffers
622 * passed in spi_mem_op be DMA-able, so we can't based the bufs on
623 * the stack
624 * @manufacturer: SPI NAND manufacturer information
625 * @configure_chip: Align the chip configuration with the core settings
626 * @cont_read_possible: Field filled by the core once the whole system
627 * configuration is known to tell whether continuous reads are
628 * suitable to use or not in general with this chip/configuration.
629 * A per-transfer check must of course be done to ensure it is
630 * actually relevant to enable this feature.
631 * @set_cont_read: Enable/disable the continuous read feature
632 * @priv: manufacturer private data
633 * @fact_otp: SPI NAND factory OTP info.
634 * @user_otp: SPI NAND user OTP info.
635 * @read_retries: the number of read retry modes supported
636 * @set_read_retry: Enable/disable the read retry feature
637 */
638struct spinand_device {
639 struct nand_device base;
640 struct spi_mem *spimem;
641 struct mutex lock;
642 struct spinand_id id;
643 u32 flags;
644
645 struct {
646 const struct spi_mem_op *read_cache;
647 const struct spi_mem_op *write_cache;
648 const struct spi_mem_op *update_cache;
649 } op_templates;
650
651 struct spinand_dirmap *dirmaps;
652
653 int (*select_target)(struct spinand_device *spinand,
654 unsigned int target);
655 unsigned int cur_target;
656
657 struct spinand_ecc_info eccinfo;
658
659 u8 *cfg_cache;
660 u8 *databuf;
661 u8 *oobbuf;
662 u8 *scratchbuf;
663 const struct spinand_manufacturer *manufacturer;
664 void *priv;
665
666 int (*configure_chip)(struct spinand_device *spinand);
667 bool cont_read_possible;
668 int (*set_cont_read)(struct spinand_device *spinand,
669 bool enable);
670
671 const struct spinand_fact_otp *fact_otp;
672 const struct spinand_user_otp *user_otp;
673
674 unsigned int read_retries;
675 int (*set_read_retry)(struct spinand_device *spinand,
676 unsigned int retry_mode);
677};
678
679/**
680 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
681 * @mtd: MTD instance
682 *
683 * Return: the SPI NAND device attached to @mtd.
684 */
685static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
686{
687 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
688}
689
690/**
691 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
692 * @spinand: SPI NAND device
693 *
694 * Return: the MTD device embedded in @spinand.
695 */
696static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
697{
698 return nanddev_to_mtd(&spinand->base);
699}
700
701/**
702 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
703 * @nand: NAND object
704 *
705 * Return: the SPI NAND device embedding @nand.
706 */
707static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
708{
709 return container_of(nand, struct spinand_device, base);
710}
711
712/**
713 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
714 * @spinand: SPI NAND device
715 *
716 * Return: the NAND device embedded in @spinand.
717 */
718static inline struct nand_device *
719spinand_to_nand(struct spinand_device *spinand)
720{
721 return &spinand->base;
722}
723
724/**
725 * spinand_set_of_node - Attach a DT node to a SPI NAND device
726 * @spinand: SPI NAND device
727 * @np: DT node
728 *
729 * Attach a DT node to a SPI NAND device.
730 */
731static inline void spinand_set_of_node(struct spinand_device *spinand,
732 struct device_node *np)
733{
734 nanddev_set_of_node(&spinand->base, np);
735}
736
737int spinand_match_and_init(struct spinand_device *spinand,
738 const struct spinand_info *table,
739 unsigned int table_size,
740 enum spinand_readid_method rdid_method);
741
742int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
743int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val);
744int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val);
745int spinand_write_enable_op(struct spinand_device *spinand);
746int spinand_select_target(struct spinand_device *spinand, unsigned int target);
747
748int spinand_wait(struct spinand_device *spinand, unsigned long initial_delay_us,
749 unsigned long poll_delay_us, u8 *s);
750
751int spinand_read_page(struct spinand_device *spinand,
752 const struct nand_page_io_req *req);
753
754int spinand_write_page(struct spinand_device *spinand,
755 const struct nand_page_io_req *req);
756
757size_t spinand_otp_page_size(struct spinand_device *spinand);
758size_t spinand_fact_otp_size(struct spinand_device *spinand);
759size_t spinand_user_otp_size(struct spinand_device *spinand);
760
761int spinand_fact_otp_read(struct spinand_device *spinand, loff_t ofs,
762 size_t len, size_t *retlen, u8 *buf);
763int spinand_user_otp_read(struct spinand_device *spinand, loff_t ofs,
764 size_t len, size_t *retlen, u8 *buf);
765int spinand_user_otp_write(struct spinand_device *spinand, loff_t ofs,
766 size_t len, size_t *retlen, const u8 *buf);
767
768int spinand_set_mtd_otp_ops(struct spinand_device *spinand);
769
770#endif /* __LINUX_MTD_SPINAND_H */