tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel / drivers / phy / qualcomm / phy-qcom-qmp-qserdes-txrx-v6.h
at v6.18 84 lines 3.6 kB view raw
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ 7#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ 8 9#define QSERDES_V6_TX_BIST_MODE_LANENO 0x00 10#define QSERDES_V6_TX_CLKBUF_ENABLE 0x08 11#define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c 12#define QSERDES_V6_TX_TX_DRV_LVL 0x14 13#define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c 14#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20 15#define QSERDES_V6_TX_TX_BAND 0x24 16#define QSERDES_V6_TX_INTERFACE_SELECT 0x2c 17#define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34 18#define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38 19#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c 20#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40 21#define QSERDES_V6_TX_TRANSCEIVER_BIAS_EN 0x54 22#define QSERDES_V6_TX_HIGHZ_DRVR_EN 0x58 23#define QSERDES_V6_TX_TX_POL_INV 0x5c 24#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 25#define QSERDES_V6_TX_BIST_PATTERN7 0x7c 26#define QSERDES_V6_TX_LANE_MODE_1 0x84 27#define QSERDES_V6_TX_LANE_MODE_2 0x88 28#define QSERDES_V6_TX_LANE_MODE_3 0x8c 29#define QSERDES_V6_TX_LANE_MODE_4 0x90 30#define QSERDES_V6_TX_LANE_MODE_5 0x94 31#define QSERDES_V6_TX_RCV_DETECT_LVL_2 0xa4 32#define QSERDES_V6_TX_TRAN_DRVR_EMP_EN 0xc0 33#define QSERDES_V6_TX_TX_INTERFACE_MODE 0xc4 34#define QSERDES_V6_TX_VMODE_CTRL1 0xc8 35#define QSERDES_V6_TX_PI_QEC_CTRL 0xe4 36 37#define QSERDES_V6_RX_UCDR_FO_GAIN 0x08 38#define QSERDES_V6_RX_UCDR_SO_GAIN 0x14 39#define QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN 0x30 40#define QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34 41#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c 42#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40 43#define QSERDES_V6_RX_UCDR_PI_CONTROLS 0x44 44#define QSERDES_V6_RX_UCDR_SB2_THRESH1 0x4c 45#define QSERDES_V6_RX_UCDR_SB2_THRESH2 0x50 46#define QSERDES_V6_RX_UCDR_SB2_GAIN1 0x54 47#define QSERDES_V6_RX_UCDR_SB2_GAIN2 0x58 48#define QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE 0x60 49#define QSERDES_V6_RX_TX_ADAPT_POST_THRESH 0xcc 50#define QSERDES_V6_RX_VGA_CAL_CNTRL1 0xd4 51#define QSERDES_V6_RX_VGA_CAL_CNTRL2 0xd8 52#define QSERDES_V6_RX_GM_CAL 0xdc 53#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2 0xec 54#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0 55#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4 56#define QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW 0xf8 57#define QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH 0xfc 58#define QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 59#define QSERDES_V6_RX_SIDGET_ENABLES 0x118 60#define QSERDES_V6_RX_SIGDET_CNTRL 0x11c 61#define QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL 0x124 62#define QSERDES_V6_RX_RX_MODE_00_LOW 0x15c 63#define QSERDES_V6_RX_RX_MODE_00_HIGH 0x160 64#define QSERDES_V6_RX_RX_MODE_00_HIGH2 0x164 65#define QSERDES_V6_RX_RX_MODE_00_HIGH3 0x168 66#define QSERDES_V6_RX_RX_MODE_00_HIGH4 0x16c 67#define QSERDES_V6_RX_RX_MODE_01_LOW 0x170 68#define QSERDES_V6_RX_RX_MODE_01_HIGH 0x174 69#define QSERDES_V6_RX_RX_MODE_01_HIGH2 0x178 70#define QSERDES_V6_RX_RX_MODE_01_HIGH3 0x17c 71#define QSERDES_V6_RX_RX_MODE_01_HIGH4 0x180 72#define QSERDES_V6_RX_RX_MODE_10_LOW 0x184 73#define QSERDES_V6_RX_RX_MODE_10_HIGH 0x188 74#define QSERDES_V6_RX_RX_MODE_10_HIGH2 0x18c 75#define QSERDES_V6_RX_RX_MODE_10_HIGH3 0x190 76#define QSERDES_V6_RX_RX_MODE_10_HIGH4 0x194 77#define QSERDES_V6_RX_DFE_EN_TIMER 0x1a0 78#define QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 79#define QSERDES_V6_RX_DCC_CTRL1 0x1a8 80#define QSERDES_V6_RX_VTH_CODE 0x1b0 81#define QSERDES_V6_RX_SIGDET_CAL_CTRL1 0x1e4 82#define QSERDES_V6_RX_SIGDET_CAL_TRIM 0x1f8 83 84#endif