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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018-2019 MediaTek Inc.
3/* A library for MediaTek SGMII circuit
4 *
5 * Author: Sean Wang <sean.wang@mediatek.com>
6 * Author: Alexander Couzens <lynxis@fe80.eu>
7 * Author: Daniel Golle <daniel@makrotopia.org>
8 *
9 */
10
11#include <linux/mdio.h>
12#include <linux/of.h>
13#include <linux/pcs/pcs-mtk-lynxi.h>
14#include <linux/phylink.h>
15#include <linux/regmap.h>
16
17/* SGMII subsystem config registers */
18/* BMCR (low 16) BMSR (high 16) */
19#define SGMSYS_PCS_CONTROL_1 0x0
20#define SGMII_BMCR GENMASK(15, 0)
21#define SGMII_BMSR GENMASK(31, 16)
22
23#define SGMSYS_PCS_DEVICE_ID 0x4
24#define SGMII_LYNXI_DEV_ID 0x4d544950
25
26#define SGMSYS_PCS_ADVERTISE 0x8
27#define SGMII_ADVERTISE GENMASK(15, 0)
28#define SGMII_LPA GENMASK(31, 16)
29
30#define SGMSYS_PCS_SCRATCH 0x14
31#define SGMII_DEV_VERSION GENMASK(31, 16)
32
33/* Register to programmable link timer, the unit in 2 * 8ns */
34#define SGMSYS_PCS_LINK_TIMER 0x18
35#define SGMII_LINK_TIMER_MASK GENMASK(19, 0)
36#define SGMII_LINK_TIMER_VAL(ns) FIELD_PREP(SGMII_LINK_TIMER_MASK, \
37 ((ns) / 2 / 8))
38
39/* Register to control remote fault */
40#define SGMSYS_SGMII_MODE 0x20
41#define SGMII_IF_MODE_SGMII BIT(0)
42#define SGMII_SPEED_DUPLEX_AN BIT(1)
43#define SGMII_SPEED_MASK GENMASK(3, 2)
44#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0)
45#define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1)
46#define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2)
47#define SGMII_DUPLEX_HALF BIT(4)
48#define SGMII_REMOTE_FAULT_DIS BIT(8)
49
50/* Register to reset SGMII design */
51#define SGMSYS_RESERVED_0 0x34
52#define SGMII_SW_RESET BIT(0)
53
54/* Register to set SGMII speed, ANA RG_ Control Signals III */
55#define SGMII_PHY_SPEED_MASK GENMASK(3, 2)
56#define SGMII_PHY_SPEED_1_25G FIELD_PREP(SGMII_PHY_SPEED_MASK, 0)
57#define SGMII_PHY_SPEED_3_125G FIELD_PREP(SGMII_PHY_SPEED_MASK, 1)
58
59/* Register to power up QPHY */
60#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
61#define SGMII_PHYA_PWD BIT(4)
62
63/* Register to QPHY wrapper control */
64#define SGMSYS_QPHY_WRAP_CTRL 0xec
65#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
66#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
67
68/* struct mtk_pcs_lynxi - This structure holds each sgmii regmap andassociated
69 * data
70 * @regmap: The register map pointing at the range used to setup
71 * SGMII modes
72 * @dev: Pointer to device owning the PCS
73 * @ana_rgc3: The offset of register ANA_RGC3 relative to regmap
74 * @interface: Currently configured interface mode
75 * @pcs: Phylink PCS structure
76 * @flags: Flags indicating hardware properties
77 */
78struct mtk_pcs_lynxi {
79 struct regmap *regmap;
80 u32 ana_rgc3;
81 phy_interface_t interface;
82 struct phylink_pcs pcs;
83 u32 flags;
84};
85
86static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs)
87{
88 return container_of(pcs, struct mtk_pcs_lynxi, pcs);
89}
90
91static unsigned int mtk_pcs_lynxi_inband_caps(struct phylink_pcs *pcs,
92 phy_interface_t interface)
93{
94 switch (interface) {
95 case PHY_INTERFACE_MODE_1000BASEX:
96 case PHY_INTERFACE_MODE_SGMII:
97 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
98
99 case PHY_INTERFACE_MODE_2500BASEX:
100 return LINK_INBAND_DISABLE;
101
102 default:
103 return 0;
104 }
105}
106
107static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs,
108 unsigned int neg_mode,
109 struct phylink_link_state *state)
110{
111 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
112 unsigned int bm, adv;
113
114 /* Read the BMSR and LPA */
115 regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &bm);
116 regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv);
117
118 phylink_mii_c22_pcs_decode_state(state, neg_mode,
119 FIELD_GET(SGMII_BMSR, bm),
120 FIELD_GET(SGMII_LPA, adv));
121}
122
123static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
124 phy_interface_t interface,
125 const unsigned long *advertising,
126 bool permit_pause_to_mac)
127{
128 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
129 bool mode_changed = false, changed;
130 unsigned int rgc3, sgm_mode, bmcr;
131 int advertise, link_timer;
132
133 advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
134 advertising);
135 if (advertise < 0)
136 return advertise;
137
138 /* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and
139 * we assume that fixes it's speed at bitrate = line rate (in
140 * other words, 1000Mbps or 2500Mbps).
141 */
142 if (interface == PHY_INTERFACE_MODE_SGMII)
143 sgm_mode = SGMII_IF_MODE_SGMII;
144 else
145 sgm_mode = 0;
146
147 if (neg_mode & PHYLINK_PCS_NEG_INBAND)
148 sgm_mode |= SGMII_REMOTE_FAULT_DIS;
149
150 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
151 if (interface == PHY_INTERFACE_MODE_SGMII)
152 sgm_mode |= SGMII_SPEED_DUPLEX_AN;
153 bmcr = BMCR_ANENABLE;
154 } else {
155 bmcr = 0;
156 }
157
158 if (mpcs->interface != interface) {
159 link_timer = phylink_get_link_timer_ns(interface);
160 if (link_timer < 0)
161 return link_timer;
162
163 /* PHYA power down */
164 regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
165 SGMII_PHYA_PWD);
166
167 /* Reset SGMII PCS state */
168 regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0,
169 SGMII_SW_RESET);
170
171 if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP)
172 regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
173 SGMII_PN_SWAP_MASK,
174 SGMII_PN_SWAP_TX_RX);
175
176 if (interface == PHY_INTERFACE_MODE_2500BASEX)
177 rgc3 = SGMII_PHY_SPEED_3_125G;
178 else
179 rgc3 = SGMII_PHY_SPEED_1_25G;
180
181 /* Configure the underlying interface speed */
182 regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
183 SGMII_PHY_SPEED_MASK, rgc3);
184
185 /* Setup the link timer */
186 regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
187 SGMII_LINK_TIMER_VAL(link_timer));
188
189 mpcs->interface = interface;
190 mode_changed = true;
191 }
192
193 /* Update the advertisement, noting whether it has changed */
194 regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
195 SGMII_ADVERTISE, advertise, &changed);
196
197 /* Update the sgmsys mode register */
198 regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
199 SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN |
200 SGMII_IF_MODE_SGMII, sgm_mode);
201
202 /* Update the BMCR */
203 regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
204 BMCR_ANENABLE, bmcr);
205
206 /* Release PHYA power down state
207 * Only removing bit SGMII_PHYA_PWD isn't enough.
208 * There are cases when the SGMII_PHYA_PWD register contains 0x9 which
209 * prevents SGMII from working. The SGMII still shows link but no traffic
210 * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
211 * taken from a good working state of the SGMII interface.
212 * Unknown how much the QPHY needs but it is racy without a sleep.
213 * Tested on mt7622 & mt7986.
214 */
215 usleep_range(50, 100);
216 regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
217
218 return changed || mode_changed;
219}
220
221static void mtk_pcs_lynxi_restart_an(struct phylink_pcs *pcs)
222{
223 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
224
225 regmap_set_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, BMCR_ANRESTART);
226}
227
228static void mtk_pcs_lynxi_link_up(struct phylink_pcs *pcs,
229 unsigned int neg_mode,
230 phy_interface_t interface, int speed,
231 int duplex)
232{
233 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
234 unsigned int sgm_mode;
235
236 if (neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
237 /* Force the speed and duplex setting */
238 if (speed == SPEED_10)
239 sgm_mode = SGMII_SPEED_10;
240 else if (speed == SPEED_100)
241 sgm_mode = SGMII_SPEED_100;
242 else
243 sgm_mode = SGMII_SPEED_1000;
244
245 if (duplex != DUPLEX_FULL)
246 sgm_mode |= SGMII_DUPLEX_HALF;
247
248 regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
249 SGMII_DUPLEX_HALF | SGMII_SPEED_MASK,
250 sgm_mode);
251 }
252}
253
254static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs)
255{
256 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
257
258 mpcs->interface = PHY_INTERFACE_MODE_NA;
259}
260
261static const struct phylink_pcs_ops mtk_pcs_lynxi_ops = {
262 .pcs_inband_caps = mtk_pcs_lynxi_inband_caps,
263 .pcs_get_state = mtk_pcs_lynxi_get_state,
264 .pcs_config = mtk_pcs_lynxi_config,
265 .pcs_an_restart = mtk_pcs_lynxi_restart_an,
266 .pcs_link_up = mtk_pcs_lynxi_link_up,
267 .pcs_disable = mtk_pcs_lynxi_disable,
268};
269
270struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
271 struct regmap *regmap, u32 ana_rgc3,
272 u32 flags)
273{
274 struct mtk_pcs_lynxi *mpcs;
275 u32 id, ver;
276 int ret;
277
278 ret = regmap_read(regmap, SGMSYS_PCS_DEVICE_ID, &id);
279 if (ret < 0)
280 return NULL;
281
282 if (id != SGMII_LYNXI_DEV_ID) {
283 dev_err(dev, "unknown PCS device id %08x\n", id);
284 return NULL;
285 }
286
287 ret = regmap_read(regmap, SGMSYS_PCS_SCRATCH, &ver);
288 if (ret < 0)
289 return NULL;
290
291 ver = FIELD_GET(SGMII_DEV_VERSION, ver);
292 if (ver != 0x1) {
293 dev_err(dev, "unknown PCS device version %04x\n", ver);
294 return NULL;
295 }
296
297 dev_dbg(dev, "MediaTek LynxI SGMII PCS (id 0x%08x, ver 0x%04x)\n", id,
298 ver);
299
300 mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
301 if (!mpcs)
302 return NULL;
303
304 mpcs->ana_rgc3 = ana_rgc3;
305 mpcs->regmap = regmap;
306 mpcs->flags = flags;
307 mpcs->pcs.ops = &mtk_pcs_lynxi_ops;
308 mpcs->pcs.poll = true;
309 mpcs->interface = PHY_INTERFACE_MODE_NA;
310
311 __set_bit(PHY_INTERFACE_MODE_SGMII, mpcs->pcs.supported_interfaces);
312 __set_bit(PHY_INTERFACE_MODE_1000BASEX, mpcs->pcs.supported_interfaces);
313 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mpcs->pcs.supported_interfaces);
314
315 return &mpcs->pcs;
316}
317EXPORT_SYMBOL(mtk_pcs_lynxi_create);
318
319void mtk_pcs_lynxi_destroy(struct phylink_pcs *pcs)
320{
321 if (!pcs)
322 return;
323
324 kfree(pcs_to_mtk_pcs_lynxi(pcs));
325}
326EXPORT_SYMBOL(mtk_pcs_lynxi_destroy);
327
328MODULE_DESCRIPTION("MediaTek SGMII library for LynxI");
329MODULE_LICENSE("GPL");