tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
5 */
6
7#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8#include <dt-bindings/clock/qcom,gcc-sdm660.h>
9#include <dt-bindings/clock/qcom,gpucc-sdm660.h>
10#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
11#include <dt-bindings/clock/qcom,rpmcc.h>
12#include <dt-bindings/firmware/qcom,scm.h>
13#include <dt-bindings/interconnect/qcom,sdm660.h>
14#include <dt-bindings/power/qcom-rpmpd.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/thermal/thermal.h>
18#include <dt-bindings/soc/qcom,apr.h>
19
20/ {
21 interrupt-parent = <&intc>;
22
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 aliases {
27 mmc1 = &sdhc_1;
28 mmc2 = &sdhc_2;
29 };
30
31 chosen { };
32
33 clocks {
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <19200000>;
38 clock-output-names = "xo_board";
39 };
40
41 sleep_clk: sleep-clk {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <32764>;
45 clock-output-names = "sleep_clk";
46 };
47 };
48
49 cpus {
50 #address-cells = <2>;
51 #size-cells = <0>;
52
53 cpu0: cpu@100 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a53";
56 reg = <0x0 0x100>;
57 enable-method = "psci";
58 cpu-idle-states = <&perf_cpu_sleep_0
59 &perf_cpu_sleep_1
60 &perf_cluster_sleep_0
61 &perf_cluster_sleep_1
62 &perf_cluster_sleep_2>;
63 capacity-dmips-mhz = <1126>;
64 #cooling-cells = <2>;
65 next-level-cache = <&l2_1>;
66 l2_1: l2-cache {
67 compatible = "cache";
68 cache-level = <2>;
69 cache-unified;
70 };
71 };
72
73 cpu1: cpu@101 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a53";
76 reg = <0x0 0x101>;
77 enable-method = "psci";
78 cpu-idle-states = <&perf_cpu_sleep_0
79 &perf_cpu_sleep_1
80 &perf_cluster_sleep_0
81 &perf_cluster_sleep_1
82 &perf_cluster_sleep_2>;
83 capacity-dmips-mhz = <1126>;
84 #cooling-cells = <2>;
85 next-level-cache = <&l2_1>;
86 };
87
88 cpu2: cpu@102 {
89 device_type = "cpu";
90 compatible = "arm,cortex-a53";
91 reg = <0x0 0x102>;
92 enable-method = "psci";
93 cpu-idle-states = <&perf_cpu_sleep_0
94 &perf_cpu_sleep_1
95 &perf_cluster_sleep_0
96 &perf_cluster_sleep_1
97 &perf_cluster_sleep_2>;
98 capacity-dmips-mhz = <1126>;
99 #cooling-cells = <2>;
100 next-level-cache = <&l2_1>;
101 };
102
103 cpu3: cpu@103 {
104 device_type = "cpu";
105 compatible = "arm,cortex-a53";
106 reg = <0x0 0x103>;
107 enable-method = "psci";
108 cpu-idle-states = <&perf_cpu_sleep_0
109 &perf_cpu_sleep_1
110 &perf_cluster_sleep_0
111 &perf_cluster_sleep_1
112 &perf_cluster_sleep_2>;
113 capacity-dmips-mhz = <1126>;
114 #cooling-cells = <2>;
115 next-level-cache = <&l2_1>;
116 };
117
118 cpu4: cpu@0 {
119 device_type = "cpu";
120 compatible = "arm,cortex-a53";
121 reg = <0x0 0x0>;
122 enable-method = "psci";
123 cpu-idle-states = <&pwr_cpu_sleep_0
124 &pwr_cpu_sleep_1
125 &pwr_cluster_sleep_0
126 &pwr_cluster_sleep_1
127 &pwr_cluster_sleep_2>;
128 capacity-dmips-mhz = <1024>;
129 #cooling-cells = <2>;
130 next-level-cache = <&l2_0>;
131 l2_0: l2-cache {
132 compatible = "cache";
133 cache-level = <2>;
134 cache-unified;
135 };
136 };
137
138 cpu5: cpu@1 {
139 device_type = "cpu";
140 compatible = "arm,cortex-a53";
141 reg = <0x0 0x1>;
142 enable-method = "psci";
143 cpu-idle-states = <&pwr_cpu_sleep_0
144 &pwr_cpu_sleep_1
145 &pwr_cluster_sleep_0
146 &pwr_cluster_sleep_1
147 &pwr_cluster_sleep_2>;
148 capacity-dmips-mhz = <1024>;
149 #cooling-cells = <2>;
150 next-level-cache = <&l2_0>;
151 };
152
153 cpu6: cpu@2 {
154 device_type = "cpu";
155 compatible = "arm,cortex-a53";
156 reg = <0x0 0x2>;
157 enable-method = "psci";
158 cpu-idle-states = <&pwr_cpu_sleep_0
159 &pwr_cpu_sleep_1
160 &pwr_cluster_sleep_0
161 &pwr_cluster_sleep_1
162 &pwr_cluster_sleep_2>;
163 capacity-dmips-mhz = <1024>;
164 #cooling-cells = <2>;
165 next-level-cache = <&l2_0>;
166 };
167
168 cpu7: cpu@3 {
169 device_type = "cpu";
170 compatible = "arm,cortex-a53";
171 reg = <0x0 0x3>;
172 enable-method = "psci";
173 cpu-idle-states = <&pwr_cpu_sleep_0
174 &pwr_cpu_sleep_1
175 &pwr_cluster_sleep_0
176 &pwr_cluster_sleep_1
177 &pwr_cluster_sleep_2>;
178 capacity-dmips-mhz = <1024>;
179 #cooling-cells = <2>;
180 next-level-cache = <&l2_0>;
181 };
182
183 cpu-map {
184 cluster0 {
185 core0 {
186 cpu = <&cpu4>;
187 };
188
189 core1 {
190 cpu = <&cpu5>;
191 };
192
193 core2 {
194 cpu = <&cpu6>;
195 };
196
197 core3 {
198 cpu = <&cpu7>;
199 };
200 };
201
202 cluster1 {
203 core0 {
204 cpu = <&cpu0>;
205 };
206
207 core1 {
208 cpu = <&cpu1>;
209 };
210
211 core2 {
212 cpu = <&cpu2>;
213 };
214
215 core3 {
216 cpu = <&cpu3>;
217 };
218 };
219 };
220
221 idle-states {
222 entry-method = "psci";
223
224 pwr_cpu_sleep_0: cpu-sleep-0-0 {
225 compatible = "arm,idle-state";
226 idle-state-name = "pwr-retention";
227 arm,psci-suspend-param = <0x40000002>;
228 entry-latency-us = <338>;
229 exit-latency-us = <423>;
230 min-residency-us = <200>;
231 };
232
233 pwr_cpu_sleep_1: cpu-sleep-0-1 {
234 compatible = "arm,idle-state";
235 idle-state-name = "pwr-power-collapse";
236 arm,psci-suspend-param = <0x40000003>;
237 entry-latency-us = <515>;
238 exit-latency-us = <1821>;
239 min-residency-us = <1000>;
240 local-timer-stop;
241 };
242
243 perf_cpu_sleep_0: cpu-sleep-1-0 {
244 compatible = "arm,idle-state";
245 idle-state-name = "perf-retention";
246 arm,psci-suspend-param = <0x40000002>;
247 entry-latency-us = <154>;
248 exit-latency-us = <87>;
249 min-residency-us = <200>;
250 };
251
252 perf_cpu_sleep_1: cpu-sleep-1-1 {
253 compatible = "arm,idle-state";
254 idle-state-name = "perf-power-collapse";
255 arm,psci-suspend-param = <0x40000003>;
256 entry-latency-us = <262>;
257 exit-latency-us = <301>;
258 min-residency-us = <1000>;
259 local-timer-stop;
260 };
261
262 pwr_cluster_sleep_0: cluster-sleep-0-0 {
263 compatible = "arm,idle-state";
264 idle-state-name = "pwr-cluster-dynamic-retention";
265 arm,psci-suspend-param = <0x400000F2>;
266 entry-latency-us = <284>;
267 exit-latency-us = <384>;
268 min-residency-us = <9987>;
269 local-timer-stop;
270 };
271
272 pwr_cluster_sleep_1: cluster-sleep-0-1 {
273 compatible = "arm,idle-state";
274 idle-state-name = "pwr-cluster-retention";
275 arm,psci-suspend-param = <0x400000F3>;
276 entry-latency-us = <338>;
277 exit-latency-us = <423>;
278 min-residency-us = <9987>;
279 local-timer-stop;
280 };
281
282 pwr_cluster_sleep_2: cluster-sleep-0-2 {
283 compatible = "arm,idle-state";
284 idle-state-name = "pwr-cluster-retention";
285 arm,psci-suspend-param = <0x400000F4>;
286 entry-latency-us = <515>;
287 exit-latency-us = <1821>;
288 min-residency-us = <9987>;
289 local-timer-stop;
290 };
291
292 perf_cluster_sleep_0: cluster-sleep-1-0 {
293 compatible = "arm,idle-state";
294 idle-state-name = "perf-cluster-dynamic-retention";
295 arm,psci-suspend-param = <0x400000F2>;
296 entry-latency-us = <272>;
297 exit-latency-us = <329>;
298 min-residency-us = <9987>;
299 local-timer-stop;
300 };
301
302 perf_cluster_sleep_1: cluster-sleep-1-1 {
303 compatible = "arm,idle-state";
304 idle-state-name = "perf-cluster-retention";
305 arm,psci-suspend-param = <0x400000F3>;
306 entry-latency-us = <332>;
307 exit-latency-us = <368>;
308 min-residency-us = <9987>;
309 local-timer-stop;
310 };
311
312 perf_cluster_sleep_2: cluster-sleep-1-2 {
313 compatible = "arm,idle-state";
314 idle-state-name = "perf-cluster-retention";
315 arm,psci-suspend-param = <0x400000F4>;
316 entry-latency-us = <545>;
317 exit-latency-us = <1609>;
318 min-residency-us = <9987>;
319 local-timer-stop;
320 };
321 };
322 };
323
324 firmware {
325 scm {
326 compatible = "qcom,scm-msm8998", "qcom,scm";
327 };
328 };
329
330 memory@80000000 {
331 device_type = "memory";
332 /* We expect the bootloader to fill in the reg */
333 reg = <0x0 0x80000000 0x0 0x0>;
334 };
335
336 dsi_opp_table: opp-table-dsi {
337 compatible = "operating-points-v2";
338
339 opp-131250000 {
340 opp-hz = /bits/ 64 <131250000>;
341 required-opps = <&rpmpd_opp_svs>;
342 };
343
344 opp-210000000 {
345 opp-hz = /bits/ 64 <210000000>;
346 required-opps = <&rpmpd_opp_svs_plus>;
347 };
348
349 opp-262500000 {
350 opp-hz = /bits/ 64 <262500000>;
351 required-opps = <&rpmpd_opp_nom>;
352 };
353 };
354
355 pmu {
356 compatible = "arm,armv8-pmuv3";
357 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
358 };
359
360 psci {
361 compatible = "arm,psci-1.0";
362 method = "smc";
363 };
364
365 rpm: remoteproc {
366 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc";
367
368 glink-edge {
369 compatible = "qcom,glink-rpm";
370
371 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
372 qcom,rpm-msg-ram = <&rpm_msg_ram>;
373 mboxes = <&apcs_glb 0>;
374
375 rpm_requests: rpm-requests {
376 compatible = "qcom,rpm-sdm660", "qcom,glink-smd-rpm";
377 qcom,glink-channels = "rpm_requests";
378
379 rpmcc: clock-controller {
380 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
381 #clock-cells = <1>;
382 };
383
384 rpmpd: power-controller {
385 compatible = "qcom,sdm660-rpmpd";
386 #power-domain-cells = <1>;
387 operating-points-v2 = <&rpmpd_opp_table>;
388
389 rpmpd_opp_table: opp-table {
390 compatible = "operating-points-v2";
391
392 rpmpd_opp_ret: opp1 {
393 opp-level = <RPM_SMD_LEVEL_RETENTION>;
394 };
395
396 rpmpd_opp_ret_plus: opp2 {
397 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
398 };
399
400 rpmpd_opp_min_svs: opp3 {
401 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
402 };
403
404 rpmpd_opp_low_svs: opp4 {
405 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
406 };
407
408 rpmpd_opp_svs: opp5 {
409 opp-level = <RPM_SMD_LEVEL_SVS>;
410 };
411
412 rpmpd_opp_svs_plus: opp6 {
413 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
414 };
415
416 rpmpd_opp_nom: opp7 {
417 opp-level = <RPM_SMD_LEVEL_NOM>;
418 };
419
420 rpmpd_opp_nom_plus: opp8 {
421 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
422 };
423
424 rpmpd_opp_turbo: opp9 {
425 opp-level = <RPM_SMD_LEVEL_TURBO>;
426 };
427 };
428 };
429 };
430 };
431 };
432
433 reserved-memory {
434 #address-cells = <2>;
435 #size-cells = <2>;
436 ranges;
437
438 wlan_msa_guard: wlan-msa-guard@85600000 {
439 reg = <0x0 0x85600000 0x0 0x100000>;
440 no-map;
441 };
442
443 wlan_msa_mem: wlan-msa-mem@85700000 {
444 reg = <0x0 0x85700000 0x0 0x100000>;
445 no-map;
446 };
447
448 qhee_code: qhee-code@85800000 {
449 reg = <0x0 0x85800000 0x0 0x600000>;
450 no-map;
451 };
452
453 rmtfs_mem: memory@85e00000 {
454 compatible = "qcom,rmtfs-mem";
455 reg = <0x0 0x85e00000 0x0 0x200000>;
456 no-map;
457
458 qcom,client-id = <1>;
459 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
460 };
461
462 smem_region: smem-mem@86000000 {
463 reg = <0 0x86000000 0 0x200000>;
464 no-map;
465 };
466
467 tz_mem: memory@86200000 {
468 reg = <0x0 0x86200000 0x0 0x3300000>;
469 no-map;
470 };
471
472 mpss_region: mpss@8ac00000 {
473 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
474 no-map;
475 };
476
477 adsp_region: adsp@92a00000 {
478 reg = <0x0 0x92a00000 0x0 0x1e00000>;
479 no-map;
480 };
481
482 mba_region: mba@94800000 {
483 reg = <0x0 0x94800000 0x0 0x200000>;
484 no-map;
485 };
486
487 buffer_mem: tzbuffer@94a00000 {
488 reg = <0x0 0x94a00000 0x0 0x100000>;
489 no-map;
490 };
491
492 venus_region: venus@9f800000 {
493 reg = <0x0 0x9f800000 0x0 0x800000>;
494 no-map;
495 };
496
497 adsp_mem: adsp-region@f6000000 {
498 reg = <0x0 0xf6000000 0x0 0x800000>;
499 no-map;
500 };
501
502 qseecom_mem: qseecom-region@f6800000 {
503 reg = <0x0 0xf6800000 0x0 0x1400000>;
504 no-map;
505 };
506
507 zap_shader_region: gpu@fed00000 {
508 compatible = "shared-dma-pool";
509 reg = <0x0 0xfed00000 0x0 0xa00000>;
510 no-map;
511 };
512
513 mdata_mem: mpss-metadata {
514 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
515 size = <0x0 0x4000>;
516 no-map;
517 };
518 };
519
520 smem: smem {
521 compatible = "qcom,smem";
522 memory-region = <&smem_region>;
523 hwlocks = <&tcsr_mutex 3>;
524 };
525
526 smp2p-adsp {
527 compatible = "qcom,smp2p";
528 qcom,smem = <443>, <429>;
529 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
530 mboxes = <&apcs_glb 10>;
531 qcom,local-pid = <0>;
532 qcom,remote-pid = <2>;
533
534 adsp_smp2p_out: master-kernel {
535 qcom,entry-name = "master-kernel";
536 #qcom,smem-state-cells = <1>;
537 };
538
539 adsp_smp2p_in: slave-kernel {
540 qcom,entry-name = "slave-kernel";
541 interrupt-controller;
542 #interrupt-cells = <2>;
543 };
544 };
545
546 smp2p-mpss {
547 compatible = "qcom,smp2p";
548 qcom,smem = <435>, <428>;
549 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
550 mboxes = <&apcs_glb 14>;
551 qcom,local-pid = <0>;
552 qcom,remote-pid = <1>;
553
554 modem_smp2p_out: master-kernel {
555 qcom,entry-name = "master-kernel";
556 #qcom,smem-state-cells = <1>;
557 };
558
559 modem_smp2p_in: slave-kernel {
560 qcom,entry-name = "slave-kernel";
561 interrupt-controller;
562 #interrupt-cells = <2>;
563 };
564 };
565
566 soc@0 {
567 #address-cells = <1>;
568 #size-cells = <1>;
569 ranges = <0 0 0 0xffffffff>;
570 compatible = "simple-bus";
571
572 gcc: clock-controller@100000 {
573 compatible = "qcom,gcc-sdm630";
574 #clock-cells = <1>;
575 #reset-cells = <1>;
576 #power-domain-cells = <1>;
577 reg = <0x00100000 0x94000>;
578
579 clock-names = "xo", "sleep_clk";
580 clocks = <&xo_board>,
581 <&sleep_clk>;
582 };
583
584 rpm_msg_ram: sram@778000 {
585 compatible = "qcom,rpm-msg-ram";
586 reg = <0x00778000 0x7000>;
587 };
588
589 qfprom: qfprom@780000 {
590 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
591 reg = <0x00780000 0x621c>;
592 #address-cells = <1>;
593 #size-cells = <1>;
594
595 qusb2_hstx_trim: hstx-trim@240 {
596 reg = <0x243 0x1>;
597 bits = <1 3>;
598 };
599
600 gpu_speed_bin: gpu-speed-bin@41a0 {
601 reg = <0x41a2 0x1>;
602 bits = <5 7>;
603 };
604 };
605
606 rng: rng@793000 {
607 compatible = "qcom,prng-ee";
608 reg = <0x00793000 0x1000>;
609 clocks = <&gcc GCC_PRNG_AHB_CLK>;
610 clock-names = "core";
611 };
612
613 bimc: interconnect@1008000 {
614 compatible = "qcom,sdm660-bimc";
615 reg = <0x01008000 0x78000>;
616 #interconnect-cells = <1>;
617 };
618
619 restart@10ac000 {
620 compatible = "qcom,pshold";
621 reg = <0x010ac000 0x4>;
622 };
623
624 cnoc: interconnect@1500000 {
625 compatible = "qcom,sdm660-cnoc";
626 reg = <0x01500000 0x10000>;
627 #interconnect-cells = <1>;
628 };
629
630 snoc: interconnect@1626000 {
631 compatible = "qcom,sdm660-snoc";
632 reg = <0x01626000 0x7090>;
633 #interconnect-cells = <1>;
634 };
635
636 anoc2_smmu: iommu@16c0000 {
637 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
638 reg = <0x016c0000 0x40000>;
639 #global-interrupts = <2>;
640 #iommu-cells = <1>;
641
642 interrupts =
643 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
645
646 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
648 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
649 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
650 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
651 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
652 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
670 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
675 };
676
677 a2noc: interconnect@1704000 {
678 compatible = "qcom,sdm660-a2noc";
679 reg = <0x01704000 0xc100>;
680 #interconnect-cells = <1>;
681 clock-names = "ipa",
682 "ufs_axi",
683 "aggre2_ufs_axi",
684 "aggre2_usb3_axi",
685 "cfg_noc_usb2_axi";
686 clocks = <&rpmcc RPM_SMD_IPA_CLK>,
687 <&gcc GCC_UFS_AXI_CLK>,
688 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
689 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
690 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
691 };
692
693 mnoc: interconnect@1745000 {
694 compatible = "qcom,sdm660-mnoc";
695 reg = <0x01745000 0xa010>;
696 #interconnect-cells = <1>;
697 clock-names = "iface";
698 clocks = <&mmcc AHB_CLK_SRC>;
699 };
700
701 tsens: thermal-sensor@10ae000 {
702 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
703 reg = <0x010ae000 0x1000>, /* TM */
704 <0x010ad000 0x1000>; /* SROT */
705 #qcom,sensors = <12>;
706 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
708 interrupt-names = "uplow", "critical";
709 #thermal-sensor-cells = <1>;
710 };
711
712 tcsr_mutex: hwlock@1f40000 {
713 compatible = "qcom,tcsr-mutex";
714 reg = <0x01f40000 0x20000>;
715 #hwlock-cells = <1>;
716 };
717
718 tcsr_regs_1: syscon@1f60000 {
719 compatible = "qcom,sdm630-tcsr", "syscon";
720 reg = <0x01f60000 0x20000>;
721 };
722
723 tlmm: pinctrl@3100000 {
724 compatible = "qcom,sdm630-pinctrl";
725 reg = <0x03100000 0x400000>,
726 <0x03500000 0x400000>,
727 <0x03900000 0x400000>;
728 reg-names = "south", "center", "north";
729 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
730 gpio-controller;
731 gpio-ranges = <&tlmm 0 0 114>;
732 #gpio-cells = <2>;
733 interrupt-controller;
734 #interrupt-cells = <2>;
735
736 blsp1_uart1_default: blsp1-uart1-default-state {
737 pins = "gpio0", "gpio1", "gpio2", "gpio3";
738 function = "blsp_uart1";
739 drive-strength = <2>;
740 bias-disable;
741 };
742
743 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
744 pins = "gpio0", "gpio1", "gpio2", "gpio3";
745 function = "gpio";
746 drive-strength = <2>;
747 bias-disable;
748 };
749
750 blsp1_uart2_default: blsp1-uart2-default-state {
751 pins = "gpio4", "gpio5";
752 function = "blsp_uart2";
753 drive-strength = <2>;
754 bias-disable;
755 };
756
757 blsp2_uart1_default: blsp2-uart1-active-state {
758 tx-rts-pins {
759 pins = "gpio16", "gpio19";
760 function = "blsp_uart5";
761 drive-strength = <2>;
762 bias-disable;
763 };
764
765 rx-pins {
766 /*
767 * Avoid garbage data while BT module
768 * is powered off or not driving signal
769 */
770 pins = "gpio17";
771 function = "blsp_uart5";
772 drive-strength = <2>;
773 bias-pull-up;
774 };
775
776 cts-pins {
777 /* Match the pull of the BT module */
778 pins = "gpio18";
779 function = "blsp_uart5";
780 drive-strength = <2>;
781 bias-pull-down;
782 };
783 };
784
785 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
786 tx-pins {
787 pins = "gpio16";
788 function = "gpio";
789 drive-strength = <2>;
790 bias-pull-up;
791 };
792
793 rx-cts-rts-pins {
794 pins = "gpio17", "gpio18", "gpio19";
795 function = "gpio";
796 drive-strength = <2>;
797 bias-disable;
798 };
799 };
800
801 i2c1_default: i2c1-default-state {
802 pins = "gpio2", "gpio3";
803 function = "blsp_i2c1";
804 drive-strength = <2>;
805 bias-disable;
806 };
807
808 i2c1_sleep: i2c1-sleep-state {
809 pins = "gpio2", "gpio3";
810 function = "blsp_i2c1";
811 drive-strength = <2>;
812 bias-pull-up;
813 };
814
815 i2c2_default: i2c2-default-state {
816 pins = "gpio6", "gpio7";
817 function = "blsp_i2c2";
818 drive-strength = <2>;
819 bias-disable;
820 };
821
822 i2c2_sleep: i2c2-sleep-state {
823 pins = "gpio6", "gpio7";
824 function = "blsp_i2c2";
825 drive-strength = <2>;
826 bias-pull-up;
827 };
828
829 i2c3_default: i2c3-default-state {
830 pins = "gpio10", "gpio11";
831 function = "blsp_i2c3";
832 drive-strength = <2>;
833 bias-disable;
834 };
835
836 i2c3_sleep: i2c3-sleep-state {
837 pins = "gpio10", "gpio11";
838 function = "blsp_i2c3";
839 drive-strength = <2>;
840 bias-pull-up;
841 };
842
843 i2c4_default: i2c4-default-state {
844 pins = "gpio14", "gpio15";
845 function = "blsp_i2c4";
846 drive-strength = <2>;
847 bias-disable;
848 };
849
850 i2c4_sleep: i2c4-sleep-state {
851 pins = "gpio14", "gpio15";
852 function = "blsp_i2c4";
853 drive-strength = <2>;
854 bias-pull-up;
855 };
856
857 i2c5_default: i2c5-default-state {
858 pins = "gpio18", "gpio19";
859 function = "blsp_i2c5";
860 drive-strength = <2>;
861 bias-disable;
862 };
863
864 i2c5_sleep: i2c5-sleep-state {
865 pins = "gpio18", "gpio19";
866 function = "blsp_i2c5";
867 drive-strength = <2>;
868 bias-pull-up;
869 };
870
871 i2c6_default: i2c6-default-state {
872 pins = "gpio22", "gpio23";
873 function = "blsp_i2c6";
874 drive-strength = <2>;
875 bias-disable;
876 };
877
878 i2c6_sleep: i2c6-sleep-state {
879 pins = "gpio22", "gpio23";
880 function = "blsp_i2c6";
881 drive-strength = <2>;
882 bias-pull-up;
883 };
884
885 i2c7_default: i2c7-default-state {
886 pins = "gpio26", "gpio27";
887 function = "blsp_i2c7";
888 drive-strength = <2>;
889 bias-disable;
890 };
891
892 i2c7_sleep: i2c7-sleep-state {
893 pins = "gpio26", "gpio27";
894 function = "blsp_i2c7";
895 drive-strength = <2>;
896 bias-pull-up;
897 };
898
899 i2c8_default: i2c8-default-state {
900 pins = "gpio30", "gpio31";
901 function = "blsp_i2c8_a";
902 drive-strength = <2>;
903 bias-disable;
904 };
905
906 i2c8_sleep: i2c8-sleep-state {
907 pins = "gpio30", "gpio31";
908 function = "blsp_i2c8_a";
909 drive-strength = <2>;
910 bias-pull-up;
911 };
912
913 cci0_default: cci0-default-state {
914 pins = "gpio36","gpio37";
915 function = "cci_i2c";
916 bias-pull-up;
917 drive-strength = <2>;
918 };
919
920 cci1_default: cci1-default-state {
921 pins = "gpio38","gpio39";
922 function = "cci_i2c";
923 bias-pull-up;
924 drive-strength = <2>;
925 };
926
927 sdc1_state_on: sdc1-on-state {
928 clk-pins {
929 pins = "sdc1_clk";
930 bias-disable;
931 drive-strength = <16>;
932 };
933
934 cmd-pins {
935 pins = "sdc1_cmd";
936 bias-pull-up;
937 drive-strength = <10>;
938 };
939
940 data-pins {
941 pins = "sdc1_data";
942 bias-pull-up;
943 drive-strength = <10>;
944 };
945
946 rclk-pins {
947 pins = "sdc1_rclk";
948 bias-pull-down;
949 };
950 };
951
952 sdc1_state_off: sdc1-off-state {
953 clk-pins {
954 pins = "sdc1_clk";
955 bias-disable;
956 drive-strength = <2>;
957 };
958
959 cmd-pins {
960 pins = "sdc1_cmd";
961 bias-pull-up;
962 drive-strength = <2>;
963 };
964
965 data-pins {
966 pins = "sdc1_data";
967 bias-pull-up;
968 drive-strength = <2>;
969 };
970
971 rclk-pins {
972 pins = "sdc1_rclk";
973 bias-pull-down;
974 };
975 };
976
977 sdc2_state_on: sdc2-on-state {
978 clk-pins {
979 pins = "sdc2_clk";
980 bias-disable;
981 drive-strength = <16>;
982 };
983
984 cmd-pins {
985 pins = "sdc2_cmd";
986 bias-pull-up;
987 drive-strength = <10>;
988 };
989
990 data-pins {
991 pins = "sdc2_data";
992 bias-pull-up;
993 drive-strength = <10>;
994 };
995 };
996
997 sdc2_state_off: sdc2-off-state {
998 clk-pins {
999 pins = "sdc2_clk";
1000 bias-disable;
1001 drive-strength = <2>;
1002 };
1003
1004 cmd-pins {
1005 pins = "sdc2_cmd";
1006 bias-pull-up;
1007 drive-strength = <2>;
1008 };
1009
1010 data-pins {
1011 pins = "sdc2_data";
1012 bias-pull-up;
1013 drive-strength = <2>;
1014 };
1015 };
1016 };
1017
1018 remoteproc_mss: remoteproc@4080000 {
1019 compatible = "qcom,sdm660-mss-pil";
1020 reg = <0x04080000 0x100>, <0x04180000 0x40>;
1021 reg-names = "qdsp6", "rmb";
1022
1023 interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1024 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1025 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1026 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1027 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1028 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1029 interrupt-names = "wdog",
1030 "fatal",
1031 "ready",
1032 "handover",
1033 "stop-ack",
1034 "shutdown-ack";
1035
1036 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1037 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1038 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1039 <&gcc GPLL0_OUT_MSSCC>,
1040 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1041 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1042 <&rpmcc RPM_SMD_QDSS_CLK>,
1043 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1044 clock-names = "iface",
1045 "bus",
1046 "mem",
1047 "gpll0_mss",
1048 "snoc_axi",
1049 "mnoc_axi",
1050 "qdss",
1051 "xo";
1052
1053 qcom,smem-states = <&modem_smp2p_out 0>;
1054 qcom,smem-state-names = "stop";
1055
1056 resets = <&gcc GCC_MSS_RESTART>;
1057 reset-names = "mss_restart";
1058
1059 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1060
1061 power-domains = <&rpmpd SDM660_VDDCX>,
1062 <&rpmpd SDM660_VDDMX>;
1063 power-domain-names = "cx", "mx";
1064
1065 memory-region = <&mba_region>, <&mpss_region>, <&mdata_mem>;
1066
1067 status = "disabled";
1068
1069 glink-edge {
1070 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1071 label = "modem";
1072 qcom,remote-pid = <1>;
1073 mboxes = <&apcs_glb 15>;
1074 };
1075 };
1076
1077 adreno_gpu: gpu@5000000 {
1078 compatible = "qcom,adreno-508.0", "qcom,adreno";
1079
1080 reg = <0x05000000 0x40000>;
1081 reg-names = "kgsl_3d0_reg_memory";
1082
1083 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1084
1085 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1086 <&gpucc GPUCC_RBBMTIMER_CLK>,
1087 <&gcc GCC_BIMC_GFX_CLK>,
1088 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1089 <&gpucc GPUCC_RBCPR_CLK>,
1090 <&gpucc GPUCC_GFX3D_CLK>;
1091
1092 clock-names = "iface",
1093 "rbbmtimer",
1094 "mem",
1095 "mem_iface",
1096 "rbcpr",
1097 "core";
1098
1099 power-domains = <&rpmpd SDM660_VDDMX>;
1100 iommus = <&kgsl_smmu 0>;
1101
1102 nvmem-cells = <&gpu_speed_bin>;
1103 nvmem-cell-names = "speed_bin";
1104
1105 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>;
1106 interconnect-names = "gfx-mem";
1107
1108 operating-points-v2 = <&gpu_sdm630_opp_table>;
1109 #cooling-cells = <2>;
1110
1111 status = "disabled";
1112
1113 gpu_sdm630_opp_table: opp-table {
1114 compatible = "operating-points-v2";
1115 opp-775000000 {
1116 opp-hz = /bits/ 64 <775000000>;
1117 opp-level = <RPM_SMD_LEVEL_TURBO>;
1118 opp-peak-kBps = <5412000>;
1119 opp-supported-hw = <0xa2>;
1120 };
1121 opp-647000000 {
1122 opp-hz = /bits/ 64 <647000000>;
1123 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1124 opp-peak-kBps = <4068000>;
1125 opp-supported-hw = <0xff>;
1126 };
1127 opp-588000000 {
1128 opp-hz = /bits/ 64 <588000000>;
1129 opp-level = <RPM_SMD_LEVEL_NOM>;
1130 opp-peak-kBps = <3072000>;
1131 opp-supported-hw = <0xff>;
1132 };
1133 opp-465000000 {
1134 opp-hz = /bits/ 64 <465000000>;
1135 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1136 opp-peak-kBps = <2724000>;
1137 opp-supported-hw = <0xff>;
1138 };
1139 opp-370000000 {
1140 opp-hz = /bits/ 64 <370000000>;
1141 opp-level = <RPM_SMD_LEVEL_SVS>;
1142 opp-peak-kBps = <2188000>;
1143 opp-supported-hw = <0xff>;
1144 };
1145 opp-240000000 {
1146 opp-hz = /bits/ 64 <240000000>;
1147 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1148 opp-peak-kBps = <1648000>;
1149 opp-supported-hw = <0xff>;
1150 };
1151 opp-160000000 {
1152 opp-hz = /bits/ 64 <160000000>;
1153 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1154 opp-peak-kBps = <1200000>;
1155 opp-supported-hw = <0xff>;
1156 };
1157 };
1158
1159 adreno_gpu_zap: zap-shader {
1160 memory-region = <&zap_shader_region>;
1161 };
1162 };
1163
1164 kgsl_smmu: iommu@5040000 {
1165 compatible = "qcom,sdm630-smmu-v2",
1166 "qcom,adreno-smmu", "qcom,smmu-v2";
1167 reg = <0x05040000 0x10000>;
1168
1169 /*
1170 * GX GDSC parent is CX. We need to bring up CX for SMMU
1171 * but we need both up for Adreno. On the other hand, we
1172 * need to manage the GX rpmpd domain in the adreno driver.
1173 * Enable CX/GX GDSCs here so that we can manage just the GX
1174 * RPM Power Domain in the Adreno driver.
1175 */
1176 power-domains = <&gpucc GPU_GX_GDSC>;
1177 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1178 <&gcc GCC_BIMC_GFX_CLK>,
1179 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1180 clock-names = "iface",
1181 "mem",
1182 "mem_iface";
1183 #global-interrupts = <2>;
1184 #iommu-cells = <1>;
1185
1186 interrupts =
1187 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1189
1190 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1192 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1194 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1195 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1196 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
1197 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
1198 };
1199
1200 gpucc: clock-controller@5065000 {
1201 compatible = "qcom,gpucc-sdm630";
1202 #clock-cells = <1>;
1203 #reset-cells = <1>;
1204 #power-domain-cells = <1>;
1205 reg = <0x05065000 0x9038>;
1206
1207 clocks = <&xo_board>,
1208 <&gcc GCC_GPU_GPLL0_CLK>,
1209 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1210 clock-names = "xo",
1211 "gcc_gpu_gpll0_clk",
1212 "gcc_gpu_gpll0_div_clk";
1213 };
1214
1215 lpass_smmu: iommu@5100000 {
1216 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1217 reg = <0x05100000 0x40000>;
1218 #iommu-cells = <1>;
1219
1220 #global-interrupts = <2>;
1221 interrupts =
1222 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1224
1225 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1242 };
1243
1244 sram@290000 {
1245 compatible = "qcom,rpm-stats";
1246 reg = <0x00290000 0x10000>;
1247 };
1248
1249 spmi_bus: spmi@800f000 {
1250 compatible = "qcom,spmi-pmic-arb";
1251 reg = <0x0800f000 0x1000>,
1252 <0x08400000 0x1000000>,
1253 <0x09400000 0x1000000>,
1254 <0x0a400000 0x220000>,
1255 <0x0800a000 0x3000>;
1256 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1257 interrupt-names = "periph_irq";
1258 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1259 qcom,ee = <0>;
1260 qcom,channel = <0>;
1261 #address-cells = <2>;
1262 #size-cells = <0>;
1263 interrupt-controller;
1264 #interrupt-cells = <4>;
1265 };
1266
1267 usb3: usb@a8f8800 {
1268 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1269 reg = <0x0a8f8800 0x400>;
1270 status = "disabled";
1271 #address-cells = <1>;
1272 #size-cells = <1>;
1273 ranges;
1274
1275 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1276 <&gcc GCC_USB30_MASTER_CLK>,
1277 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1278 <&gcc GCC_USB30_SLEEP_CLK>,
1279 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
1280 clock-names = "cfg_noc",
1281 "core",
1282 "iface",
1283 "sleep",
1284 "mock_utmi";
1285
1286 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1287 <&gcc GCC_USB30_MASTER_CLK>;
1288 assigned-clock-rates = <19200000>, <120000000>;
1289
1290 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1291 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1292 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1294 interrupt-names = "pwr_event",
1295 "qusb2_phy",
1296 "hs_phy_irq",
1297 "ss_phy_irq";
1298
1299 power-domains = <&gcc USB_30_GDSC>;
1300
1301 resets = <&gcc GCC_USB_30_BCR>;
1302
1303 usb3_dwc3: usb@a800000 {
1304 compatible = "snps,dwc3";
1305 reg = <0x0a800000 0xc8d0>;
1306 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1307 snps,dis_u2_susphy_quirk;
1308 snps,dis_enblslpm_quirk;
1309 snps,parkmode-disable-ss-quirk;
1310 snps,dis-u1-entry-quirk;
1311 snps,dis-u2-entry-quirk;
1312
1313 phys = <&qusb2phy0>, <&usb3_qmpphy>;
1314 phy-names = "usb2-phy", "usb3-phy";
1315 snps,hird-threshold = /bits/ 8 <0>;
1316 };
1317 };
1318
1319 usb3_qmpphy: phy@c010000 {
1320 compatible = "qcom,sdm660-qmp-usb3-phy";
1321 reg = <0x0c010000 0x1000>;
1322
1323 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1324 <&gcc GCC_USB3_CLKREF_CLK>,
1325 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1326 <&gcc GCC_USB3_PHY_PIPE_CLK>;
1327 clock-names = "aux",
1328 "ref",
1329 "cfg_ahb",
1330 "pipe";
1331 clock-output-names = "usb3_phy_pipe_clk_src";
1332 #clock-cells = <0>;
1333 #phy-cells = <0>;
1334
1335 resets = <&gcc GCC_USB3_PHY_BCR>,
1336 <&gcc GCC_USB3PHY_PHY_BCR>;
1337 reset-names = "phy",
1338 "phy_phy";
1339
1340 qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
1341
1342 status = "disabled";
1343 };
1344
1345 qusb2phy0: phy@c012000 {
1346 compatible = "qcom,sdm660-qusb2-phy";
1347 reg = <0x0c012000 0x180>;
1348 #phy-cells = <0>;
1349
1350 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1351 <&gcc GCC_RX0_USB2_CLKREF_CLK>;
1352 clock-names = "cfg_ahb", "ref";
1353
1354 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1355 nvmem-cells = <&qusb2_hstx_trim>;
1356 status = "disabled";
1357 };
1358
1359 qusb2phy1: phy@c014000 {
1360 compatible = "qcom,sdm660-qusb2-phy";
1361 reg = <0x0c014000 0x180>;
1362 #phy-cells = <0>;
1363
1364 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1365 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1366 clock-names = "cfg_ahb", "ref";
1367
1368 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1369 nvmem-cells = <&qusb2_hstx_trim>;
1370 status = "disabled";
1371 };
1372
1373 sdhc_2: mmc@c084000 {
1374 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1375 reg = <0x0c084000 0x1000>;
1376 reg-names = "hc";
1377
1378 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1380 interrupt-names = "hc_irq", "pwr_irq";
1381
1382 bus-width = <4>;
1383
1384 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1385 <&gcc GCC_SDCC2_APPS_CLK>,
1386 <&xo_board>;
1387 clock-names = "iface", "core", "xo";
1388
1389 resets = <&gcc GCC_SDCC2_BCR>;
1390
1391 interconnects = <&a2noc 3 &a2noc 10>,
1392 <&gnoc 0 &cnoc 28>;
1393 interconnect-names = "sdhc-ddr","cpu-sdhc";
1394 operating-points-v2 = <&sdhc2_opp_table>;
1395
1396 pinctrl-names = "default", "sleep";
1397 pinctrl-0 = <&sdc2_state_on>;
1398 pinctrl-1 = <&sdc2_state_off>;
1399 power-domains = <&rpmpd SDM660_VDDCX>;
1400
1401 status = "disabled";
1402
1403 sdhc2_opp_table: opp-table {
1404 compatible = "operating-points-v2";
1405
1406 opp-50000000 {
1407 opp-hz = /bits/ 64 <50000000>;
1408 required-opps = <&rpmpd_opp_low_svs>;
1409 opp-peak-kBps = <200000 140000>;
1410 opp-avg-kBps = <130718 133320>;
1411 };
1412 opp-100000000 {
1413 opp-hz = /bits/ 64 <100000000>;
1414 required-opps = <&rpmpd_opp_svs>;
1415 opp-peak-kBps = <250000 160000>;
1416 opp-avg-kBps = <196078 150000>;
1417 };
1418 opp-200000000 {
1419 opp-hz = /bits/ 64 <200000000>;
1420 required-opps = <&rpmpd_opp_nom>;
1421 opp-peak-kBps = <4096000 4096000>;
1422 opp-avg-kBps = <1338562 1338562>;
1423 };
1424 };
1425 };
1426
1427 sdhc_1: mmc@c0c4000 {
1428 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1429 reg = <0x0c0c4000 0x1000>,
1430 <0x0c0c5000 0x1000>,
1431 <0x0c0c8000 0x8000>;
1432 reg-names = "hc", "cqhci", "ice";
1433
1434 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1435 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1436 interrupt-names = "hc_irq", "pwr_irq";
1437
1438 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1439 <&gcc GCC_SDCC1_APPS_CLK>,
1440 <&xo_board>,
1441 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1442 clock-names = "iface", "core", "xo", "ice";
1443
1444 resets = <&gcc GCC_SDCC1_BCR>;
1445
1446 interconnects = <&a2noc 2 &a2noc 10>,
1447 <&gnoc 0 &cnoc 27>;
1448 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1449 operating-points-v2 = <&sdhc1_opp_table>;
1450 pinctrl-names = "default", "sleep";
1451 pinctrl-0 = <&sdc1_state_on>;
1452 pinctrl-1 = <&sdc1_state_off>;
1453 power-domains = <&rpmpd SDM660_VDDCX>;
1454
1455 bus-width = <8>;
1456 non-removable;
1457
1458 status = "disabled";
1459
1460 sdhc1_opp_table: opp-table {
1461 compatible = "operating-points-v2";
1462
1463 opp-50000000 {
1464 opp-hz = /bits/ 64 <50000000>;
1465 required-opps = <&rpmpd_opp_low_svs>;
1466 opp-peak-kBps = <200000 140000>;
1467 opp-avg-kBps = <130718 133320>;
1468 };
1469 opp-100000000 {
1470 opp-hz = /bits/ 64 <100000000>;
1471 required-opps = <&rpmpd_opp_svs>;
1472 opp-peak-kBps = <250000 160000>;
1473 opp-avg-kBps = <196078 150000>;
1474 };
1475 opp-384000000 {
1476 opp-hz = /bits/ 64 <384000000>;
1477 required-opps = <&rpmpd_opp_nom>;
1478 opp-peak-kBps = <4096000 4096000>;
1479 opp-avg-kBps = <1338562 1338562>;
1480 };
1481 };
1482 };
1483
1484 usb2: usb@c2f8800 {
1485 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1486 reg = <0x0c2f8800 0x400>;
1487 status = "disabled";
1488 #address-cells = <1>;
1489 #size-cells = <1>;
1490 ranges;
1491
1492 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>,
1493 <&gcc GCC_USB20_MASTER_CLK>,
1494 <&gcc GCC_USB20_SLEEP_CLK>,
1495 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
1496 clock-names = "cfg_noc", "core",
1497 "sleep", "mock_utmi";
1498
1499 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1500 <&gcc GCC_USB20_MASTER_CLK>;
1501 assigned-clock-rates = <19200000>, <60000000>;
1502
1503 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1504 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
1505 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1506 interrupt-names = "pwr_event",
1507 "qusb2_phy",
1508 "hs_phy_irq";
1509
1510 qcom,select-utmi-as-pipe-clk;
1511
1512 resets = <&gcc GCC_USB_20_BCR>;
1513
1514 usb2_dwc3: usb@c200000 {
1515 compatible = "snps,dwc3";
1516 reg = <0x0c200000 0xc8d0>;
1517 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1518 snps,dis_u2_susphy_quirk;
1519 snps,dis_enblslpm_quirk;
1520 snps,dis-u1-entry-quirk;
1521 snps,dis-u2-entry-quirk;
1522
1523 /* This is the HS-only host */
1524 maximum-speed = "high-speed";
1525 phys = <&qusb2phy1>;
1526 phy-names = "usb2-phy";
1527 snps,hird-threshold = /bits/ 8 <0>;
1528 };
1529 };
1530
1531 mmcc: clock-controller@c8c0000 {
1532 compatible = "qcom,mmcc-sdm630";
1533 reg = <0x0c8c0000 0x40000>;
1534 #clock-cells = <1>;
1535 #reset-cells = <1>;
1536 #power-domain-cells = <1>;
1537 clock-names = "xo",
1538 "sleep_clk",
1539 "gpll0",
1540 "gpll0_div",
1541 "dsi0pll",
1542 "dsi0pllbyte",
1543 "dsi1pll",
1544 "dsi1pllbyte",
1545 "dp_link_2x_clk_divsel_five",
1546 "dp_vco_divided_clk_src_mux";
1547 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1548 <&sleep_clk>,
1549 <&gcc GCC_MMSS_GPLL0_CLK>,
1550 <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
1551 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
1552 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1553 <0>,
1554 <0>,
1555 <0>,
1556 <0>;
1557 };
1558
1559 mdss: display-subsystem@c900000 {
1560 compatible = "qcom,mdss";
1561 reg = <0x0c900000 0x1000>,
1562 <0x0c9b0000 0x1040>;
1563 reg-names = "mdss_phys", "vbif_phys";
1564
1565 power-domains = <&mmcc MDSS_GDSC>;
1566
1567 clocks = <&mmcc MDSS_AHB_CLK>,
1568 <&mmcc MDSS_AXI_CLK>,
1569 <&mmcc MDSS_VSYNC_CLK>,
1570 <&mmcc MDSS_MDP_CLK>;
1571 clock-names = "iface",
1572 "bus",
1573 "vsync",
1574 "core";
1575
1576 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1577
1578 interrupt-controller;
1579 #interrupt-cells = <1>;
1580
1581 #address-cells = <1>;
1582 #size-cells = <1>;
1583 ranges;
1584 status = "disabled";
1585
1586 mdp: display-controller@c901000 {
1587 compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
1588 reg = <0x0c901000 0x89000>;
1589 reg-names = "mdp_phys";
1590
1591 interrupt-parent = <&mdss>;
1592 interrupts = <0>;
1593
1594 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1595 <&mmcc MDSS_VSYNC_CLK>;
1596 assigned-clock-rates = <300000000>,
1597 <19200000>;
1598 clocks = <&mmcc MDSS_AHB_CLK>,
1599 <&mmcc MDSS_AXI_CLK>,
1600 <&mmcc MDSS_MDP_CLK>,
1601 <&mmcc MDSS_VSYNC_CLK>;
1602 clock-names = "iface",
1603 "bus",
1604 "core",
1605 "vsync";
1606
1607 interconnects = <&mnoc 2 &bimc 5>,
1608 <&mnoc 3 &bimc 5>,
1609 <&gnoc 0 &mnoc 17>;
1610 interconnect-names = "mdp0-mem",
1611 "mdp1-mem",
1612 "rotator-mem";
1613 iommus = <&mmss_smmu 0>;
1614 operating-points-v2 = <&mdp_opp_table>;
1615 power-domains = <&rpmpd SDM660_VDDCX>;
1616
1617 ports {
1618 #address-cells = <1>;
1619 #size-cells = <0>;
1620
1621 port@0 {
1622 reg = <0>;
1623 mdp5_intf1_out: endpoint {
1624 remote-endpoint = <&mdss_dsi0_in>;
1625 };
1626 };
1627 };
1628
1629 mdp_opp_table: opp-table {
1630 compatible = "operating-points-v2";
1631
1632 opp-150000000 {
1633 opp-hz = /bits/ 64 <150000000>;
1634 opp-peak-kBps = <320000 320000 76800>;
1635 required-opps = <&rpmpd_opp_low_svs>;
1636 };
1637 opp-275000000 {
1638 opp-hz = /bits/ 64 <275000000>;
1639 opp-peak-kBps = <6400000 6400000 160000>;
1640 required-opps = <&rpmpd_opp_svs>;
1641 };
1642 opp-300000000 {
1643 opp-hz = /bits/ 64 <300000000>;
1644 opp-peak-kBps = <6400000 6400000 190000>;
1645 required-opps = <&rpmpd_opp_svs_plus>;
1646 };
1647 opp-330000000 {
1648 opp-hz = /bits/ 64 <330000000>;
1649 opp-peak-kBps = <6400000 6400000 240000>;
1650 required-opps = <&rpmpd_opp_nom>;
1651 };
1652 opp-412500000 {
1653 opp-hz = /bits/ 64 <412500000>;
1654 opp-peak-kBps = <6400000 6400000 320000>;
1655 required-opps = <&rpmpd_opp_turbo>;
1656 };
1657 };
1658 };
1659
1660 mdss_dsi0: dsi@c994000 {
1661 compatible = "qcom,sdm660-dsi-ctrl",
1662 "qcom,mdss-dsi-ctrl";
1663 reg = <0x0c994000 0x400>;
1664 reg-names = "dsi_ctrl";
1665
1666 operating-points-v2 = <&dsi_opp_table>;
1667 power-domains = <&rpmpd SDM660_VDDCX>;
1668
1669 interrupt-parent = <&mdss>;
1670 interrupts = <4>;
1671
1672 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1673 <&mmcc PCLK0_CLK_SRC>;
1674 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1675 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
1676
1677 clocks = <&mmcc MDSS_MDP_CLK>,
1678 <&mmcc MDSS_BYTE0_CLK>,
1679 <&mmcc MDSS_BYTE0_INTF_CLK>,
1680 <&mmcc MNOC_AHB_CLK>,
1681 <&mmcc MDSS_AHB_CLK>,
1682 <&mmcc MDSS_AXI_CLK>,
1683 <&mmcc MISC_AHB_CLK>,
1684 <&mmcc MDSS_PCLK0_CLK>,
1685 <&mmcc MDSS_ESC0_CLK>;
1686 clock-names = "mdp_core",
1687 "byte",
1688 "byte_intf",
1689 "mnoc",
1690 "iface",
1691 "bus",
1692 "core_mmss",
1693 "pixel",
1694 "core";
1695
1696 phys = <&mdss_dsi0_phy>;
1697
1698 status = "disabled";
1699
1700 ports {
1701 #address-cells = <1>;
1702 #size-cells = <0>;
1703
1704 port@0 {
1705 reg = <0>;
1706 mdss_dsi0_in: endpoint {
1707 remote-endpoint = <&mdp5_intf1_out>;
1708 };
1709 };
1710
1711 port@1 {
1712 reg = <1>;
1713 mdss_dsi0_out: endpoint {
1714 };
1715 };
1716 };
1717 };
1718
1719 mdss_dsi0_phy: phy@c994400 {
1720 compatible = "qcom,dsi-phy-14nm-660";
1721 reg = <0x0c994400 0x100>,
1722 <0x0c994500 0x300>,
1723 <0x0c994800 0x188>;
1724 reg-names = "dsi_phy",
1725 "dsi_phy_lane",
1726 "dsi_pll";
1727
1728 #clock-cells = <1>;
1729 #phy-cells = <0>;
1730
1731 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1732 clock-names = "iface", "ref";
1733 status = "disabled";
1734 };
1735 };
1736
1737 blsp1_dma: dma-controller@c144000 {
1738 compatible = "qcom,bam-v1.7.0";
1739 reg = <0x0c144000 0x1f000>;
1740 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1741 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1742 clock-names = "bam_clk";
1743 #dma-cells = <1>;
1744 qcom,ee = <0>;
1745 qcom,controlled-remotely;
1746 num-channels = <18>;
1747 qcom,num-ees = <4>;
1748 };
1749
1750 blsp1_uart1: serial@c16f000 {
1751 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1752 reg = <0x0c16f000 0x200>;
1753 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1754 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1755 <&gcc GCC_BLSP1_AHB_CLK>;
1756 clock-names = "core", "iface";
1757 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1758 dma-names = "tx", "rx";
1759 pinctrl-names = "default", "sleep";
1760 pinctrl-0 = <&blsp1_uart1_default>;
1761 pinctrl-1 = <&blsp1_uart1_sleep>;
1762 status = "disabled";
1763 };
1764
1765 blsp1_uart2: serial@c170000 {
1766 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1767 reg = <0x0c170000 0x1000>;
1768 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1769 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1770 <&gcc GCC_BLSP1_AHB_CLK>;
1771 clock-names = "core", "iface";
1772 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1773 dma-names = "tx", "rx";
1774 pinctrl-names = "default";
1775 pinctrl-0 = <&blsp1_uart2_default>;
1776 status = "disabled";
1777 };
1778
1779 blsp_i2c1: i2c@c175000 {
1780 compatible = "qcom,i2c-qup-v2.2.1";
1781 reg = <0x0c175000 0x600>;
1782 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1783
1784 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1785 <&gcc GCC_BLSP1_AHB_CLK>;
1786 clock-names = "core", "iface";
1787 clock-frequency = <400000>;
1788 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1789 dma-names = "tx", "rx";
1790
1791 pinctrl-names = "default", "sleep";
1792 pinctrl-0 = <&i2c1_default>;
1793 pinctrl-1 = <&i2c1_sleep>;
1794 #address-cells = <1>;
1795 #size-cells = <0>;
1796 status = "disabled";
1797 };
1798
1799 blsp_i2c2: i2c@c176000 {
1800 compatible = "qcom,i2c-qup-v2.2.1";
1801 reg = <0x0c176000 0x600>;
1802 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1803
1804 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1805 <&gcc GCC_BLSP1_AHB_CLK>;
1806 clock-names = "core", "iface";
1807 clock-frequency = <400000>;
1808 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1809 dma-names = "tx", "rx";
1810
1811 pinctrl-names = "default", "sleep";
1812 pinctrl-0 = <&i2c2_default>;
1813 pinctrl-1 = <&i2c2_sleep>;
1814 #address-cells = <1>;
1815 #size-cells = <0>;
1816 status = "disabled";
1817 };
1818
1819 blsp_i2c3: i2c@c177000 {
1820 compatible = "qcom,i2c-qup-v2.2.1";
1821 reg = <0x0c177000 0x600>;
1822 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1823
1824 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1825 <&gcc GCC_BLSP1_AHB_CLK>;
1826 clock-names = "core", "iface";
1827 clock-frequency = <400000>;
1828 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1829 dma-names = "tx", "rx";
1830
1831 pinctrl-names = "default", "sleep";
1832 pinctrl-0 = <&i2c3_default>;
1833 pinctrl-1 = <&i2c3_sleep>;
1834 #address-cells = <1>;
1835 #size-cells = <0>;
1836 status = "disabled";
1837 };
1838
1839 blsp_i2c4: i2c@c178000 {
1840 compatible = "qcom,i2c-qup-v2.2.1";
1841 reg = <0x0c178000 0x600>;
1842 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1843
1844 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1845 <&gcc GCC_BLSP1_AHB_CLK>;
1846 clock-names = "core", "iface";
1847 clock-frequency = <400000>;
1848 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
1849 dma-names = "tx", "rx";
1850
1851 pinctrl-names = "default", "sleep";
1852 pinctrl-0 = <&i2c4_default>;
1853 pinctrl-1 = <&i2c4_sleep>;
1854 #address-cells = <1>;
1855 #size-cells = <0>;
1856 status = "disabled";
1857 };
1858
1859 blsp2_dma: dma-controller@c184000 {
1860 compatible = "qcom,bam-v1.7.0";
1861 reg = <0x0c184000 0x1f000>;
1862 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1863 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1864 clock-names = "bam_clk";
1865 #dma-cells = <1>;
1866 qcom,ee = <0>;
1867 qcom,controlled-remotely;
1868 num-channels = <18>;
1869 qcom,num-ees = <4>;
1870 };
1871
1872 blsp2_uart1: serial@c1af000 {
1873 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1874 reg = <0x0c1af000 0x200>;
1875 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1876 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1877 <&gcc GCC_BLSP2_AHB_CLK>;
1878 clock-names = "core", "iface";
1879 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1880 dma-names = "tx", "rx";
1881 pinctrl-names = "default", "sleep";
1882 pinctrl-0 = <&blsp2_uart1_default>;
1883 pinctrl-1 = <&blsp2_uart1_sleep>;
1884 status = "disabled";
1885 };
1886
1887 blsp_i2c5: i2c@c1b5000 {
1888 compatible = "qcom,i2c-qup-v2.2.1";
1889 reg = <0x0c1b5000 0x600>;
1890 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1891
1892 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1893 <&gcc GCC_BLSP2_AHB_CLK>;
1894 clock-names = "core", "iface";
1895 clock-frequency = <400000>;
1896 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1897 dma-names = "tx", "rx";
1898
1899 pinctrl-names = "default", "sleep";
1900 pinctrl-0 = <&i2c5_default>;
1901 pinctrl-1 = <&i2c5_sleep>;
1902 #address-cells = <1>;
1903 #size-cells = <0>;
1904 status = "disabled";
1905 };
1906
1907 blsp_i2c6: i2c@c1b6000 {
1908 compatible = "qcom,i2c-qup-v2.2.1";
1909 reg = <0x0c1b6000 0x600>;
1910 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1911
1912 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1913 <&gcc GCC_BLSP2_AHB_CLK>;
1914 clock-names = "core", "iface";
1915 clock-frequency = <400000>;
1916 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1917 dma-names = "tx", "rx";
1918
1919 pinctrl-names = "default", "sleep";
1920 pinctrl-0 = <&i2c6_default>;
1921 pinctrl-1 = <&i2c6_sleep>;
1922 #address-cells = <1>;
1923 #size-cells = <0>;
1924 status = "disabled";
1925 };
1926
1927 blsp_i2c7: i2c@c1b7000 {
1928 compatible = "qcom,i2c-qup-v2.2.1";
1929 reg = <0x0c1b7000 0x600>;
1930 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1931
1932 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1933 <&gcc GCC_BLSP2_AHB_CLK>;
1934 clock-names = "core", "iface";
1935 clock-frequency = <400000>;
1936 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1937 dma-names = "tx", "rx";
1938
1939 pinctrl-names = "default", "sleep";
1940 pinctrl-0 = <&i2c7_default>;
1941 pinctrl-1 = <&i2c7_sleep>;
1942 #address-cells = <1>;
1943 #size-cells = <0>;
1944 status = "disabled";
1945 };
1946
1947 blsp_i2c8: i2c@c1b8000 {
1948 compatible = "qcom,i2c-qup-v2.2.1";
1949 reg = <0x0c1b8000 0x600>;
1950 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1951
1952 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1953 <&gcc GCC_BLSP2_AHB_CLK>;
1954 clock-names = "core", "iface";
1955 clock-frequency = <400000>;
1956 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1957 dma-names = "tx", "rx";
1958
1959 pinctrl-names = "default", "sleep";
1960 pinctrl-0 = <&i2c8_default>;
1961 pinctrl-1 = <&i2c8_sleep>;
1962 #address-cells = <1>;
1963 #size-cells = <0>;
1964 status = "disabled";
1965 };
1966
1967 sram@146bf000 {
1968 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1969 reg = <0x146bf000 0x1000>;
1970
1971 #address-cells = <1>;
1972 #size-cells = <1>;
1973
1974 ranges = <0 0x146bf000 0x1000>;
1975
1976 pil-reloc@94c {
1977 compatible = "qcom,pil-reloc-info";
1978 reg = <0x94c 0xc8>;
1979 };
1980 };
1981
1982 camss: camss@ca00020 {
1983 compatible = "qcom,sdm660-camss";
1984 reg = <0x0ca00020 0x10>,
1985 <0x0ca30000 0x100>,
1986 <0x0ca30400 0x100>,
1987 <0x0ca30800 0x100>,
1988 <0x0ca30c00 0x100>,
1989 <0x0c824000 0x1000>,
1990 <0x0ca00120 0x4>,
1991 <0x0c825000 0x1000>,
1992 <0x0ca00124 0x4>,
1993 <0x0c826000 0x1000>,
1994 <0x0ca00128 0x4>,
1995 <0x0ca31000 0x500>,
1996 <0x0ca10000 0x1000>,
1997 <0x0ca14000 0x1000>;
1998 reg-names = "csi_clk_mux",
1999 "csid0",
2000 "csid1",
2001 "csid2",
2002 "csid3",
2003 "csiphy0",
2004 "csiphy0_clk_mux",
2005 "csiphy1",
2006 "csiphy1_clk_mux",
2007 "csiphy2",
2008 "csiphy2_clk_mux",
2009 "ispif",
2010 "vfe0",
2011 "vfe1";
2012 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2013 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2014 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2015 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2016 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2017 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2018 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2019 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2020 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2021 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2022 interrupt-names = "csid0",
2023 "csid1",
2024 "csid2",
2025 "csid3",
2026 "csiphy0",
2027 "csiphy1",
2028 "csiphy2",
2029 "ispif",
2030 "vfe0",
2031 "vfe1";
2032 clocks = <&mmcc CAMSS_AHB_CLK>,
2033 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2034 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2035 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2036 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2037 <&mmcc CAMSS_CSI0_AHB_CLK>,
2038 <&mmcc CAMSS_CSI0_CLK>,
2039 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2040 <&mmcc CAMSS_CSI0PIX_CLK>,
2041 <&mmcc CAMSS_CSI0RDI_CLK>,
2042 <&mmcc CAMSS_CSI1_AHB_CLK>,
2043 <&mmcc CAMSS_CSI1_CLK>,
2044 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2045 <&mmcc CAMSS_CSI1PIX_CLK>,
2046 <&mmcc CAMSS_CSI1RDI_CLK>,
2047 <&mmcc CAMSS_CSI2_AHB_CLK>,
2048 <&mmcc CAMSS_CSI2_CLK>,
2049 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2050 <&mmcc CAMSS_CSI2PIX_CLK>,
2051 <&mmcc CAMSS_CSI2RDI_CLK>,
2052 <&mmcc CAMSS_CSI3_AHB_CLK>,
2053 <&mmcc CAMSS_CSI3_CLK>,
2054 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2055 <&mmcc CAMSS_CSI3PIX_CLK>,
2056 <&mmcc CAMSS_CSI3RDI_CLK>,
2057 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2058 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2059 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2060 <&mmcc CSIPHY_AHB2CRIF_CLK>,
2061 <&mmcc CAMSS_CSI_VFE0_CLK>,
2062 <&mmcc CAMSS_CSI_VFE1_CLK>,
2063 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2064 <&mmcc THROTTLE_CAMSS_AXI_CLK>,
2065 <&mmcc CAMSS_TOP_AHB_CLK>,
2066 <&mmcc CAMSS_VFE0_AHB_CLK>,
2067 <&mmcc CAMSS_VFE0_CLK>,
2068 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2069 <&mmcc CAMSS_VFE1_AHB_CLK>,
2070 <&mmcc CAMSS_VFE1_CLK>,
2071 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2072 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
2073 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;
2074 clock-names = "ahb",
2075 "cphy_csid0",
2076 "cphy_csid1",
2077 "cphy_csid2",
2078 "cphy_csid3",
2079 "csi0_ahb",
2080 "csi0",
2081 "csi0_phy",
2082 "csi0_pix",
2083 "csi0_rdi",
2084 "csi1_ahb",
2085 "csi1",
2086 "csi1_phy",
2087 "csi1_pix",
2088 "csi1_rdi",
2089 "csi2_ahb",
2090 "csi2",
2091 "csi2_phy",
2092 "csi2_pix",
2093 "csi2_rdi",
2094 "csi3_ahb",
2095 "csi3",
2096 "csi3_phy",
2097 "csi3_pix",
2098 "csi3_rdi",
2099 "csiphy0_timer",
2100 "csiphy1_timer",
2101 "csiphy2_timer",
2102 "csiphy_ahb2crif",
2103 "csi_vfe0",
2104 "csi_vfe1",
2105 "ispif_ahb",
2106 "throttle_axi",
2107 "top_ahb",
2108 "vfe0_ahb",
2109 "vfe0",
2110 "vfe0_stream",
2111 "vfe1_ahb",
2112 "vfe1",
2113 "vfe1_stream",
2114 "vfe_ahb",
2115 "vfe_axi";
2116 interconnects = <&mnoc 5 &bimc 5>;
2117 interconnect-names = "vfe-mem";
2118 iommus = <&mmss_smmu 0xc00>,
2119 <&mmss_smmu 0xc01>,
2120 <&mmss_smmu 0xc02>,
2121 <&mmss_smmu 0xc03>;
2122 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2123 <&mmcc CAMSS_VFE1_GDSC>;
2124 status = "disabled";
2125
2126 ports {
2127 #address-cells = <1>;
2128 #size-cells = <0>;
2129 };
2130 };
2131
2132 cci: cci@ca0c000 {
2133 compatible = "qcom,msm8996-cci";
2134 #address-cells = <1>;
2135 #size-cells = <0>;
2136 reg = <0x0ca0c000 0x1000>;
2137 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2138
2139 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2140 <&mmcc CAMSS_CCI_CLK>;
2141 assigned-clock-rates = <80800000>, <37500000>;
2142 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2143 <&mmcc CAMSS_CCI_AHB_CLK>,
2144 <&mmcc CAMSS_CCI_CLK>,
2145 <&mmcc CAMSS_AHB_CLK>;
2146 clock-names = "camss_top_ahb",
2147 "cci_ahb",
2148 "cci",
2149 "camss_ahb";
2150
2151 pinctrl-names = "default";
2152 pinctrl-0 = <&cci0_default &cci1_default>;
2153 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2154 status = "disabled";
2155
2156 cci_i2c0: i2c-bus@0 {
2157 reg = <0>;
2158 clock-frequency = <400000>;
2159 #address-cells = <1>;
2160 #size-cells = <0>;
2161 };
2162
2163 cci_i2c1: i2c-bus@1 {
2164 reg = <1>;
2165 clock-frequency = <400000>;
2166 #address-cells = <1>;
2167 #size-cells = <0>;
2168 };
2169 };
2170
2171 venus: video-codec@cc00000 {
2172 compatible = "qcom,sdm660-venus";
2173 reg = <0x0cc00000 0xff000>;
2174 clocks = <&mmcc VIDEO_CORE_CLK>,
2175 <&mmcc VIDEO_AHB_CLK>,
2176 <&mmcc VIDEO_AXI_CLK>,
2177 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
2178 clock-names = "core", "iface", "bus", "bus_throttle";
2179 interconnects = <&gnoc 0 &mnoc 13>,
2180 <&mnoc 4 &bimc 5>;
2181 interconnect-names = "cpu-cfg", "video-mem";
2182 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2183 iommus = <&mmss_smmu 0x400>,
2184 <&mmss_smmu 0x401>,
2185 <&mmss_smmu 0x40a>,
2186 <&mmss_smmu 0x407>,
2187 <&mmss_smmu 0x40e>,
2188 <&mmss_smmu 0x40f>,
2189 <&mmss_smmu 0x408>,
2190 <&mmss_smmu 0x409>,
2191 <&mmss_smmu 0x40b>,
2192 <&mmss_smmu 0x40c>,
2193 <&mmss_smmu 0x40d>,
2194 <&mmss_smmu 0x410>,
2195 <&mmss_smmu 0x421>,
2196 <&mmss_smmu 0x428>,
2197 <&mmss_smmu 0x429>,
2198 <&mmss_smmu 0x42b>,
2199 <&mmss_smmu 0x42c>,
2200 <&mmss_smmu 0x42d>,
2201 <&mmss_smmu 0x411>,
2202 <&mmss_smmu 0x431>;
2203 memory-region = <&venus_region>;
2204 power-domains = <&mmcc VENUS_GDSC>;
2205 status = "disabled";
2206
2207 video-decoder {
2208 compatible = "venus-decoder";
2209 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2210 clock-names = "vcodec0_core";
2211 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2212 };
2213
2214 video-encoder {
2215 compatible = "venus-encoder";
2216 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2217 clock-names = "vcodec0_core";
2218 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2219 };
2220 };
2221
2222 mmss_smmu: iommu@cd00000 {
2223 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2224 reg = <0x0cd00000 0x40000>;
2225
2226 clocks = <&mmcc MNOC_AHB_CLK>,
2227 <&mmcc BIMC_SMMU_AHB_CLK>,
2228 <&mmcc BIMC_SMMU_AXI_CLK>;
2229 clock-names = "iface-mm", "iface-smmu",
2230 "bus-smmu";
2231 #global-interrupts = <2>;
2232 #iommu-cells = <1>;
2233
2234 interrupts =
2235 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2237
2238 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2241 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2242 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2243 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2244 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2245 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2246 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2248 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2249 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2250 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2253 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2254 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2255 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2256 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2257 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
2258 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
2259 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2260 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
2261 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
2262
2263 status = "disabled";
2264 };
2265
2266 adsp_pil: remoteproc@15700000 {
2267 compatible = "qcom,sdm660-adsp-pas";
2268 reg = <0x15700000 0x4040>;
2269
2270 interrupts-extended =
2271 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2272 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2273 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2274 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2275 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2276 interrupt-names = "wdog", "fatal", "ready",
2277 "handover", "stop-ack";
2278
2279 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2280 clock-names = "xo";
2281
2282 memory-region = <&adsp_region>;
2283 power-domains = <&rpmpd SDM660_VDDCX>;
2284 power-domain-names = "cx";
2285
2286 qcom,smem-states = <&adsp_smp2p_out 0>;
2287 qcom,smem-state-names = "stop";
2288
2289 glink-edge {
2290 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2291
2292 label = "lpass";
2293 mboxes = <&apcs_glb 9>;
2294 qcom,remote-pid = <2>;
2295
2296 apr {
2297 compatible = "qcom,apr-v2";
2298 qcom,glink-channels = "apr_audio_svc";
2299 qcom,domain = <APR_DOMAIN_ADSP>;
2300 #address-cells = <1>;
2301 #size-cells = <0>;
2302
2303 service@3 {
2304 reg = <APR_SVC_ADSP_CORE>;
2305 compatible = "qcom,q6core";
2306 };
2307
2308 q6afe: service@4 {
2309 compatible = "qcom,q6afe";
2310 reg = <APR_SVC_AFE>;
2311 q6afedai: dais {
2312 compatible = "qcom,q6afe-dais";
2313 #address-cells = <1>;
2314 #size-cells = <0>;
2315 #sound-dai-cells = <1>;
2316 };
2317 };
2318
2319 q6asm: service@7 {
2320 compatible = "qcom,q6asm";
2321 reg = <APR_SVC_ASM>;
2322 q6asmdai: dais {
2323 compatible = "qcom,q6asm-dais";
2324 #address-cells = <1>;
2325 #size-cells = <0>;
2326 #sound-dai-cells = <1>;
2327 iommus = <&lpass_smmu 1>;
2328 };
2329 };
2330
2331 q6adm: service@8 {
2332 compatible = "qcom,q6adm";
2333 reg = <APR_SVC_ADM>;
2334 q6routing: routing {
2335 compatible = "qcom,q6adm-routing";
2336 #sound-dai-cells = <0>;
2337 };
2338 };
2339 };
2340 };
2341 };
2342
2343 gnoc: interconnect@17900000 {
2344 compatible = "qcom,sdm660-gnoc";
2345 reg = <0x17900000 0xe000>;
2346 #interconnect-cells = <1>;
2347 };
2348
2349 apcs_glb: mailbox@17911000 {
2350 compatible = "qcom,sdm660-apcs-hmss-global",
2351 "qcom,msm8994-apcs-kpss-global";
2352 reg = <0x17911000 0x1000>;
2353
2354 #mbox-cells = <1>;
2355 };
2356
2357 timer@17920000 {
2358 #address-cells = <1>;
2359 #size-cells = <1>;
2360 ranges;
2361 compatible = "arm,armv7-timer-mem";
2362 reg = <0x17920000 0x1000>;
2363 clock-frequency = <19200000>;
2364
2365 frame@17921000 {
2366 frame-number = <0>;
2367 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2369 reg = <0x17921000 0x1000>,
2370 <0x17922000 0x1000>;
2371 };
2372
2373 frame@17923000 {
2374 frame-number = <1>;
2375 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2376 reg = <0x17923000 0x1000>;
2377 status = "disabled";
2378 };
2379
2380 frame@17924000 {
2381 frame-number = <2>;
2382 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2383 reg = <0x17924000 0x1000>;
2384 status = "disabled";
2385 };
2386
2387 frame@17925000 {
2388 frame-number = <3>;
2389 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2390 reg = <0x17925000 0x1000>;
2391 status = "disabled";
2392 };
2393
2394 frame@17926000 {
2395 frame-number = <4>;
2396 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2397 reg = <0x17926000 0x1000>;
2398 status = "disabled";
2399 };
2400
2401 frame@17927000 {
2402 frame-number = <5>;
2403 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2404 reg = <0x17927000 0x1000>;
2405 status = "disabled";
2406 };
2407
2408 frame@17928000 {
2409 frame-number = <6>;
2410 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2411 reg = <0x17928000 0x1000>;
2412 status = "disabled";
2413 };
2414 };
2415
2416 intc: interrupt-controller@17a00000 {
2417 compatible = "arm,gic-v3";
2418 reg = <0x17a00000 0x10000>, /* GICD */
2419 <0x17b00000 0x100000>; /* GICR * 8 */
2420 #interrupt-cells = <3>;
2421 #address-cells = <1>;
2422 #size-cells = <1>;
2423 ranges;
2424 interrupt-controller;
2425 #redistributor-regions = <1>;
2426 redistributor-stride = <0x0 0x20000>;
2427 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2428 };
2429
2430 wifi: wifi@18800000 {
2431 compatible = "qcom,wcn3990-wifi";
2432 reg = <0x18800000 0x800000>;
2433 reg-names = "membase";
2434 memory-region = <&wlan_msa_mem>;
2435 clocks = <&rpmcc RPM_SMD_RF_CLK1_PIN>;
2436 clock-names = "cxo_ref_clk_pin";
2437 interrupts =
2438 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2439 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
2442 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
2443 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2448 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2449 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2450 iommus = <&anoc2_smmu 0x1a00>,
2451 <&anoc2_smmu 0x1a01>;
2452 qcom,snoc-host-cap-8bit-quirk;
2453 qcom,no-msa-ready-indicator;
2454 status = "disabled";
2455 };
2456 };
2457
2458 sound: sound {
2459 };
2460
2461 thermal-zones {
2462 aoss-thermal {
2463 polling-delay-passive = <250>;
2464
2465 thermal-sensors = <&tsens 0>;
2466
2467 trips {
2468 aoss_alert0: trip-point0 {
2469 temperature = <105000>;
2470 hysteresis = <1000>;
2471 type = "hot";
2472 };
2473 };
2474 };
2475
2476 cpuss0-thermal {
2477 polling-delay-passive = <250>;
2478
2479 thermal-sensors = <&tsens 1>;
2480
2481 trips {
2482 cpuss0_alert0: trip-point0 {
2483 temperature = <125000>;
2484 hysteresis = <1000>;
2485 type = "hot";
2486 };
2487 };
2488 };
2489
2490 cpuss1-thermal {
2491 polling-delay-passive = <250>;
2492
2493 thermal-sensors = <&tsens 2>;
2494
2495 trips {
2496 cpuss1_alert0: trip-point0 {
2497 temperature = <125000>;
2498 hysteresis = <1000>;
2499 type = "hot";
2500 };
2501 };
2502 };
2503
2504 cpu0-thermal {
2505 polling-delay-passive = <250>;
2506
2507 thermal-sensors = <&tsens 3>;
2508
2509 trips {
2510 cpu0_alert0: trip-point0 {
2511 temperature = <70000>;
2512 hysteresis = <1000>;
2513 type = "passive";
2514 };
2515
2516 cpu0_crit: cpu-crit {
2517 temperature = <110000>;
2518 hysteresis = <1000>;
2519 type = "critical";
2520 };
2521 };
2522 };
2523
2524 cpu1-thermal {
2525 polling-delay-passive = <250>;
2526
2527 thermal-sensors = <&tsens 4>;
2528
2529 trips {
2530 cpu1_alert0: trip-point0 {
2531 temperature = <70000>;
2532 hysteresis = <1000>;
2533 type = "passive";
2534 };
2535
2536 cpu1_crit: cpu-crit {
2537 temperature = <110000>;
2538 hysteresis = <1000>;
2539 type = "critical";
2540 };
2541 };
2542 };
2543
2544 cpu2-thermal {
2545 polling-delay-passive = <250>;
2546
2547 thermal-sensors = <&tsens 5>;
2548
2549 trips {
2550 cpu2_alert0: trip-point0 {
2551 temperature = <70000>;
2552 hysteresis = <1000>;
2553 type = "passive";
2554 };
2555
2556 cpu2_crit: cpu-crit {
2557 temperature = <110000>;
2558 hysteresis = <1000>;
2559 type = "critical";
2560 };
2561 };
2562 };
2563
2564 cpu3-thermal {
2565 polling-delay-passive = <250>;
2566
2567 thermal-sensors = <&tsens 6>;
2568
2569 trips {
2570 cpu3_alert0: trip-point0 {
2571 temperature = <70000>;
2572 hysteresis = <1000>;
2573 type = "passive";
2574 };
2575
2576 cpu3_crit: cpu-crit {
2577 temperature = <110000>;
2578 hysteresis = <1000>;
2579 type = "critical";
2580 };
2581 };
2582 };
2583
2584 /*
2585 * According to what downstream DTS says,
2586 * the entire power efficient cluster has
2587 * only a single thermal sensor.
2588 */
2589
2590 pwr-cluster-thermal {
2591 polling-delay-passive = <250>;
2592
2593 thermal-sensors = <&tsens 7>;
2594
2595 trips {
2596 pwr_cluster_alert0: trip-point0 {
2597 temperature = <70000>;
2598 hysteresis = <1000>;
2599 type = "passive";
2600 };
2601
2602 pwr_cluster_crit: cpu-crit {
2603 temperature = <110000>;
2604 hysteresis = <1000>;
2605 type = "critical";
2606 };
2607 };
2608 };
2609
2610 gpu-thermal {
2611 polling-delay-passive = <250>;
2612
2613 thermal-sensors = <&tsens 8>;
2614
2615 cooling-maps {
2616 map0 {
2617 trip = <&gpu_alert0>;
2618 cooling-device = <&adreno_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2619 };
2620 };
2621
2622 trips {
2623 gpu_alert0: trip-point0 {
2624 temperature = <85000>;
2625 hysteresis = <1000>;
2626 type = "passive";
2627 };
2628
2629 trip-point1 {
2630 temperature = <90000>;
2631 hysteresis = <1000>;
2632 type = "hot";
2633 };
2634
2635 trip-point2 {
2636 temperature = <110000>;
2637 hysteresis = <1000>;
2638 type = "critical";
2639 };
2640 };
2641 };
2642 };
2643
2644 timer {
2645 compatible = "arm,armv8-timer";
2646 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2647 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2648 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2649 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2650 };
2651};
2652