tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8#include <dt-bindings/clock/qcom,gcc-msm8996.h>
9#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
10#include <dt-bindings/clock/qcom,rpmcc.h>
11#include <dt-bindings/interconnect/qcom,msm8996.h>
12#include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
13#include <dt-bindings/firmware/qcom,scm.h>
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/power/qcom-rpmpd.h>
16#include <dt-bindings/soc/qcom,apr.h>
17#include <dt-bindings/thermal/thermal.h>
18
19/ {
20 interrupt-parent = <&intc>;
21
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 chosen { };
26
27 clocks {
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <19200000>;
32 clock-output-names = "xo_board";
33 };
34
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32764>;
39 clock-output-names = "sleep_clk";
40 };
41 };
42
43 cpus {
44 #address-cells = <2>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 device_type = "cpu";
49 compatible = "qcom,kryo";
50 reg = <0x0 0x0>;
51 enable-method = "psci";
52 cpu-idle-states = <&cpu_sleep_0>;
53 capacity-dmips-mhz = <1024>;
54 clocks = <&kryocc 0>;
55 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
56 operating-points-v2 = <&cluster0_opp>;
57 #cooling-cells = <2>;
58 next-level-cache = <&l2_0>;
59 l2_0: l2-cache {
60 compatible = "cache";
61 cache-level = <2>;
62 cache-unified;
63 };
64 };
65
66 cpu1: cpu@1 {
67 device_type = "cpu";
68 compatible = "qcom,kryo";
69 reg = <0x0 0x1>;
70 enable-method = "psci";
71 cpu-idle-states = <&cpu_sleep_0>;
72 capacity-dmips-mhz = <1024>;
73 clocks = <&kryocc 0>;
74 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
75 operating-points-v2 = <&cluster0_opp>;
76 #cooling-cells = <2>;
77 next-level-cache = <&l2_0>;
78 };
79
80 cpu2: cpu@100 {
81 device_type = "cpu";
82 compatible = "qcom,kryo";
83 reg = <0x0 0x100>;
84 enable-method = "psci";
85 cpu-idle-states = <&cpu_sleep_0>;
86 capacity-dmips-mhz = <1024>;
87 clocks = <&kryocc 1>;
88 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
89 operating-points-v2 = <&cluster1_opp>;
90 #cooling-cells = <2>;
91 next-level-cache = <&l2_1>;
92 l2_1: l2-cache {
93 compatible = "cache";
94 cache-level = <2>;
95 cache-unified;
96 };
97 };
98
99 cpu3: cpu@101 {
100 device_type = "cpu";
101 compatible = "qcom,kryo";
102 reg = <0x0 0x101>;
103 enable-method = "psci";
104 cpu-idle-states = <&cpu_sleep_0>;
105 capacity-dmips-mhz = <1024>;
106 clocks = <&kryocc 1>;
107 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
108 operating-points-v2 = <&cluster1_opp>;
109 #cooling-cells = <2>;
110 next-level-cache = <&l2_1>;
111 };
112
113 cpu-map {
114 cluster0 {
115 core0 {
116 cpu = <&cpu0>;
117 };
118
119 core1 {
120 cpu = <&cpu1>;
121 };
122 };
123
124 cluster1 {
125 core0 {
126 cpu = <&cpu2>;
127 };
128
129 core1 {
130 cpu = <&cpu3>;
131 };
132 };
133 };
134
135 idle-states {
136 entry-method = "psci";
137
138 cpu_sleep_0: cpu-sleep-0 {
139 compatible = "arm,idle-state";
140 idle-state-name = "standalone-power-collapse";
141 arm,psci-suspend-param = <0x00000004>;
142 entry-latency-us = <130>;
143 exit-latency-us = <80>;
144 min-residency-us = <300>;
145 };
146 };
147 };
148
149 cluster0_opp: opp-table-cluster0 {
150 compatible = "operating-points-v2-kryo-cpu";
151 nvmem-cells = <&speedbin_efuse>;
152 opp-shared;
153
154 /* Nominal fmax for now */
155 opp-307200000 {
156 opp-hz = /bits/ 64 <307200000>;
157 opp-supported-hw = <0xf>;
158 clock-latency-ns = <200000>;
159 opp-peak-kBps = <307200>;
160 };
161 opp-422400000 {
162 opp-hz = /bits/ 64 <422400000>;
163 opp-supported-hw = <0xf>;
164 clock-latency-ns = <200000>;
165 opp-peak-kBps = <307200>;
166 };
167 opp-480000000 {
168 opp-hz = /bits/ 64 <480000000>;
169 opp-supported-hw = <0xf>;
170 clock-latency-ns = <200000>;
171 opp-peak-kBps = <307200>;
172 };
173 opp-556800000 {
174 opp-hz = /bits/ 64 <556800000>;
175 opp-supported-hw = <0xf>;
176 clock-latency-ns = <200000>;
177 opp-peak-kBps = <307200>;
178 };
179 opp-652800000 {
180 opp-hz = /bits/ 64 <652800000>;
181 opp-supported-hw = <0xf>;
182 clock-latency-ns = <200000>;
183 opp-peak-kBps = <384000>;
184 };
185 opp-729600000 {
186 opp-hz = /bits/ 64 <729600000>;
187 opp-supported-hw = <0xf>;
188 clock-latency-ns = <200000>;
189 opp-peak-kBps = <460800>;
190 };
191 opp-844800000 {
192 opp-hz = /bits/ 64 <844800000>;
193 opp-supported-hw = <0xf>;
194 clock-latency-ns = <200000>;
195 opp-peak-kBps = <537600>;
196 };
197 opp-960000000 {
198 opp-hz = /bits/ 64 <960000000>;
199 opp-supported-hw = <0xf>;
200 clock-latency-ns = <200000>;
201 opp-peak-kBps = <672000>;
202 };
203 opp-1036800000 {
204 opp-hz = /bits/ 64 <1036800000>;
205 opp-supported-hw = <0xf>;
206 clock-latency-ns = <200000>;
207 opp-peak-kBps = <672000>;
208 };
209 opp-1113600000 {
210 opp-hz = /bits/ 64 <1113600000>;
211 opp-supported-hw = <0xf>;
212 clock-latency-ns = <200000>;
213 opp-peak-kBps = <825600>;
214 };
215 opp-1190400000 {
216 opp-hz = /bits/ 64 <1190400000>;
217 opp-supported-hw = <0xf>;
218 clock-latency-ns = <200000>;
219 opp-peak-kBps = <825600>;
220 };
221 opp-1228800000 {
222 opp-hz = /bits/ 64 <1228800000>;
223 opp-supported-hw = <0xf>;
224 clock-latency-ns = <200000>;
225 opp-peak-kBps = <902400>;
226 };
227 opp-1324800000 {
228 opp-hz = /bits/ 64 <1324800000>;
229 opp-supported-hw = <0xd>;
230 clock-latency-ns = <200000>;
231 opp-peak-kBps = <1056000>;
232 };
233 opp-1363200000 {
234 opp-hz = /bits/ 64 <1363200000>;
235 opp-supported-hw = <0x2>;
236 clock-latency-ns = <200000>;
237 opp-peak-kBps = <1132800>;
238 };
239 opp-1401600000 {
240 opp-hz = /bits/ 64 <1401600000>;
241 opp-supported-hw = <0xd>;
242 clock-latency-ns = <200000>;
243 opp-peak-kBps = <1132800>;
244 };
245 opp-1478400000 {
246 opp-hz = /bits/ 64 <1478400000>;
247 opp-supported-hw = <0x9>;
248 clock-latency-ns = <200000>;
249 opp-peak-kBps = <1190400>;
250 };
251 opp-1497600000 {
252 opp-hz = /bits/ 64 <1497600000>;
253 opp-supported-hw = <0x04>;
254 clock-latency-ns = <200000>;
255 opp-peak-kBps = <1305600>;
256 };
257 opp-1593600000 {
258 opp-hz = /bits/ 64 <1593600000>;
259 opp-supported-hw = <0x9>;
260 clock-latency-ns = <200000>;
261 opp-peak-kBps = <1382400>;
262 };
263 };
264
265 cluster1_opp: opp-table-cluster1 {
266 compatible = "operating-points-v2-kryo-cpu";
267 nvmem-cells = <&speedbin_efuse>;
268 opp-shared;
269
270 /* Nominal fmax for now */
271 opp-307200000 {
272 opp-hz = /bits/ 64 <307200000>;
273 opp-supported-hw = <0xf>;
274 clock-latency-ns = <200000>;
275 opp-peak-kBps = <307200>;
276 };
277 opp-403200000 {
278 opp-hz = /bits/ 64 <403200000>;
279 opp-supported-hw = <0xf>;
280 clock-latency-ns = <200000>;
281 opp-peak-kBps = <307200>;
282 };
283 opp-480000000 {
284 opp-hz = /bits/ 64 <480000000>;
285 opp-supported-hw = <0xf>;
286 clock-latency-ns = <200000>;
287 opp-peak-kBps = <307200>;
288 };
289 opp-556800000 {
290 opp-hz = /bits/ 64 <556800000>;
291 opp-supported-hw = <0xf>;
292 clock-latency-ns = <200000>;
293 opp-peak-kBps = <307200>;
294 };
295 opp-652800000 {
296 opp-hz = /bits/ 64 <652800000>;
297 opp-supported-hw = <0xf>;
298 clock-latency-ns = <200000>;
299 opp-peak-kBps = <307200>;
300 };
301 opp-729600000 {
302 opp-hz = /bits/ 64 <729600000>;
303 opp-supported-hw = <0xf>;
304 clock-latency-ns = <200000>;
305 opp-peak-kBps = <307200>;
306 };
307 opp-806400000 {
308 opp-hz = /bits/ 64 <806400000>;
309 opp-supported-hw = <0xf>;
310 clock-latency-ns = <200000>;
311 opp-peak-kBps = <384000>;
312 };
313 opp-883200000 {
314 opp-hz = /bits/ 64 <883200000>;
315 opp-supported-hw = <0xf>;
316 clock-latency-ns = <200000>;
317 opp-peak-kBps = <460800>;
318 };
319 opp-940800000 {
320 opp-hz = /bits/ 64 <940800000>;
321 opp-supported-hw = <0xf>;
322 clock-latency-ns = <200000>;
323 opp-peak-kBps = <537600>;
324 };
325 opp-1036800000 {
326 opp-hz = /bits/ 64 <1036800000>;
327 opp-supported-hw = <0xf>;
328 clock-latency-ns = <200000>;
329 opp-peak-kBps = <595200>;
330 };
331 opp-1113600000 {
332 opp-hz = /bits/ 64 <1113600000>;
333 opp-supported-hw = <0xf>;
334 clock-latency-ns = <200000>;
335 opp-peak-kBps = <672000>;
336 };
337 opp-1190400000 {
338 opp-hz = /bits/ 64 <1190400000>;
339 opp-supported-hw = <0xf>;
340 clock-latency-ns = <200000>;
341 opp-peak-kBps = <672000>;
342 };
343 opp-1248000000 {
344 opp-hz = /bits/ 64 <1248000000>;
345 opp-supported-hw = <0xf>;
346 clock-latency-ns = <200000>;
347 opp-peak-kBps = <748800>;
348 };
349 opp-1324800000 {
350 opp-hz = /bits/ 64 <1324800000>;
351 opp-supported-hw = <0xf>;
352 clock-latency-ns = <200000>;
353 opp-peak-kBps = <825600>;
354 };
355 opp-1401600000 {
356 opp-hz = /bits/ 64 <1401600000>;
357 opp-supported-hw = <0xf>;
358 clock-latency-ns = <200000>;
359 opp-peak-kBps = <902400>;
360 };
361 opp-1478400000 {
362 opp-hz = /bits/ 64 <1478400000>;
363 opp-supported-hw = <0xf>;
364 clock-latency-ns = <200000>;
365 opp-peak-kBps = <979200>;
366 };
367 opp-1555200000 {
368 opp-hz = /bits/ 64 <1555200000>;
369 opp-supported-hw = <0xf>;
370 clock-latency-ns = <200000>;
371 opp-peak-kBps = <1056000>;
372 };
373 opp-1632000000 {
374 opp-hz = /bits/ 64 <1632000000>;
375 opp-supported-hw = <0xf>;
376 clock-latency-ns = <200000>;
377 opp-peak-kBps = <1190400>;
378 };
379 opp-1708800000 {
380 opp-hz = /bits/ 64 <1708800000>;
381 opp-supported-hw = <0xf>;
382 clock-latency-ns = <200000>;
383 opp-peak-kBps = <1228800>;
384 };
385 opp-1785600000 {
386 opp-hz = /bits/ 64 <1785600000>;
387 opp-supported-hw = <0xf>;
388 clock-latency-ns = <200000>;
389 opp-peak-kBps = <1305600>;
390 };
391 opp-1804800000 {
392 opp-hz = /bits/ 64 <1804800000>;
393 opp-supported-hw = <0xe>;
394 clock-latency-ns = <200000>;
395 opp-peak-kBps = <1305600>;
396 };
397 opp-1824000000 {
398 opp-hz = /bits/ 64 <1824000000>;
399 opp-supported-hw = <0x1>;
400 clock-latency-ns = <200000>;
401 opp-peak-kBps = <1382400>;
402 };
403 opp-1900800000 {
404 opp-hz = /bits/ 64 <1900800000>;
405 opp-supported-hw = <0x4>;
406 clock-latency-ns = <200000>;
407 opp-peak-kBps = <1305600>;
408 };
409 opp-1920000000 {
410 opp-hz = /bits/ 64 <1920000000>;
411 opp-supported-hw = <0x1>;
412 clock-latency-ns = <200000>;
413 opp-peak-kBps = <1459200>;
414 };
415 opp-1996800000 {
416 opp-hz = /bits/ 64 <1996800000>;
417 opp-supported-hw = <0x1>;
418 clock-latency-ns = <200000>;
419 opp-peak-kBps = <1593600>;
420 };
421 opp-2073600000 {
422 opp-hz = /bits/ 64 <2073600000>;
423 opp-supported-hw = <0x1>;
424 clock-latency-ns = <200000>;
425 opp-peak-kBps = <1593600>;
426 };
427 opp-2150400000 {
428 opp-hz = /bits/ 64 <2150400000>;
429 opp-supported-hw = <0x1>;
430 clock-latency-ns = <200000>;
431 opp-peak-kBps = <1593600>;
432 };
433 };
434
435 firmware {
436 scm {
437 compatible = "qcom,scm-msm8996", "qcom,scm";
438 qcom,dload-mode = <&tcsr_2 0x13000>;
439 };
440 };
441
442 memory@80000000 {
443 device_type = "memory";
444 /* We expect the bootloader to fill in the reg */
445 reg = <0x0 0x80000000 0x0 0x0>;
446 };
447
448 etm {
449 compatible = "qcom,coresight-remote-etm";
450
451 out-ports {
452 port {
453 modem_etm_out_funnel_in2: endpoint {
454 remote-endpoint =
455 <&funnel_in2_in_modem_etm>;
456 };
457 };
458 };
459 };
460
461 psci {
462 compatible = "arm,psci-1.0";
463 method = "smc";
464 };
465
466 rpm: remoteproc {
467 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
468
469 glink-edge {
470 compatible = "qcom,glink-rpm";
471 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
472 qcom,rpm-msg-ram = <&rpm_msg_ram>;
473 mboxes = <&apcs_glb 0>;
474
475 rpm_requests: rpm-requests {
476 compatible = "qcom,rpm-msm8996", "qcom,glink-smd-rpm";
477 qcom,glink-channels = "rpm_requests";
478
479 rpmcc: clock-controller {
480 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
481 #clock-cells = <1>;
482 clocks = <&xo_board>;
483 clock-names = "xo";
484 };
485
486 rpmpd: power-controller {
487 compatible = "qcom,msm8996-rpmpd";
488 #power-domain-cells = <1>;
489 operating-points-v2 = <&rpmpd_opp_table>;
490
491 rpmpd_opp_table: opp-table {
492 compatible = "operating-points-v2";
493
494 rpmpd_opp1: opp1 {
495 opp-level = <1>;
496 };
497
498 rpmpd_opp2: opp2 {
499 opp-level = <2>;
500 };
501
502 rpmpd_opp3: opp3 {
503 opp-level = <3>;
504 };
505
506 rpmpd_opp4: opp4 {
507 opp-level = <4>;
508 };
509
510 rpmpd_opp5: opp5 {
511 opp-level = <5>;
512 };
513
514 rpmpd_opp6: opp6 {
515 opp-level = <6>;
516 };
517 };
518 };
519 };
520 };
521 };
522
523 reserved-memory {
524 #address-cells = <2>;
525 #size-cells = <2>;
526 ranges;
527
528 hyp_mem: memory@85800000 {
529 reg = <0x0 0x85800000 0x0 0x600000>;
530 no-map;
531 };
532
533 xbl_mem: memory@85e00000 {
534 reg = <0x0 0x85e00000 0x0 0x200000>;
535 no-map;
536 };
537
538 smem_mem: smem-mem@86000000 {
539 reg = <0x0 0x86000000 0x0 0x200000>;
540 no-map;
541 };
542
543 tz_mem: memory@86200000 {
544 reg = <0x0 0x86200000 0x0 0x2600000>;
545 no-map;
546 };
547
548 rmtfs_mem: rmtfs {
549 compatible = "qcom,rmtfs-mem";
550
551 size = <0x0 0x200000>;
552 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
553 no-map;
554
555 qcom,client-id = <1>;
556 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
557 };
558
559 mpss_mem: mpss@88800000 {
560 reg = <0x0 0x88800000 0x0 0x6200000>;
561 no-map;
562 };
563
564 adsp_mem: adsp@8ea00000 {
565 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
566 no-map;
567 };
568
569 slpi_mem: slpi@90500000 {
570 reg = <0x0 0x90500000 0x0 0xa00000>;
571 no-map;
572 };
573
574 gpu_mem: gpu@90f00000 {
575 compatible = "shared-dma-pool";
576 reg = <0x0 0x90f00000 0x0 0x100000>;
577 no-map;
578 };
579
580 venus_mem: venus@91000000 {
581 reg = <0x0 0x91000000 0x0 0x500000>;
582 no-map;
583 };
584
585 mba_mem: mba@91500000 {
586 reg = <0x0 0x91500000 0x0 0x200000>;
587 no-map;
588 };
589
590 mdata_mem: mpss-metadata {
591 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
592 size = <0x0 0x4000>;
593 no-map;
594 };
595 };
596
597 smem {
598 compatible = "qcom,smem";
599 memory-region = <&smem_mem>;
600 hwlocks = <&tcsr_mutex 3>;
601 };
602
603 smp2p-adsp {
604 compatible = "qcom,smp2p";
605 qcom,smem = <443>, <429>;
606
607 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
608
609 mboxes = <&apcs_glb 10>;
610
611 qcom,local-pid = <0>;
612 qcom,remote-pid = <2>;
613
614 adsp_smp2p_out: master-kernel {
615 qcom,entry-name = "master-kernel";
616 #qcom,smem-state-cells = <1>;
617 };
618
619 adsp_smp2p_in: slave-kernel {
620 qcom,entry-name = "slave-kernel";
621
622 interrupt-controller;
623 #interrupt-cells = <2>;
624 };
625 };
626
627 smp2p-mpss {
628 compatible = "qcom,smp2p";
629 qcom,smem = <435>, <428>;
630
631 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
632
633 mboxes = <&apcs_glb 14>;
634
635 qcom,local-pid = <0>;
636 qcom,remote-pid = <1>;
637
638 mpss_smp2p_out: master-kernel {
639 qcom,entry-name = "master-kernel";
640 #qcom,smem-state-cells = <1>;
641 };
642
643 mpss_smp2p_in: slave-kernel {
644 qcom,entry-name = "slave-kernel";
645
646 interrupt-controller;
647 #interrupt-cells = <2>;
648 };
649 };
650
651 smp2p-slpi {
652 compatible = "qcom,smp2p";
653 qcom,smem = <481>, <430>;
654
655 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
656
657 mboxes = <&apcs_glb 26>;
658
659 qcom,local-pid = <0>;
660 qcom,remote-pid = <3>;
661
662 slpi_smp2p_out: master-kernel {
663 qcom,entry-name = "master-kernel";
664 #qcom,smem-state-cells = <1>;
665 };
666
667 slpi_smp2p_in: slave-kernel {
668 qcom,entry-name = "slave-kernel";
669
670 interrupt-controller;
671 #interrupt-cells = <2>;
672 };
673 };
674
675 soc: soc@0 {
676 #address-cells = <1>;
677 #size-cells = <1>;
678 ranges = <0 0 0 0xffffffff>;
679 compatible = "simple-bus";
680
681 pcie_phy: phy-wrapper@34000 {
682 compatible = "qcom,msm8996-qmp-pcie-phy";
683 reg = <0x00034000 0x488>;
684 #address-cells = <1>;
685 #size-cells = <1>;
686 ranges = <0x0 0x00034000 0x4000>;
687
688 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
689 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
690 <&gcc GCC_PCIE_CLKREF_CLK>;
691 clock-names = "aux", "cfg_ahb", "ref";
692
693 resets = <&gcc GCC_PCIE_PHY_BCR>,
694 <&gcc GCC_PCIE_PHY_COM_BCR>,
695 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
696 reset-names = "phy", "common", "cfg";
697
698 status = "disabled";
699
700 pciephy_0: phy@1000 {
701 reg = <0x1000 0x130>,
702 <0x1200 0x200>,
703 <0x1400 0x1dc>;
704
705 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
706 clock-names = "pipe0";
707 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
708 reset-names = "lane0";
709
710 #clock-cells = <0>;
711 clock-output-names = "pcie_0_pipe_clk_src";
712
713 #phy-cells = <0>;
714 };
715
716 pciephy_1: phy@2000 {
717 reg = <0x2000 0x130>,
718 <0x2200 0x200>,
719 <0x2400 0x1dc>;
720
721 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
722 clock-names = "pipe1";
723 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
724 reset-names = "lane1";
725
726 #clock-cells = <0>;
727 clock-output-names = "pcie_1_pipe_clk_src";
728
729 #phy-cells = <0>;
730 };
731
732 pciephy_2: phy@3000 {
733 reg = <0x3000 0x130>,
734 <0x3200 0x200>,
735 <0x3400 0x1dc>;
736
737 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
738 clock-names = "pipe2";
739 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
740 reset-names = "lane2";
741
742 #clock-cells = <0>;
743 clock-output-names = "pcie_2_pipe_clk_src";
744
745 #phy-cells = <0>;
746 };
747 };
748
749 rpm_msg_ram: sram@68000 {
750 compatible = "qcom,rpm-msg-ram";
751 reg = <0x00068000 0x6000>;
752 };
753
754 qfprom@74000 {
755 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
756 reg = <0x00074000 0x8ff>;
757 #address-cells = <1>;
758 #size-cells = <1>;
759
760 qusb2p_hstx_trim: hstx-trim@24e {
761 reg = <0x24e 0x2>;
762 bits = <5 4>;
763 };
764
765 qusb2s_hstx_trim: hstx-trim@24f {
766 reg = <0x24f 0x1>;
767 bits = <1 4>;
768 };
769
770 speedbin_efuse: speedbin@133 {
771 reg = <0x133 0x1>;
772 bits = <5 3>;
773 };
774 };
775
776 rng: rng@83000 {
777 compatible = "qcom,prng-ee";
778 reg = <0x00083000 0x1000>;
779 clocks = <&gcc GCC_PRNG_AHB_CLK>;
780 clock-names = "core";
781 };
782
783 gcc: clock-controller@300000 {
784 compatible = "qcom,gcc-msm8996";
785 #clock-cells = <1>;
786 #reset-cells = <1>;
787 #power-domain-cells = <1>;
788 reg = <0x00300000 0x90000>;
789
790 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
791 <&rpmcc RPM_SMD_LN_BB_CLK>,
792 <&sleep_clk>,
793 <&pciephy_0>,
794 <&pciephy_1>,
795 <&pciephy_2>,
796 <&usb3phy>,
797 <&ufsphy 0>,
798 <&ufsphy 1>,
799 <&ufsphy 2>;
800 clock-names = "cxo",
801 "cxo2",
802 "sleep_clk",
803 "pcie_0_pipe_clk_src",
804 "pcie_1_pipe_clk_src",
805 "pcie_2_pipe_clk_src",
806 "usb3_phy_pipe_clk_src",
807 "ufs_rx_symbol_0_clk_src",
808 "ufs_rx_symbol_1_clk_src",
809 "ufs_tx_symbol_0_clk_src";
810 };
811
812 bimc: interconnect@408000 {
813 compatible = "qcom,msm8996-bimc";
814 reg = <0x00408000 0x5a000>;
815 #interconnect-cells = <1>;
816 };
817
818 tsens0: thermal-sensor@4a9000 {
819 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
820 reg = <0x004a9000 0x1000>, /* TM */
821 <0x004a8000 0x1000>; /* SROT */
822 #qcom,sensors = <13>;
823 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
825 interrupt-names = "uplow", "critical";
826 #thermal-sensor-cells = <1>;
827 };
828
829 tsens1: thermal-sensor@4ad000 {
830 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
831 reg = <0x004ad000 0x1000>, /* TM */
832 <0x004ac000 0x1000>; /* SROT */
833 #qcom,sensors = <8>;
834 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "uplow", "critical";
837 #thermal-sensor-cells = <1>;
838 };
839
840 cryptobam: dma-controller@644000 {
841 compatible = "qcom,bam-v1.7.0";
842 reg = <0x00644000 0x24000>;
843 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&gcc GCC_CE1_CLK>;
845 clock-names = "bam_clk";
846 #dma-cells = <1>;
847 qcom,ee = <0>;
848 qcom,controlled-remotely;
849 };
850
851 crypto: crypto@67a000 {
852 compatible = "qcom,crypto-v5.4";
853 reg = <0x0067a000 0x6000>;
854 clocks = <&gcc GCC_CE1_AHB_CLK>,
855 <&gcc GCC_CE1_AXI_CLK>,
856 <&gcc GCC_CE1_CLK>;
857 clock-names = "iface", "bus", "core";
858 dmas = <&cryptobam 6>, <&cryptobam 7>;
859 dma-names = "rx", "tx";
860 };
861
862 cnoc: interconnect@500000 {
863 compatible = "qcom,msm8996-cnoc";
864 reg = <0x00500000 0x1000>;
865 #interconnect-cells = <1>;
866 };
867
868 snoc: interconnect@524000 {
869 compatible = "qcom,msm8996-snoc";
870 reg = <0x00524000 0x1c000>;
871 #interconnect-cells = <1>;
872 };
873
874 a0noc: interconnect@543000 {
875 compatible = "qcom,msm8996-a0noc";
876 reg = <0x00543000 0x6000>;
877 #interconnect-cells = <1>;
878 clock-names = "aggre0_snoc_axi",
879 "aggre0_cnoc_ahb",
880 "aggre0_noc_mpu_cfg";
881 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
882 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
883 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
884 power-domains = <&gcc AGGRE0_NOC_GDSC>;
885 };
886
887 a1noc: interconnect@562000 {
888 compatible = "qcom,msm8996-a1noc";
889 reg = <0x00562000 0x5000>;
890 #interconnect-cells = <1>;
891 };
892
893 a2noc: interconnect@583000 {
894 compatible = "qcom,msm8996-a2noc";
895 reg = <0x00583000 0x7000>;
896 #interconnect-cells = <1>;
897 clock-names = "aggre2_ufs_axi", "ufs_axi";
898 clocks = <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
899 <&gcc GCC_UFS_AXI_CLK>;
900 };
901
902 mnoc: interconnect@5a4000 {
903 compatible = "qcom,msm8996-mnoc";
904 reg = <0x005a4000 0x1c000>;
905 #interconnect-cells = <1>;
906 clock-names = "iface";
907 clocks = <&mmcc AHB_CLK_SRC>;
908 };
909
910 pnoc: interconnect@5c0000 {
911 compatible = "qcom,msm8996-pnoc";
912 reg = <0x005c0000 0x3000>;
913 #interconnect-cells = <1>;
914 };
915
916 tcsr_mutex: hwlock@740000 {
917 compatible = "qcom,tcsr-mutex";
918 reg = <0x00740000 0x20000>;
919 #hwlock-cells = <1>;
920 };
921
922 tcsr_1: syscon@760000 {
923 compatible = "qcom,tcsr-msm8996", "syscon";
924 reg = <0x00760000 0x20000>;
925 };
926
927 tcsr_2: syscon@7a0000 {
928 compatible = "qcom,tcsr-msm8996", "syscon";
929 reg = <0x007a0000 0x18000>;
930 };
931
932 mmcc: clock-controller@8c0000 {
933 compatible = "qcom,mmcc-msm8996";
934 #clock-cells = <1>;
935 #reset-cells = <1>;
936 #power-domain-cells = <1>;
937 reg = <0x008c0000 0x40000>;
938 clocks = <&xo_board>,
939 <&gcc GPLL0>,
940 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
941 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
942 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
943 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
944 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
945 <&mdss_hdmi_phy>;
946 clock-names = "xo",
947 "gpll0",
948 "gcc_mmss_noc_cfg_ahb_clk",
949 "dsi0pll",
950 "dsi0pllbyte",
951 "dsi1pll",
952 "dsi1pllbyte",
953 "hdmipll";
954 assigned-clocks = <&mmcc MMPLL9_PLL>,
955 <&mmcc MMPLL1_PLL>,
956 <&mmcc MMPLL3_PLL>,
957 <&mmcc MMPLL4_PLL>,
958 <&mmcc MMPLL5_PLL>;
959 assigned-clock-rates = <624000000>,
960 <810000000>,
961 <980000000>,
962 <960000000>,
963 <825000000>;
964 };
965
966 mdss: display-subsystem@900000 {
967 compatible = "qcom,mdss";
968
969 reg = <0x00900000 0x1000>,
970 <0x009b0000 0x1040>,
971 <0x009b8000 0x1040>;
972 reg-names = "mdss_phys",
973 "vbif_phys",
974 "vbif_nrt_phys";
975
976 power-domains = <&mmcc MDSS_GDSC>;
977 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
978
979 interrupt-controller;
980 #interrupt-cells = <1>;
981
982 clocks = <&mmcc MDSS_AHB_CLK>,
983 <&mmcc MDSS_MDP_CLK>;
984 clock-names = "iface", "core";
985
986 resets = <&mmcc MDSS_BCR>;
987
988 #address-cells = <1>;
989 #size-cells = <1>;
990 ranges;
991
992 status = "disabled";
993
994 mdp: display-controller@901000 {
995 compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
996 reg = <0x00901000 0x90000>;
997 reg-names = "mdp_phys";
998
999 interrupt-parent = <&mdss>;
1000 interrupts = <0>;
1001
1002 clocks = <&mmcc MDSS_AHB_CLK>,
1003 <&mmcc MDSS_AXI_CLK>,
1004 <&mmcc MDSS_MDP_CLK>,
1005 <&mmcc SMMU_MDP_AXI_CLK>,
1006 <&mmcc MDSS_VSYNC_CLK>;
1007 clock-names = "iface",
1008 "bus",
1009 "core",
1010 "iommu",
1011 "vsync";
1012
1013 iommus = <&mdp_smmu 0>;
1014
1015 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1016 <&mmcc MDSS_VSYNC_CLK>;
1017 assigned-clock-rates = <300000000>,
1018 <19200000>;
1019
1020 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1021 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
1022 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
1023 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1024
1025 ports {
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1028
1029 port@0 {
1030 reg = <0>;
1031 mdp5_intf3_out: endpoint {
1032 remote-endpoint = <&mdss_hdmi_in>;
1033 };
1034 };
1035
1036 port@1 {
1037 reg = <1>;
1038 mdp5_intf1_out: endpoint {
1039 remote-endpoint = <&mdss_dsi0_in>;
1040 };
1041 };
1042
1043 port@2 {
1044 reg = <2>;
1045 mdp5_intf2_out: endpoint {
1046 remote-endpoint = <&mdss_dsi1_in>;
1047 };
1048 };
1049 };
1050 };
1051
1052 mdss_dsi0: dsi@994000 {
1053 compatible = "qcom,msm8996-dsi-ctrl",
1054 "qcom,mdss-dsi-ctrl";
1055 reg = <0x00994000 0x400>;
1056 reg-names = "dsi_ctrl";
1057
1058 interrupt-parent = <&mdss>;
1059 interrupts = <4>;
1060
1061 clocks = <&mmcc MDSS_MDP_CLK>,
1062 <&mmcc MDSS_BYTE0_CLK>,
1063 <&mmcc MDSS_AHB_CLK>,
1064 <&mmcc MDSS_AXI_CLK>,
1065 <&mmcc MMSS_MISC_AHB_CLK>,
1066 <&mmcc MDSS_PCLK0_CLK>,
1067 <&mmcc MDSS_ESC0_CLK>;
1068 clock-names = "mdp_core",
1069 "byte",
1070 "iface",
1071 "bus",
1072 "core_mmss",
1073 "pixel",
1074 "core";
1075 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1076 <&mmcc PCLK0_CLK_SRC>;
1077 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1078 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
1079
1080 phys = <&mdss_dsi0_phy>;
1081 status = "disabled";
1082
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085
1086 ports {
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1089
1090 port@0 {
1091 reg = <0>;
1092 mdss_dsi0_in: endpoint {
1093 remote-endpoint = <&mdp5_intf1_out>;
1094 };
1095 };
1096
1097 port@1 {
1098 reg = <1>;
1099 mdss_dsi0_out: endpoint {
1100 };
1101 };
1102 };
1103 };
1104
1105 mdss_dsi0_phy: phy@994400 {
1106 compatible = "qcom,dsi-phy-14nm";
1107 reg = <0x00994400 0x100>,
1108 <0x00994500 0x300>,
1109 <0x00994800 0x188>;
1110 reg-names = "dsi_phy",
1111 "dsi_phy_lane",
1112 "dsi_pll";
1113
1114 #clock-cells = <1>;
1115 #phy-cells = <0>;
1116
1117 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1118 clock-names = "iface", "ref";
1119 status = "disabled";
1120 };
1121
1122 mdss_dsi1: dsi@996000 {
1123 compatible = "qcom,msm8996-dsi-ctrl",
1124 "qcom,mdss-dsi-ctrl";
1125 reg = <0x00996000 0x400>;
1126 reg-names = "dsi_ctrl";
1127
1128 interrupt-parent = <&mdss>;
1129 interrupts = <5>;
1130
1131 clocks = <&mmcc MDSS_MDP_CLK>,
1132 <&mmcc MDSS_BYTE1_CLK>,
1133 <&mmcc MDSS_AHB_CLK>,
1134 <&mmcc MDSS_AXI_CLK>,
1135 <&mmcc MMSS_MISC_AHB_CLK>,
1136 <&mmcc MDSS_PCLK1_CLK>,
1137 <&mmcc MDSS_ESC1_CLK>;
1138 clock-names = "mdp_core",
1139 "byte",
1140 "iface",
1141 "bus",
1142 "core_mmss",
1143 "pixel",
1144 "core";
1145 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
1146 <&mmcc PCLK1_CLK_SRC>;
1147 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
1148 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;
1149
1150 phys = <&mdss_dsi1_phy>;
1151 status = "disabled";
1152
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1155
1156 ports {
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1159
1160 port@0 {
1161 reg = <0>;
1162 mdss_dsi1_in: endpoint {
1163 remote-endpoint = <&mdp5_intf2_out>;
1164 };
1165 };
1166
1167 port@1 {
1168 reg = <1>;
1169 mdss_dsi1_out: endpoint {
1170 };
1171 };
1172 };
1173 };
1174
1175 mdss_dsi1_phy: phy@996400 {
1176 compatible = "qcom,dsi-phy-14nm";
1177 reg = <0x00996400 0x100>,
1178 <0x00996500 0x300>,
1179 <0x00996800 0x188>;
1180 reg-names = "dsi_phy",
1181 "dsi_phy_lane",
1182 "dsi_pll";
1183
1184 #clock-cells = <1>;
1185 #phy-cells = <0>;
1186
1187 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1188 clock-names = "iface", "ref";
1189 status = "disabled";
1190 };
1191
1192 mdss_hdmi: hdmi-tx@9a0000 {
1193 compatible = "qcom,hdmi-tx-8996";
1194 reg = <0x009a0000 0x50c>,
1195 <0x00070000 0x6158>,
1196 <0x009e0000 0xfff>;
1197 reg-names = "core_physical",
1198 "qfprom_physical",
1199 "hdcp_physical";
1200
1201 interrupt-parent = <&mdss>;
1202 interrupts = <8>;
1203
1204 clocks = <&mmcc MDSS_MDP_CLK>,
1205 <&mmcc MDSS_AHB_CLK>,
1206 <&mmcc MDSS_HDMI_CLK>,
1207 <&mmcc MDSS_HDMI_AHB_CLK>,
1208 <&mmcc MDSS_EXTPCLK_CLK>;
1209 clock-names =
1210 "mdp_core",
1211 "iface",
1212 "core",
1213 "alt_iface",
1214 "extp";
1215
1216 phys = <&mdss_hdmi_phy>;
1217 #sound-dai-cells = <1>;
1218
1219 status = "disabled";
1220
1221 ports {
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1224
1225 port@0 {
1226 reg = <0>;
1227 mdss_hdmi_in: endpoint {
1228 remote-endpoint = <&mdp5_intf3_out>;
1229 };
1230 };
1231 };
1232 };
1233
1234 mdss_hdmi_phy: phy@9a0600 {
1235 #phy-cells = <0>;
1236 compatible = "qcom,hdmi-phy-8996";
1237 reg = <0x009a0600 0x1c4>,
1238 <0x009a0a00 0x124>,
1239 <0x009a0c00 0x124>,
1240 <0x009a0e00 0x124>,
1241 <0x009a1000 0x124>,
1242 <0x009a1200 0x0c8>;
1243 reg-names = "hdmi_pll",
1244 "hdmi_tx_l0",
1245 "hdmi_tx_l1",
1246 "hdmi_tx_l2",
1247 "hdmi_tx_l3",
1248 "hdmi_phy";
1249
1250 clocks = <&mmcc MDSS_AHB_CLK>,
1251 <&gcc GCC_HDMI_CLKREF_CLK>,
1252 <&xo_board>;
1253 clock-names = "iface",
1254 "ref",
1255 "xo";
1256
1257 #clock-cells = <0>;
1258
1259 status = "disabled";
1260 };
1261 };
1262
1263 gpu: gpu@b00000 {
1264 compatible = "qcom,adreno-530.2", "qcom,adreno";
1265
1266 reg = <0x00b00000 0x3f000>;
1267 reg-names = "kgsl_3d0_reg_memory";
1268
1269 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1270
1271 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1272 <&mmcc GPU_AHB_CLK>,
1273 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1274 <&gcc GCC_BIMC_GFX_CLK>,
1275 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1276
1277 clock-names = "core",
1278 "iface",
1279 "rbbmtimer",
1280 "mem",
1281 "mem_iface";
1282
1283 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
1284 interconnect-names = "gfx-mem";
1285
1286 power-domains = <&mmcc GPU_GX_GDSC>;
1287 iommus = <&adreno_smmu 0>;
1288
1289 nvmem-cells = <&speedbin_efuse>;
1290 nvmem-cell-names = "speed_bin";
1291
1292 operating-points-v2 = <&gpu_opp_table>;
1293
1294 status = "disabled";
1295
1296 #cooling-cells = <2>;
1297
1298 gpu_opp_table: opp-table {
1299 compatible = "operating-points-v2";
1300
1301 /*
1302 * 624Mhz is only available on speed bins 0 and 3.
1303 * 560Mhz is only available on speed bins 0, 2 and 3.
1304 * All the rest are available on all bins of the hardware.
1305 */
1306 opp-624000000 {
1307 opp-hz = /bits/ 64 <624000000>;
1308 opp-supported-hw = <0x09>;
1309 };
1310 opp-560000000 {
1311 opp-hz = /bits/ 64 <560000000>;
1312 opp-supported-hw = <0x0d>;
1313 };
1314 opp-510000000 {
1315 opp-hz = /bits/ 64 <510000000>;
1316 opp-supported-hw = <0xff>;
1317 };
1318 opp-401800000 {
1319 opp-hz = /bits/ 64 <401800000>;
1320 opp-supported-hw = <0xff>;
1321 };
1322 opp-315000000 {
1323 opp-hz = /bits/ 64 <315000000>;
1324 opp-supported-hw = <0xff>;
1325 };
1326 opp-214000000 {
1327 opp-hz = /bits/ 64 <214000000>;
1328 opp-supported-hw = <0xff>;
1329 };
1330 opp-133000000 {
1331 opp-hz = /bits/ 64 <133000000>;
1332 opp-supported-hw = <0xff>;
1333 };
1334 };
1335
1336 zap-shader {
1337 memory-region = <&gpu_mem>;
1338 };
1339 };
1340
1341 tlmm: pinctrl@1010000 {
1342 compatible = "qcom,msm8996-pinctrl";
1343 reg = <0x01010000 0x300000>;
1344 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1345 gpio-controller;
1346 gpio-ranges = <&tlmm 0 0 150>;
1347 #gpio-cells = <2>;
1348 interrupt-controller;
1349 #interrupt-cells = <2>;
1350
1351 blsp1_spi1_default: blsp1-spi1-default-state {
1352 spi-pins {
1353 pins = "gpio0", "gpio1", "gpio3";
1354 function = "blsp_spi1";
1355 drive-strength = <12>;
1356 bias-disable;
1357 };
1358
1359 cs-pins {
1360 pins = "gpio2";
1361 function = "gpio";
1362 drive-strength = <16>;
1363 bias-disable;
1364 output-high;
1365 };
1366 };
1367
1368 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1369 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1370 function = "gpio";
1371 drive-strength = <2>;
1372 bias-pull-down;
1373 };
1374
1375 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1376 pins = "gpio4", "gpio5";
1377 function = "blsp_uart8";
1378 drive-strength = <16>;
1379 bias-disable;
1380 };
1381
1382 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1383 pins = "gpio4", "gpio5";
1384 function = "gpio";
1385 drive-strength = <2>;
1386 bias-disable;
1387 };
1388
1389 blsp2_i2c2_default: blsp2-i2c2-state {
1390 pins = "gpio6", "gpio7";
1391 function = "blsp_i2c8";
1392 drive-strength = <16>;
1393 bias-disable;
1394 };
1395
1396 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1397 pins = "gpio6", "gpio7";
1398 function = "gpio";
1399 drive-strength = <2>;
1400 bias-disable;
1401 };
1402
1403 blsp1_i2c6_default: blsp1-i2c6-state {
1404 pins = "gpio27", "gpio28";
1405 function = "blsp_i2c6";
1406 drive-strength = <16>;
1407 bias-disable;
1408 };
1409
1410 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1411 pins = "gpio27", "gpio28";
1412 function = "gpio";
1413 drive-strength = <2>;
1414 bias-pull-up;
1415 };
1416
1417 cci0_default: cci0-default-state {
1418 pins = "gpio17", "gpio18";
1419 function = "cci_i2c";
1420 drive-strength = <16>;
1421 bias-disable;
1422 };
1423
1424 camera0_state_on:
1425 camera_rear_default: camera-rear-default-state {
1426 camera0_mclk: mclk0-pins {
1427 pins = "gpio13";
1428 function = "cam_mclk";
1429 drive-strength = <16>;
1430 bias-disable;
1431 };
1432
1433 camera0_rst: rst-pins {
1434 pins = "gpio25";
1435 function = "gpio";
1436 drive-strength = <16>;
1437 bias-disable;
1438 };
1439
1440 camera0_pwdn: pwdn-pins {
1441 pins = "gpio26";
1442 function = "gpio";
1443 drive-strength = <16>;
1444 bias-disable;
1445 };
1446 };
1447
1448 cci1_default: cci1-default-state {
1449 pins = "gpio19", "gpio20";
1450 function = "cci_i2c";
1451 drive-strength = <16>;
1452 bias-disable;
1453 };
1454
1455 camera1_state_on:
1456 camera_board_default: camera-board-default-state {
1457 mclk1-pins {
1458 pins = "gpio14";
1459 function = "cam_mclk";
1460 drive-strength = <16>;
1461 bias-disable;
1462 };
1463
1464 pwdn-pins {
1465 pins = "gpio98";
1466 function = "gpio";
1467 drive-strength = <16>;
1468 bias-disable;
1469 };
1470
1471 rst-pins {
1472 pins = "gpio104";
1473 function = "gpio";
1474 drive-strength = <16>;
1475 bias-disable;
1476 };
1477 };
1478
1479 camera2_state_on:
1480 camera_front_default: camera-front-default-state {
1481 camera2_mclk: mclk2-pins {
1482 pins = "gpio15";
1483 function = "cam_mclk";
1484 drive-strength = <16>;
1485 bias-disable;
1486 };
1487
1488 camera2_rst: rst-pins {
1489 pins = "gpio23";
1490 function = "gpio";
1491 drive-strength = <16>;
1492 bias-disable;
1493 };
1494
1495 pwdn-pins {
1496 pins = "gpio133";
1497 function = "gpio";
1498 drive-strength = <16>;
1499 bias-disable;
1500 };
1501 };
1502
1503 pcie0_state_on: pcie0-state-on-state {
1504 perst-pins {
1505 pins = "gpio35";
1506 function = "gpio";
1507 drive-strength = <2>;
1508 bias-pull-down;
1509 };
1510
1511 clkreq-pins {
1512 pins = "gpio36";
1513 function = "pci_e0";
1514 drive-strength = <2>;
1515 bias-pull-up;
1516 };
1517
1518 wake-pins {
1519 pins = "gpio37";
1520 function = "gpio";
1521 drive-strength = <2>;
1522 bias-pull-up;
1523 };
1524 };
1525
1526 pcie0_state_off: pcie0-state-off-state {
1527 perst-pins {
1528 pins = "gpio35";
1529 function = "gpio";
1530 drive-strength = <2>;
1531 bias-pull-down;
1532 };
1533
1534 clkreq-pins {
1535 pins = "gpio36";
1536 function = "gpio";
1537 drive-strength = <2>;
1538 bias-disable;
1539 };
1540
1541 wake-pins {
1542 pins = "gpio37";
1543 function = "gpio";
1544 drive-strength = <2>;
1545 bias-disable;
1546 };
1547 };
1548
1549 blsp1_uart2_default: blsp1-uart2-default-state {
1550 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1551 function = "blsp_uart2";
1552 drive-strength = <16>;
1553 bias-disable;
1554 };
1555
1556 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1557 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1558 function = "gpio";
1559 drive-strength = <2>;
1560 bias-disable;
1561 };
1562
1563 blsp1_i2c3_default: blsp1-i2c3-default-state {
1564 pins = "gpio47", "gpio48";
1565 function = "blsp_i2c3";
1566 drive-strength = <16>;
1567 bias-disable;
1568 };
1569
1570 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1571 pins = "gpio47", "gpio48";
1572 function = "gpio";
1573 drive-strength = <2>;
1574 bias-disable;
1575 };
1576
1577 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1578 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1579 function = "blsp_uart9";
1580 drive-strength = <16>;
1581 bias-disable;
1582 };
1583
1584 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1585 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1586 function = "blsp_uart9";
1587 drive-strength = <2>;
1588 bias-disable;
1589 };
1590
1591 blsp2_i2c3_default: blsp2-i2c3-state-state {
1592 pins = "gpio51", "gpio52";
1593 function = "blsp_i2c9";
1594 drive-strength = <16>;
1595 bias-disable;
1596 };
1597
1598 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1599 pins = "gpio51", "gpio52";
1600 function = "gpio";
1601 drive-strength = <2>;
1602 bias-disable;
1603 };
1604
1605 wcd_intr_default: wcd-intr-default-state {
1606 pins = "gpio54";
1607 function = "gpio";
1608 drive-strength = <2>;
1609 bias-pull-down;
1610 };
1611
1612 blsp2_i2c1_default: blsp2-i2c1-state {
1613 pins = "gpio55", "gpio56";
1614 function = "blsp_i2c7";
1615 drive-strength = <16>;
1616 bias-disable;
1617 };
1618
1619 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1620 pins = "gpio55", "gpio56";
1621 function = "gpio";
1622 drive-strength = <2>;
1623 bias-disable;
1624 };
1625
1626 blsp2_i2c5_default: blsp2-i2c5-state {
1627 pins = "gpio60", "gpio61";
1628 function = "blsp_i2c11";
1629 drive-strength = <2>;
1630 bias-disable;
1631 };
1632
1633 /* Sleep state for BLSP2_I2C5 is missing.. */
1634
1635 cdc_reset_active: cdc-reset-active-state {
1636 pins = "gpio64";
1637 function = "gpio";
1638 drive-strength = <16>;
1639 bias-pull-down;
1640 output-high;
1641 };
1642
1643 cdc_reset_sleep: cdc-reset-sleep-state {
1644 pins = "gpio64";
1645 function = "gpio";
1646 drive-strength = <16>;
1647 bias-disable;
1648 output-low;
1649 };
1650
1651 blsp2_spi6_default: blsp2-spi6-default-state {
1652 spi-pins {
1653 pins = "gpio85", "gpio86", "gpio88";
1654 function = "blsp_spi12";
1655 drive-strength = <12>;
1656 bias-disable;
1657 };
1658
1659 cs-pins {
1660 pins = "gpio87";
1661 function = "gpio";
1662 drive-strength = <16>;
1663 bias-disable;
1664 output-high;
1665 };
1666 };
1667
1668 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1669 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1670 function = "gpio";
1671 drive-strength = <2>;
1672 bias-pull-down;
1673 };
1674
1675 blsp2_i2c6_default: blsp2-i2c6-state {
1676 pins = "gpio87", "gpio88";
1677 function = "blsp_i2c12";
1678 drive-strength = <16>;
1679 bias-disable;
1680 };
1681
1682 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1683 pins = "gpio87", "gpio88";
1684 function = "gpio";
1685 drive-strength = <2>;
1686 bias-disable;
1687 };
1688
1689 pcie1_state_on: pcie1-on-state {
1690 perst-pins {
1691 pins = "gpio130";
1692 function = "gpio";
1693 drive-strength = <2>;
1694 bias-pull-down;
1695 };
1696
1697 clkreq-pins {
1698 pins = "gpio131";
1699 function = "pci_e1";
1700 drive-strength = <2>;
1701 bias-pull-up;
1702 };
1703
1704 wake-pins {
1705 pins = "gpio132";
1706 function = "gpio";
1707 drive-strength = <2>;
1708 bias-pull-down;
1709 };
1710 };
1711
1712 pcie1_state_off: pcie1-off-state {
1713 /* Perst is missing? */
1714 clkreq-pins {
1715 pins = "gpio131";
1716 function = "gpio";
1717 drive-strength = <2>;
1718 bias-disable;
1719 };
1720
1721 wake-pins {
1722 pins = "gpio132";
1723 function = "gpio";
1724 drive-strength = <2>;
1725 bias-disable;
1726 };
1727 };
1728
1729 pcie2_state_on: pcie2-on-state {
1730 perst-pins {
1731 pins = "gpio114";
1732 function = "gpio";
1733 drive-strength = <2>;
1734 bias-pull-down;
1735 };
1736
1737 clkreq-pins {
1738 pins = "gpio115";
1739 function = "pci_e2";
1740 drive-strength = <2>;
1741 bias-pull-up;
1742 };
1743
1744 wake-pins {
1745 pins = "gpio116";
1746 function = "gpio";
1747 drive-strength = <2>;
1748 bias-pull-down;
1749 };
1750 };
1751
1752 pcie2_state_off: pcie2-off-state {
1753 /* Perst is missing? */
1754 clkreq-pins {
1755 pins = "gpio115";
1756 function = "gpio";
1757 drive-strength = <2>;
1758 bias-disable;
1759 };
1760
1761 wake-pins {
1762 pins = "gpio116";
1763 function = "gpio";
1764 drive-strength = <2>;
1765 bias-disable;
1766 };
1767 };
1768
1769 sdc1_state_on: sdc1-on-state {
1770 clk-pins {
1771 pins = "sdc1_clk";
1772 bias-disable;
1773 drive-strength = <16>;
1774 };
1775
1776 cmd-pins {
1777 pins = "sdc1_cmd";
1778 bias-pull-up;
1779 drive-strength = <10>;
1780 };
1781
1782 data-pins {
1783 pins = "sdc1_data";
1784 bias-pull-up;
1785 drive-strength = <10>;
1786 };
1787
1788 rclk-pins {
1789 pins = "sdc1_rclk";
1790 bias-pull-down;
1791 };
1792 };
1793
1794 sdc1_state_off: sdc1-off-state {
1795 clk-pins {
1796 pins = "sdc1_clk";
1797 bias-disable;
1798 drive-strength = <2>;
1799 };
1800
1801 cmd-pins {
1802 pins = "sdc1_cmd";
1803 bias-pull-up;
1804 drive-strength = <2>;
1805 };
1806
1807 data-pins {
1808 pins = "sdc1_data";
1809 bias-pull-up;
1810 drive-strength = <2>;
1811 };
1812
1813 rclk-pins {
1814 pins = "sdc1_rclk";
1815 bias-pull-down;
1816 };
1817 };
1818
1819 sdc2_state_on: sdc2-on-state {
1820 clk-pins {
1821 pins = "sdc2_clk";
1822 bias-disable;
1823 drive-strength = <16>;
1824 };
1825
1826 cmd-pins {
1827 pins = "sdc2_cmd";
1828 bias-pull-up;
1829 drive-strength = <10>;
1830 };
1831
1832 data-pins {
1833 pins = "sdc2_data";
1834 bias-pull-up;
1835 drive-strength = <10>;
1836 };
1837 };
1838
1839 sdc2_state_off: sdc2-off-state {
1840 clk-pins {
1841 pins = "sdc2_clk";
1842 bias-disable;
1843 drive-strength = <2>;
1844 };
1845
1846 cmd-pins {
1847 pins = "sdc2_cmd";
1848 bias-pull-up;
1849 drive-strength = <2>;
1850 };
1851
1852 data-pins {
1853 pins = "sdc2_data";
1854 bias-pull-up;
1855 drive-strength = <2>;
1856 };
1857 };
1858 };
1859
1860 sram@290000 {
1861 compatible = "qcom,rpm-stats";
1862 reg = <0x00290000 0x10000>;
1863 };
1864
1865 spmi_bus: spmi@400f000 {
1866 compatible = "qcom,spmi-pmic-arb";
1867 reg = <0x0400f000 0x1000>,
1868 <0x04400000 0x800000>,
1869 <0x04c00000 0x800000>,
1870 <0x05800000 0x200000>,
1871 <0x0400a000 0x002100>;
1872 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1873 interrupt-names = "periph_irq";
1874 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1875 qcom,ee = <0>;
1876 qcom,channel = <0>;
1877 #address-cells = <2>;
1878 #size-cells = <0>;
1879 interrupt-controller;
1880 #interrupt-cells = <4>;
1881 };
1882
1883 bus@0 {
1884 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1885 compatible = "simple-pm-bus";
1886 #address-cells = <1>;
1887 #size-cells = <1>;
1888 ranges = <0x0 0x0 0xffffffff>;
1889
1890 pcie0: pcie@600000 {
1891 compatible = "qcom,pcie-msm8996";
1892 status = "disabled";
1893 power-domains = <&gcc PCIE0_GDSC>;
1894 bus-range = <0x00 0xff>;
1895 num-lanes = <1>;
1896
1897 reg = <0x00600000 0x2000>,
1898 <0x0c000000 0xf1d>,
1899 <0x0c000f20 0xa8>,
1900 <0x0c100000 0x100000>;
1901 reg-names = "parf", "dbi", "elbi","config";
1902
1903 phys = <&pciephy_0>;
1904 phy-names = "pciephy";
1905
1906 #address-cells = <3>;
1907 #size-cells = <2>;
1908 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1909 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1910
1911 device_type = "pci";
1912
1913 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1914 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1915 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1916 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1917 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1918 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
1919 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
1920 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1921 interrupt-names = "msi0",
1922 "msi1",
1923 "msi2",
1924 "msi3",
1925 "msi4",
1926 "msi5",
1927 "msi6",
1928 "msi7";
1929 #interrupt-cells = <1>;
1930 interrupt-map-mask = <0 0 0 0x7>;
1931 interrupt-map = <0 0 0 1 &intc GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1932 <0 0 0 2 &intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1933 <0 0 0 3 &intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1934 <0 0 0 4 &intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1935
1936 pinctrl-names = "default", "sleep";
1937 pinctrl-0 = <&pcie0_state_on>;
1938 pinctrl-1 = <&pcie0_state_off>;
1939
1940 linux,pci-domain = <0>;
1941
1942 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1943 <&gcc GCC_PCIE_0_AUX_CLK>,
1944 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1945 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1946 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1947
1948 clock-names = "pipe",
1949 "aux",
1950 "cfg",
1951 "bus_master",
1952 "bus_slave";
1953
1954 pcie@0 {
1955 device_type = "pci";
1956 reg = <0x0 0x0 0x0 0x0 0x0>;
1957 bus-range = <0x01 0xff>;
1958
1959 #address-cells = <3>;
1960 #size-cells = <2>;
1961 ranges;
1962 };
1963 };
1964
1965 pcie1: pcie@608000 {
1966 compatible = "qcom,pcie-msm8996";
1967 power-domains = <&gcc PCIE1_GDSC>;
1968 bus-range = <0x00 0xff>;
1969 num-lanes = <1>;
1970
1971 status = "disabled";
1972
1973 reg = <0x00608000 0x2000>,
1974 <0x0d000000 0xf1d>,
1975 <0x0d000f20 0xa8>,
1976 <0x0d100000 0x100000>;
1977
1978 reg-names = "parf", "dbi", "elbi","config";
1979
1980 phys = <&pciephy_1>;
1981 phy-names = "pciephy";
1982
1983 #address-cells = <3>;
1984 #size-cells = <2>;
1985 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1986 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1987
1988 device_type = "pci";
1989
1990 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
1991 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
1992 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
1993 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1994 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1995 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1996 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1997 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1998 interrupt-names = "msi0",
1999 "msi1",
2000 "msi2",
2001 "msi3",
2002 "msi4",
2003 "msi5",
2004 "msi6",
2005 "msi7";
2006 #interrupt-cells = <1>;
2007 interrupt-map-mask = <0 0 0 0x7>;
2008 interrupt-map = <0 0 0 1 &intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2009 <0 0 0 2 &intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2010 <0 0 0 3 &intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2011 <0 0 0 4 &intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2012
2013 pinctrl-names = "default", "sleep";
2014 pinctrl-0 = <&pcie1_state_on>;
2015 pinctrl-1 = <&pcie1_state_off>;
2016
2017 linux,pci-domain = <1>;
2018
2019 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2020 <&gcc GCC_PCIE_1_AUX_CLK>,
2021 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2022 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2023 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
2024
2025 clock-names = "pipe",
2026 "aux",
2027 "cfg",
2028 "bus_master",
2029 "bus_slave";
2030
2031 pcie@0 {
2032 device_type = "pci";
2033 reg = <0x0 0x0 0x0 0x0 0x0>;
2034 bus-range = <0x01 0xff>;
2035
2036 #address-cells = <3>;
2037 #size-cells = <2>;
2038 ranges;
2039 };
2040 };
2041
2042 pcie2: pcie@610000 {
2043 compatible = "qcom,pcie-msm8996";
2044 power-domains = <&gcc PCIE2_GDSC>;
2045 bus-range = <0x00 0xff>;
2046 num-lanes = <1>;
2047 status = "disabled";
2048 reg = <0x00610000 0x2000>,
2049 <0x0e000000 0xf1d>,
2050 <0x0e000f20 0xa8>,
2051 <0x0e100000 0x100000>;
2052
2053 reg-names = "parf", "dbi", "elbi","config";
2054
2055 phys = <&pciephy_2>;
2056 phy-names = "pciephy";
2057
2058 #address-cells = <3>;
2059 #size-cells = <2>;
2060 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
2061 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2062
2063 device_type = "pci";
2064
2065 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2066 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2067 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2068 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2069 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2070 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
2071 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
2072 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
2073 interrupt-names = "msi0",
2074 "msi1",
2075 "msi2",
2076 "msi3",
2077 "msi4",
2078 "msi5",
2079 "msi6",
2080 "msi7";
2081 #interrupt-cells = <1>;
2082 interrupt-map-mask = <0 0 0 0x7>;
2083 interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2084 <0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2085 <0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2086 <0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2087
2088 pinctrl-names = "default", "sleep";
2089 pinctrl-0 = <&pcie2_state_on>;
2090 pinctrl-1 = <&pcie2_state_off>;
2091
2092 linux,pci-domain = <2>;
2093 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2094 <&gcc GCC_PCIE_2_AUX_CLK>,
2095 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2096 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2097 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2098
2099 clock-names = "pipe",
2100 "aux",
2101 "cfg",
2102 "bus_master",
2103 "bus_slave";
2104
2105 pcie@0 {
2106 device_type = "pci";
2107 reg = <0x0 0x0 0x0 0x0 0x0>;
2108 bus-range = <0x01 0xff>;
2109
2110 #address-cells = <3>;
2111 #size-cells = <2>;
2112 ranges;
2113 };
2114 };
2115 };
2116
2117 ufshc: ufshc@624000 {
2118 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2119 "jedec,ufs-2.0";
2120 reg = <0x00624000 0x2500>;
2121 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2122
2123 phys = <&ufsphy>;
2124 phy-names = "ufsphy";
2125
2126 power-domains = <&gcc UFS_GDSC>;
2127
2128 clock-names =
2129 "core_clk",
2130 "bus_clk",
2131 "bus_aggr_clk",
2132 "iface_clk",
2133 "core_clk_unipro",
2134 "core_clk_ice",
2135 "ref_clk",
2136 "tx_lane0_sync_clk",
2137 "rx_lane0_sync_clk";
2138 clocks =
2139 <&gcc GCC_UFS_AXI_CLK>,
2140 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2141 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2142 <&gcc GCC_UFS_AHB_CLK>,
2143 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2144 <&gcc GCC_UFS_ICE_CORE_CLK>,
2145 <&rpmcc RPM_SMD_LN_BB_CLK>,
2146 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2147 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2148 freq-table-hz =
2149 <100000000 200000000>,
2150 <0 0>,
2151 <0 0>,
2152 <0 0>,
2153 <75000000 150000000>,
2154 <150000000 300000000>,
2155 <0 0>,
2156 <0 0>,
2157 <0 0>;
2158
2159 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>,
2160 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>;
2161 interconnect-names = "ufs-ddr", "cpu-ufs";
2162
2163 lanes-per-direction = <1>;
2164 #reset-cells = <1>;
2165 status = "disabled";
2166 };
2167
2168 ufsphy: phy@627000 {
2169 compatible = "qcom,msm8996-qmp-ufs-phy";
2170 reg = <0x00627000 0x1000>;
2171
2172 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>;
2173 clock-names = "ref", "qref";
2174
2175 resets = <&ufshc 0>;
2176 reset-names = "ufsphy";
2177
2178 #clock-cells = <1>;
2179 #phy-cells = <0>;
2180
2181 status = "disabled";
2182 };
2183
2184 camss: camss@a34000 {
2185 compatible = "qcom,msm8996-camss";
2186 reg = <0x00a34000 0x1000>,
2187 <0x00a00030 0x4>,
2188 <0x00a35000 0x1000>,
2189 <0x00a00038 0x4>,
2190 <0x00a36000 0x1000>,
2191 <0x00a00040 0x4>,
2192 <0x00a30000 0x100>,
2193 <0x00a30400 0x100>,
2194 <0x00a30800 0x100>,
2195 <0x00a30c00 0x100>,
2196 <0x00a31000 0x500>,
2197 <0x00a00020 0x10>,
2198 <0x00a10000 0x1000>,
2199 <0x00a14000 0x1000>;
2200 reg-names = "csiphy0",
2201 "csiphy0_clk_mux",
2202 "csiphy1",
2203 "csiphy1_clk_mux",
2204 "csiphy2",
2205 "csiphy2_clk_mux",
2206 "csid0",
2207 "csid1",
2208 "csid2",
2209 "csid3",
2210 "ispif",
2211 "csi_clk_mux",
2212 "vfe0",
2213 "vfe1";
2214 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2215 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2216 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2217 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2218 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2219 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2220 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2221 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2222 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2223 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2224 interrupt-names = "csiphy0",
2225 "csiphy1",
2226 "csiphy2",
2227 "csid0",
2228 "csid1",
2229 "csid2",
2230 "csid3",
2231 "ispif",
2232 "vfe0",
2233 "vfe1";
2234 power-domains = <&mmcc VFE0_GDSC>,
2235 <&mmcc VFE1_GDSC>;
2236 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2237 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2238 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2239 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2240 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2241 <&mmcc CAMSS_CSI0_AHB_CLK>,
2242 <&mmcc CAMSS_CSI0_CLK>,
2243 <&mmcc CAMSS_CSI0PHY_CLK>,
2244 <&mmcc CAMSS_CSI0PIX_CLK>,
2245 <&mmcc CAMSS_CSI0RDI_CLK>,
2246 <&mmcc CAMSS_CSI1_AHB_CLK>,
2247 <&mmcc CAMSS_CSI1_CLK>,
2248 <&mmcc CAMSS_CSI1PHY_CLK>,
2249 <&mmcc CAMSS_CSI1PIX_CLK>,
2250 <&mmcc CAMSS_CSI1RDI_CLK>,
2251 <&mmcc CAMSS_CSI2_AHB_CLK>,
2252 <&mmcc CAMSS_CSI2_CLK>,
2253 <&mmcc CAMSS_CSI2PHY_CLK>,
2254 <&mmcc CAMSS_CSI2PIX_CLK>,
2255 <&mmcc CAMSS_CSI2RDI_CLK>,
2256 <&mmcc CAMSS_CSI3_AHB_CLK>,
2257 <&mmcc CAMSS_CSI3_CLK>,
2258 <&mmcc CAMSS_CSI3PHY_CLK>,
2259 <&mmcc CAMSS_CSI3PIX_CLK>,
2260 <&mmcc CAMSS_CSI3RDI_CLK>,
2261 <&mmcc CAMSS_AHB_CLK>,
2262 <&mmcc CAMSS_VFE0_CLK>,
2263 <&mmcc CAMSS_CSI_VFE0_CLK>,
2264 <&mmcc CAMSS_VFE0_AHB_CLK>,
2265 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2266 <&mmcc CAMSS_VFE1_CLK>,
2267 <&mmcc CAMSS_CSI_VFE1_CLK>,
2268 <&mmcc CAMSS_VFE1_AHB_CLK>,
2269 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2270 <&mmcc CAMSS_VFE_AHB_CLK>,
2271 <&mmcc CAMSS_VFE_AXI_CLK>;
2272 clock-names = "top_ahb",
2273 "ispif_ahb",
2274 "csiphy0_timer",
2275 "csiphy1_timer",
2276 "csiphy2_timer",
2277 "csi0_ahb",
2278 "csi0",
2279 "csi0_phy",
2280 "csi0_pix",
2281 "csi0_rdi",
2282 "csi1_ahb",
2283 "csi1",
2284 "csi1_phy",
2285 "csi1_pix",
2286 "csi1_rdi",
2287 "csi2_ahb",
2288 "csi2",
2289 "csi2_phy",
2290 "csi2_pix",
2291 "csi2_rdi",
2292 "csi3_ahb",
2293 "csi3",
2294 "csi3_phy",
2295 "csi3_pix",
2296 "csi3_rdi",
2297 "ahb",
2298 "vfe0",
2299 "csi_vfe0",
2300 "vfe0_ahb",
2301 "vfe0_stream",
2302 "vfe1",
2303 "csi_vfe1",
2304 "vfe1_ahb",
2305 "vfe1_stream",
2306 "vfe_ahb",
2307 "vfe_axi";
2308 iommus = <&vfe_smmu 0>,
2309 <&vfe_smmu 1>,
2310 <&vfe_smmu 2>,
2311 <&vfe_smmu 3>;
2312 status = "disabled";
2313 ports {
2314 #address-cells = <1>;
2315 #size-cells = <0>;
2316 };
2317 };
2318
2319 cci: cci@a0c000 {
2320 compatible = "qcom,msm8996-cci";
2321 #address-cells = <1>;
2322 #size-cells = <0>;
2323 reg = <0xa0c000 0x1000>;
2324 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2325 power-domains = <&mmcc CAMSS_GDSC>;
2326 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2327 <&mmcc CAMSS_CCI_AHB_CLK>,
2328 <&mmcc CAMSS_CCI_CLK>,
2329 <&mmcc CAMSS_AHB_CLK>;
2330 clock-names = "camss_top_ahb",
2331 "cci_ahb",
2332 "cci",
2333 "camss_ahb";
2334 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2335 <&mmcc CAMSS_CCI_CLK>;
2336 assigned-clock-rates = <80000000>, <37500000>;
2337 pinctrl-names = "default";
2338 pinctrl-0 = <&cci0_default &cci1_default>;
2339 status = "disabled";
2340
2341 cci_i2c0: i2c-bus@0 {
2342 reg = <0>;
2343 clock-frequency = <400000>;
2344 #address-cells = <1>;
2345 #size-cells = <0>;
2346 };
2347
2348 cci_i2c1: i2c-bus@1 {
2349 reg = <1>;
2350 clock-frequency = <400000>;
2351 #address-cells = <1>;
2352 #size-cells = <0>;
2353 };
2354 };
2355
2356 adreno_smmu: iommu@b40000 {
2357 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2358 reg = <0x00b40000 0x10000>;
2359
2360 #global-interrupts = <1>;
2361 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2362 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2363 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2364 #iommu-cells = <1>;
2365
2366 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
2367 <&mmcc GPU_AHB_CLK>;
2368 clock-names = "bus", "iface";
2369
2370 power-domains = <&mmcc GPU_GDSC>;
2371 };
2372
2373 venus: video-codec@c00000 {
2374 compatible = "qcom,msm8996-venus";
2375 reg = <0x00c00000 0xff000>;
2376 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2377 power-domains = <&mmcc VENUS_GDSC>;
2378 clocks = <&mmcc VIDEO_CORE_CLK>,
2379 <&mmcc VIDEO_AHB_CLK>,
2380 <&mmcc VIDEO_AXI_CLK>,
2381 <&mmcc VIDEO_MAXI_CLK>;
2382 clock-names = "core", "iface", "bus", "mbus";
2383 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
2384 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
2385 interconnect-names = "video-mem", "cpu-cfg";
2386 iommus = <&venus_smmu 0x00>,
2387 <&venus_smmu 0x01>,
2388 <&venus_smmu 0x0a>,
2389 <&venus_smmu 0x07>,
2390 <&venus_smmu 0x0e>,
2391 <&venus_smmu 0x0f>,
2392 <&venus_smmu 0x08>,
2393 <&venus_smmu 0x09>,
2394 <&venus_smmu 0x0b>,
2395 <&venus_smmu 0x0c>,
2396 <&venus_smmu 0x0d>,
2397 <&venus_smmu 0x10>,
2398 <&venus_smmu 0x11>,
2399 <&venus_smmu 0x21>,
2400 <&venus_smmu 0x28>,
2401 <&venus_smmu 0x29>,
2402 <&venus_smmu 0x2b>,
2403 <&venus_smmu 0x2c>,
2404 <&venus_smmu 0x2d>,
2405 <&venus_smmu 0x31>;
2406 memory-region = <&venus_mem>;
2407 status = "disabled";
2408
2409 video-decoder {
2410 compatible = "venus-decoder";
2411 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2412 clock-names = "core";
2413 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2414 };
2415
2416 video-encoder {
2417 compatible = "venus-encoder";
2418 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2419 clock-names = "core";
2420 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2421 };
2422 };
2423
2424 mdp_smmu: iommu@d00000 {
2425 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2426 reg = <0x00d00000 0x10000>;
2427
2428 #global-interrupts = <1>;
2429 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2430 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2431 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2432 #iommu-cells = <1>;
2433 clocks = <&mmcc SMMU_MDP_AXI_CLK>,
2434 <&mmcc SMMU_MDP_AHB_CLK>;
2435 clock-names = "bus", "iface";
2436
2437 power-domains = <&mmcc MDSS_GDSC>;
2438 };
2439
2440 venus_smmu: iommu@d40000 {
2441 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2442 reg = <0x00d40000 0x20000>;
2443 #global-interrupts = <1>;
2444 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2448 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2449 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2450 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2451 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2452 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2453 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
2454 <&mmcc SMMU_VIDEO_AHB_CLK>;
2455 clock-names = "bus", "iface";
2456 #iommu-cells = <1>;
2457 status = "okay";
2458 };
2459
2460 vfe_smmu: iommu@da0000 {
2461 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2462 reg = <0x00da0000 0x10000>;
2463
2464 #global-interrupts = <1>;
2465 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2466 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2467 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2468 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2469 clocks = <&mmcc SMMU_VFE_AXI_CLK>,
2470 <&mmcc SMMU_VFE_AHB_CLK>;
2471 clock-names = "bus", "iface";
2472 #iommu-cells = <1>;
2473 };
2474
2475 lpass_q6_smmu: iommu@1600000 {
2476 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2477 reg = <0x01600000 0x20000>;
2478 #iommu-cells = <1>;
2479 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2480
2481 #global-interrupts = <1>;
2482 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2483 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2484 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2485 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2486 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2487 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2488 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2489 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2490 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2491 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2492 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2493 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2494 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2495
2496 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
2497 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
2498 clock-names = "bus", "iface";
2499 };
2500
2501 slpi_pil: remoteproc@1c00000 {
2502 compatible = "qcom,msm8996-slpi-pil";
2503 reg = <0x01c00000 0x4000>;
2504
2505 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2506 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2507 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2508 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2509 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2510 interrupt-names = "wdog",
2511 "fatal",
2512 "ready",
2513 "handover",
2514 "stop-ack";
2515
2516 clocks = <&xo_board>;
2517 clock-names = "xo";
2518
2519 memory-region = <&slpi_mem>;
2520
2521 qcom,smem-states = <&slpi_smp2p_out 0>;
2522 qcom,smem-state-names = "stop";
2523
2524 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2525 power-domain-names = "ssc_cx";
2526
2527 status = "disabled";
2528
2529 glink-edge {
2530 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
2531 label = "dsps";
2532 qcom,remote-pid = <3>;
2533 mboxes = <&apcs_glb 27>;
2534 };
2535
2536 smd-edge {
2537 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
2538
2539 label = "dsps";
2540 mboxes = <&apcs_glb 25>;
2541 qcom,smd-edge = <3>;
2542 qcom,remote-pid = <3>;
2543 };
2544 };
2545
2546 mss_pil: remoteproc@2080000 {
2547 compatible = "qcom,msm8996-mss-pil";
2548 reg = <0x2080000 0x100>,
2549 <0x2180000 0x020>;
2550 reg-names = "qdsp6", "rmb";
2551
2552 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2553 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2554 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2555 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2556 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2557 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2558 interrupt-names = "wdog", "fatal", "ready",
2559 "handover", "stop-ack",
2560 "shutdown-ack";
2561
2562 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2563 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2564 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2565 <&xo_board>,
2566 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2567 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2568 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
2569 <&rpmcc RPM_SMD_QDSS_CLK>;
2570 clock-names = "iface",
2571 "bus",
2572 "mem",
2573 "xo",
2574 "gpll0_mss",
2575 "snoc_axi",
2576 "mnoc_axi",
2577 "qdss";
2578
2579 resets = <&gcc GCC_MSS_RESTART>;
2580 reset-names = "mss_restart";
2581
2582 power-domains = <&rpmpd MSM8996_VDDCX>,
2583 <&rpmpd MSM8996_VDDMX>;
2584 power-domain-names = "cx", "mx";
2585
2586 qcom,smem-states = <&mpss_smp2p_out 0>;
2587 qcom,smem-state-names = "stop";
2588
2589 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2590
2591 status = "disabled";
2592
2593 mba {
2594 memory-region = <&mba_mem>;
2595 };
2596
2597 mpss {
2598 memory-region = <&mpss_mem>;
2599 };
2600
2601 metadata {
2602 memory-region = <&mdata_mem>;
2603 };
2604
2605 glink-edge {
2606 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
2607 label = "modem";
2608 qcom,remote-pid = <1>;
2609 mboxes = <&apcs_glb 15>;
2610 };
2611
2612 smd-edge {
2613 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2614
2615 label = "mpss";
2616 mboxes = <&apcs_glb 12>;
2617 qcom,smd-edge = <0>;
2618 qcom,remote-pid = <1>;
2619 };
2620 };
2621
2622 stm@3002000 {
2623 compatible = "arm,coresight-stm", "arm,primecell";
2624 reg = <0x3002000 0x1000>,
2625 <0x8280000 0x180000>;
2626 reg-names = "stm-base", "stm-stimulus-base";
2627
2628 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2629 clock-names = "apb_pclk", "atclk";
2630
2631 out-ports {
2632 port {
2633 stm_out: endpoint {
2634 remote-endpoint =
2635 <&funnel0_in>;
2636 };
2637 };
2638 };
2639 };
2640
2641 tpiu@3020000 {
2642 compatible = "arm,coresight-tpiu", "arm,primecell";
2643 reg = <0x3020000 0x1000>;
2644
2645 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2646 clock-names = "apb_pclk", "atclk";
2647
2648 in-ports {
2649 port {
2650 tpiu_in: endpoint {
2651 remote-endpoint =
2652 <&replicator_out1>;
2653 };
2654 };
2655 };
2656 };
2657
2658 funnel@3021000 {
2659 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2660 reg = <0x3021000 0x1000>;
2661
2662 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2663 clock-names = "apb_pclk", "atclk";
2664
2665 in-ports {
2666 #address-cells = <1>;
2667 #size-cells = <0>;
2668
2669 port@7 {
2670 reg = <7>;
2671 funnel0_in: endpoint {
2672 remote-endpoint =
2673 <&stm_out>;
2674 };
2675 };
2676 };
2677
2678 out-ports {
2679 port {
2680 funnel0_out: endpoint {
2681 remote-endpoint =
2682 <&merge_funnel_in0>;
2683 };
2684 };
2685 };
2686 };
2687
2688 funnel@3022000 {
2689 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2690 reg = <0x3022000 0x1000>;
2691
2692 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2693 clock-names = "apb_pclk", "atclk";
2694
2695 in-ports {
2696 #address-cells = <1>;
2697 #size-cells = <0>;
2698
2699 port@6 {
2700 reg = <6>;
2701 funnel1_in: endpoint {
2702 remote-endpoint =
2703 <&apss_merge_funnel_out>;
2704 };
2705 };
2706 };
2707
2708 out-ports {
2709 port {
2710 funnel1_out: endpoint {
2711 remote-endpoint =
2712 <&merge_funnel_in1>;
2713 };
2714 };
2715 };
2716 };
2717
2718 funnel@3023000 {
2719 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2720 reg = <0x3023000 0x1000>;
2721
2722 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2723 clock-names = "apb_pclk", "atclk";
2724
2725 in-ports {
2726 port {
2727 funnel_in2_in_modem_etm: endpoint {
2728 remote-endpoint =
2729 <&modem_etm_out_funnel_in2>;
2730 };
2731 };
2732 };
2733
2734 out-ports {
2735 port {
2736 funnel2_out: endpoint {
2737 remote-endpoint =
2738 <&merge_funnel_in2>;
2739 };
2740 };
2741 };
2742 };
2743
2744 funnel@3025000 {
2745 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2746 reg = <0x3025000 0x1000>;
2747
2748 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2749 clock-names = "apb_pclk", "atclk";
2750
2751 in-ports {
2752 #address-cells = <1>;
2753 #size-cells = <0>;
2754
2755 port@0 {
2756 reg = <0>;
2757 merge_funnel_in0: endpoint {
2758 remote-endpoint =
2759 <&funnel0_out>;
2760 };
2761 };
2762
2763 port@1 {
2764 reg = <1>;
2765 merge_funnel_in1: endpoint {
2766 remote-endpoint =
2767 <&funnel1_out>;
2768 };
2769 };
2770
2771 port@2 {
2772 reg = <2>;
2773 merge_funnel_in2: endpoint {
2774 remote-endpoint =
2775 <&funnel2_out>;
2776 };
2777 };
2778 };
2779
2780 out-ports {
2781 port {
2782 merge_funnel_out: endpoint {
2783 remote-endpoint =
2784 <&etf_in>;
2785 };
2786 };
2787 };
2788 };
2789
2790 replicator@3026000 {
2791 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2792 reg = <0x3026000 0x1000>;
2793
2794 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2795 clock-names = "apb_pclk", "atclk";
2796
2797 in-ports {
2798 port {
2799 replicator_in: endpoint {
2800 remote-endpoint =
2801 <&etf_out>;
2802 };
2803 };
2804 };
2805
2806 out-ports {
2807 #address-cells = <1>;
2808 #size-cells = <0>;
2809
2810 port@0 {
2811 reg = <0>;
2812 replicator_out0: endpoint {
2813 remote-endpoint =
2814 <&etr_in>;
2815 };
2816 };
2817
2818 port@1 {
2819 reg = <1>;
2820 replicator_out1: endpoint {
2821 remote-endpoint =
2822 <&tpiu_in>;
2823 };
2824 };
2825 };
2826 };
2827
2828 etf@3027000 {
2829 compatible = "arm,coresight-tmc", "arm,primecell";
2830 reg = <0x3027000 0x1000>;
2831
2832 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2833 clock-names = "apb_pclk", "atclk";
2834
2835 in-ports {
2836 port {
2837 etf_in: endpoint {
2838 remote-endpoint =
2839 <&merge_funnel_out>;
2840 };
2841 };
2842 };
2843
2844 out-ports {
2845 port {
2846 etf_out: endpoint {
2847 remote-endpoint =
2848 <&replicator_in>;
2849 };
2850 };
2851 };
2852 };
2853
2854 etr@3028000 {
2855 compatible = "arm,coresight-tmc", "arm,primecell";
2856 reg = <0x3028000 0x1000>;
2857
2858 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2859 clock-names = "apb_pclk", "atclk";
2860 arm,scatter-gather;
2861
2862 in-ports {
2863 port {
2864 etr_in: endpoint {
2865 remote-endpoint =
2866 <&replicator_out0>;
2867 };
2868 };
2869 };
2870 };
2871
2872 debug@3810000 {
2873 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2874 reg = <0x3810000 0x1000>;
2875
2876 clocks = <&rpmcc RPM_QDSS_CLK>;
2877 clock-names = "apb_pclk";
2878
2879 cpu = <&cpu0>;
2880 };
2881
2882 etm@3840000 {
2883 compatible = "arm,coresight-etm4x", "arm,primecell";
2884 reg = <0x3840000 0x1000>;
2885
2886 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2887 clock-names = "apb_pclk", "atclk";
2888
2889 cpu = <&cpu0>;
2890
2891 out-ports {
2892 port {
2893 etm0_out: endpoint {
2894 remote-endpoint =
2895 <&apss_funnel0_in0>;
2896 };
2897 };
2898 };
2899 };
2900
2901 debug@3910000 {
2902 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2903 reg = <0x3910000 0x1000>;
2904
2905 clocks = <&rpmcc RPM_QDSS_CLK>;
2906 clock-names = "apb_pclk";
2907
2908 cpu = <&cpu1>;
2909 };
2910
2911 etm@3940000 {
2912 compatible = "arm,coresight-etm4x", "arm,primecell";
2913 reg = <0x3940000 0x1000>;
2914
2915 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2916 clock-names = "apb_pclk", "atclk";
2917
2918 cpu = <&cpu1>;
2919
2920 out-ports {
2921 port {
2922 etm1_out: endpoint {
2923 remote-endpoint =
2924 <&apss_funnel0_in1>;
2925 };
2926 };
2927 };
2928 };
2929
2930 funnel@39b0000 { /* APSS Funnel 0 */
2931 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2932 reg = <0x39b0000 0x1000>;
2933
2934 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2935 clock-names = "apb_pclk", "atclk";
2936
2937 in-ports {
2938 #address-cells = <1>;
2939 #size-cells = <0>;
2940
2941 port@0 {
2942 reg = <0>;
2943 apss_funnel0_in0: endpoint {
2944 remote-endpoint = <&etm0_out>;
2945 };
2946 };
2947
2948 port@1 {
2949 reg = <1>;
2950 apss_funnel0_in1: endpoint {
2951 remote-endpoint = <&etm1_out>;
2952 };
2953 };
2954 };
2955
2956 out-ports {
2957 port {
2958 apss_funnel0_out: endpoint {
2959 remote-endpoint =
2960 <&apss_merge_funnel_in0>;
2961 };
2962 };
2963 };
2964 };
2965
2966 debug@3a10000 {
2967 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2968 reg = <0x3a10000 0x1000>;
2969
2970 clocks = <&rpmcc RPM_QDSS_CLK>;
2971 clock-names = "apb_pclk";
2972
2973 cpu = <&cpu2>;
2974 };
2975
2976 etm@3a40000 {
2977 compatible = "arm,coresight-etm4x", "arm,primecell";
2978 reg = <0x3a40000 0x1000>;
2979
2980 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2981 clock-names = "apb_pclk", "atclk";
2982
2983 cpu = <&cpu2>;
2984
2985 out-ports {
2986 port {
2987 etm2_out: endpoint {
2988 remote-endpoint =
2989 <&apss_funnel1_in0>;
2990 };
2991 };
2992 };
2993 };
2994
2995 debug@3b10000 {
2996 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2997 reg = <0x3b10000 0x1000>;
2998
2999 clocks = <&rpmcc RPM_QDSS_CLK>;
3000 clock-names = "apb_pclk";
3001
3002 cpu = <&cpu3>;
3003 };
3004
3005 etm@3b40000 {
3006 compatible = "arm,coresight-etm4x", "arm,primecell";
3007 reg = <0x3b40000 0x1000>;
3008
3009 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3010 clock-names = "apb_pclk", "atclk";
3011
3012 cpu = <&cpu3>;
3013
3014 out-ports {
3015 port {
3016 etm3_out: endpoint {
3017 remote-endpoint =
3018 <&apss_funnel1_in1>;
3019 };
3020 };
3021 };
3022 };
3023
3024 funnel@3bb0000 { /* APSS Funnel 1 */
3025 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3026 reg = <0x3bb0000 0x1000>;
3027
3028 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3029 clock-names = "apb_pclk", "atclk";
3030
3031 in-ports {
3032 #address-cells = <1>;
3033 #size-cells = <0>;
3034
3035 port@0 {
3036 reg = <0>;
3037 apss_funnel1_in0: endpoint {
3038 remote-endpoint = <&etm2_out>;
3039 };
3040 };
3041
3042 port@1 {
3043 reg = <1>;
3044 apss_funnel1_in1: endpoint {
3045 remote-endpoint = <&etm3_out>;
3046 };
3047 };
3048 };
3049
3050 out-ports {
3051 port {
3052 apss_funnel1_out: endpoint {
3053 remote-endpoint =
3054 <&apss_merge_funnel_in1>;
3055 };
3056 };
3057 };
3058 };
3059
3060 funnel@3bc0000 {
3061 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3062 reg = <0x3bc0000 0x1000>;
3063
3064 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3065 clock-names = "apb_pclk", "atclk";
3066
3067 in-ports {
3068 #address-cells = <1>;
3069 #size-cells = <0>;
3070
3071 port@0 {
3072 reg = <0>;
3073 apss_merge_funnel_in0: endpoint {
3074 remote-endpoint =
3075 <&apss_funnel0_out>;
3076 };
3077 };
3078
3079 port@1 {
3080 reg = <1>;
3081 apss_merge_funnel_in1: endpoint {
3082 remote-endpoint =
3083 <&apss_funnel1_out>;
3084 };
3085 };
3086 };
3087
3088 out-ports {
3089 port {
3090 apss_merge_funnel_out: endpoint {
3091 remote-endpoint =
3092 <&funnel1_in>;
3093 };
3094 };
3095 };
3096 };
3097
3098 kryocc: clock-controller@6400000 {
3099 compatible = "qcom,msm8996-apcc";
3100 reg = <0x06400000 0x90000>;
3101
3102 clock-names = "xo", "sys_apcs_aux";
3103 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3104
3105 #clock-cells = <1>;
3106 };
3107
3108 usb3: usb@6af8800 {
3109 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3110 reg = <0x06af8800 0x400>;
3111 #address-cells = <1>;
3112 #size-cells = <1>;
3113 ranges;
3114
3115 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
3116 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
3117 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
3118 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
3119 interrupt-names = "pwr_event",
3120 "qusb2_phy",
3121 "hs_phy_irq",
3122 "ss_phy_irq";
3123
3124 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3125 <&gcc GCC_USB30_MASTER_CLK>,
3126 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3127 <&gcc GCC_USB30_SLEEP_CLK>,
3128 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
3129 clock-names = "cfg_noc",
3130 "core",
3131 "iface",
3132 "sleep",
3133 "mock_utmi";
3134
3135 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3136 <&gcc GCC_USB30_MASTER_CLK>;
3137 assigned-clock-rates = <19200000>, <120000000>;
3138
3139 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
3140 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
3141 interconnect-names = "usb-ddr", "apps-usb";
3142
3143 power-domains = <&gcc USB30_GDSC>;
3144 status = "disabled";
3145
3146 usb3_dwc3: usb@6a00000 {
3147 compatible = "snps,dwc3";
3148 reg = <0x06a00000 0xcc00>;
3149 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
3150 phys = <&hsusb_phy1>, <&usb3phy>;
3151 phy-names = "usb2-phy", "usb3-phy";
3152 snps,hird-threshold = /bits/ 8 <0>;
3153 snps,dis_u2_susphy_quirk;
3154 snps,dis_enblslpm_quirk;
3155 snps,is-utmi-l1-suspend;
3156 snps,parkmode-disable-ss-quirk;
3157 tx-fifo-resize;
3158 };
3159 };
3160
3161 usb3phy: phy@7410000 {
3162 compatible = "qcom,msm8996-qmp-usb3-phy";
3163 reg = <0x07410000 0x1000>;
3164
3165 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3166 <&gcc GCC_USB3_CLKREF_CLK>,
3167 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3168 <&gcc GCC_USB3_PHY_PIPE_CLK>;
3169 clock-names = "aux",
3170 "ref",
3171 "cfg_ahb",
3172 "pipe";
3173 clock-output-names = "usb3_phy_pipe_clk_src";
3174 #clock-cells = <0>;
3175 #phy-cells = <0>;
3176
3177 resets = <&gcc GCC_USB3_PHY_BCR>,
3178 <&gcc GCC_USB3PHY_PHY_BCR>;
3179 reset-names = "phy",
3180 "phy_phy";
3181
3182 status = "disabled";
3183 };
3184
3185 hsusb_phy1: phy@7411000 {
3186 compatible = "qcom,msm8996-qusb2-phy";
3187 reg = <0x07411000 0x180>;
3188 #phy-cells = <0>;
3189
3190 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3191 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3192 clock-names = "cfg_ahb", "ref";
3193
3194 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3195 nvmem-cells = <&qusb2p_hstx_trim>;
3196 status = "disabled";
3197 };
3198
3199 hsusb_phy2: phy@7412000 {
3200 compatible = "qcom,msm8996-qusb2-phy";
3201 reg = <0x07412000 0x180>;
3202 #phy-cells = <0>;
3203
3204 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3205 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3206 clock-names = "cfg_ahb", "ref";
3207
3208 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3209 nvmem-cells = <&qusb2s_hstx_trim>;
3210 status = "disabled";
3211 };
3212
3213 sdhc1: mmc@7464900 {
3214 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3215 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3216 reg-names = "hc", "core";
3217
3218 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3219 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3220 interrupt-names = "hc_irq", "pwr_irq";
3221
3222 clock-names = "iface", "core", "xo";
3223 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3224 <&gcc GCC_SDCC1_APPS_CLK>,
3225 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3226 resets = <&gcc GCC_SDCC1_BCR>;
3227
3228 pinctrl-names = "default", "sleep";
3229 pinctrl-0 = <&sdc1_state_on>;
3230 pinctrl-1 = <&sdc1_state_off>;
3231
3232 bus-width = <8>;
3233 non-removable;
3234 status = "disabled";
3235 };
3236
3237 sdhc2: mmc@74a4900 {
3238 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3239 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3240 reg-names = "hc", "core";
3241
3242 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3244 interrupt-names = "hc_irq", "pwr_irq";
3245
3246 clock-names = "iface", "core", "xo";
3247 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3248 <&gcc GCC_SDCC2_APPS_CLK>,
3249 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3250 resets = <&gcc GCC_SDCC2_BCR>;
3251
3252 pinctrl-names = "default", "sleep";
3253 pinctrl-0 = <&sdc2_state_on>;
3254 pinctrl-1 = <&sdc2_state_off>;
3255
3256 bus-width = <4>;
3257 status = "disabled";
3258 };
3259
3260 blsp1_dma: dma-controller@7544000 {
3261 compatible = "qcom,bam-v1.7.0";
3262 reg = <0x07544000 0x2b000>;
3263 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3264 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3265 clock-names = "bam_clk";
3266 qcom,controlled-remotely;
3267 #dma-cells = <1>;
3268 qcom,ee = <0>;
3269 };
3270
3271 blsp1_uart2: serial@7570000 {
3272 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3273 reg = <0x07570000 0x1000>;
3274 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3275 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3276 <&gcc GCC_BLSP1_AHB_CLK>;
3277 clock-names = "core", "iface";
3278 pinctrl-names = "default", "sleep";
3279 pinctrl-0 = <&blsp1_uart2_default>;
3280 pinctrl-1 = <&blsp1_uart2_sleep>;
3281 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3282 dma-names = "tx", "rx";
3283 status = "disabled";
3284 };
3285
3286 blsp1_spi1: spi@7575000 {
3287 compatible = "qcom,spi-qup-v2.2.1";
3288 reg = <0x07575000 0x600>;
3289 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3290 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3291 <&gcc GCC_BLSP1_AHB_CLK>;
3292 clock-names = "core", "iface";
3293 pinctrl-names = "default", "sleep";
3294 pinctrl-0 = <&blsp1_spi1_default>;
3295 pinctrl-1 = <&blsp1_spi1_sleep>;
3296 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3297 dma-names = "tx", "rx";
3298 #address-cells = <1>;
3299 #size-cells = <0>;
3300 status = "disabled";
3301 };
3302
3303 blsp1_i2c3: i2c@7577000 {
3304 compatible = "qcom,i2c-qup-v2.2.1";
3305 reg = <0x07577000 0x1000>;
3306 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3307 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3308 <&gcc GCC_BLSP1_AHB_CLK>;
3309 clock-names = "core", "iface";
3310 pinctrl-names = "default", "sleep";
3311 pinctrl-0 = <&blsp1_i2c3_default>;
3312 pinctrl-1 = <&blsp1_i2c3_sleep>;
3313 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3314 dma-names = "tx", "rx";
3315 #address-cells = <1>;
3316 #size-cells = <0>;
3317 status = "disabled";
3318 };
3319
3320 blsp1_i2c6: i2c@757a000 {
3321 compatible = "qcom,i2c-qup-v2.2.1";
3322 reg = <0x757a000 0x1000>;
3323 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
3324 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
3325 <&gcc GCC_BLSP1_AHB_CLK>;
3326 clock-names = "core", "iface";
3327 pinctrl-names = "default", "sleep";
3328 pinctrl-0 = <&blsp1_i2c6_default>;
3329 pinctrl-1 = <&blsp1_i2c6_sleep>;
3330 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
3331 dma-names = "tx", "rx";
3332 #address-cells = <1>;
3333 #size-cells = <0>;
3334 status = "disabled";
3335 };
3336
3337 blsp2_dma: dma-controller@7584000 {
3338 compatible = "qcom,bam-v1.7.0";
3339 reg = <0x07584000 0x2b000>;
3340 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3341 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3342 clock-names = "bam_clk";
3343 qcom,controlled-remotely;
3344 #dma-cells = <1>;
3345 qcom,ee = <0>;
3346 };
3347
3348 blsp2_uart2: serial@75b0000 {
3349 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3350 reg = <0x075b0000 0x1000>;
3351 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3352 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3353 <&gcc GCC_BLSP2_AHB_CLK>;
3354 clock-names = "core", "iface";
3355 status = "disabled";
3356 };
3357
3358 blsp2_uart3: serial@75b1000 {
3359 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3360 reg = <0x075b1000 0x1000>;
3361 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3362 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3363 <&gcc GCC_BLSP2_AHB_CLK>;
3364 clock-names = "core", "iface";
3365 status = "disabled";
3366 };
3367
3368 blsp2_i2c1: i2c@75b5000 {
3369 compatible = "qcom,i2c-qup-v2.2.1";
3370 reg = <0x075b5000 0x1000>;
3371 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3372 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3373 <&gcc GCC_BLSP2_AHB_CLK>;
3374 clock-names = "core", "iface";
3375 pinctrl-names = "default", "sleep";
3376 pinctrl-0 = <&blsp2_i2c1_default>;
3377 pinctrl-1 = <&blsp2_i2c1_sleep>;
3378 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3379 dma-names = "tx", "rx";
3380 #address-cells = <1>;
3381 #size-cells = <0>;
3382 status = "disabled";
3383 };
3384
3385 blsp2_i2c2: i2c@75b6000 {
3386 compatible = "qcom,i2c-qup-v2.2.1";
3387 reg = <0x075b6000 0x1000>;
3388 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3389 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3390 <&gcc GCC_BLSP2_AHB_CLK>;
3391 clock-names = "core", "iface";
3392 pinctrl-names = "default", "sleep";
3393 pinctrl-0 = <&blsp2_i2c2_default>;
3394 pinctrl-1 = <&blsp2_i2c2_sleep>;
3395 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3396 dma-names = "tx", "rx";
3397 #address-cells = <1>;
3398 #size-cells = <0>;
3399 status = "disabled";
3400 };
3401
3402 blsp2_i2c3: i2c@75b7000 {
3403 compatible = "qcom,i2c-qup-v2.2.1";
3404 reg = <0x075b7000 0x1000>;
3405 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3406 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3407 <&gcc GCC_BLSP2_AHB_CLK>;
3408 clock-names = "core", "iface";
3409 clock-frequency = <400000>;
3410 pinctrl-names = "default", "sleep";
3411 pinctrl-0 = <&blsp2_i2c3_default>;
3412 pinctrl-1 = <&blsp2_i2c3_sleep>;
3413 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
3414 dma-names = "tx", "rx";
3415 #address-cells = <1>;
3416 #size-cells = <0>;
3417 status = "disabled";
3418 };
3419
3420 blsp2_i2c5: i2c@75b9000 {
3421 compatible = "qcom,i2c-qup-v2.2.1";
3422 reg = <0x75b9000 0x1000>;
3423 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3424 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3425 <&gcc GCC_BLSP2_AHB_CLK>;
3426 clock-names = "core", "iface";
3427 pinctrl-names = "default";
3428 pinctrl-0 = <&blsp2_i2c5_default>;
3429 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3430 dma-names = "tx", "rx";
3431 #address-cells = <1>;
3432 #size-cells = <0>;
3433 status = "disabled";
3434 };
3435
3436 blsp2_i2c6: i2c@75ba000 {
3437 compatible = "qcom,i2c-qup-v2.2.1";
3438 reg = <0x75ba000 0x1000>;
3439 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3440 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3441 <&gcc GCC_BLSP2_AHB_CLK>;
3442 clock-names = "core", "iface";
3443 pinctrl-names = "default", "sleep";
3444 pinctrl-0 = <&blsp2_i2c6_default>;
3445 pinctrl-1 = <&blsp2_i2c6_sleep>;
3446 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3447 dma-names = "tx", "rx";
3448 #address-cells = <1>;
3449 #size-cells = <0>;
3450 status = "disabled";
3451 };
3452
3453 blsp2_spi6: spi@75ba000 {
3454 compatible = "qcom,spi-qup-v2.2.1";
3455 reg = <0x075ba000 0x600>;
3456 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3457 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3458 <&gcc GCC_BLSP2_AHB_CLK>;
3459 clock-names = "core", "iface";
3460 pinctrl-names = "default", "sleep";
3461 pinctrl-0 = <&blsp2_spi6_default>;
3462 pinctrl-1 = <&blsp2_spi6_sleep>;
3463 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3464 dma-names = "tx", "rx";
3465 #address-cells = <1>;
3466 #size-cells = <0>;
3467 status = "disabled";
3468 };
3469
3470 usb2: usb@76f8800 {
3471 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3472 reg = <0x076f8800 0x400>;
3473 #address-cells = <1>;
3474 #size-cells = <1>;
3475 ranges;
3476
3477 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
3478 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
3479 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
3480 interrupt-names = "pwr_event",
3481 "qusb2_phy",
3482 "hs_phy_irq";
3483
3484 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3485 <&gcc GCC_USB20_MASTER_CLK>,
3486 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3487 <&gcc GCC_USB20_SLEEP_CLK>,
3488 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3489 clock-names = "cfg_noc",
3490 "core",
3491 "iface",
3492 "sleep",
3493 "mock_utmi";
3494
3495 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3496 <&gcc GCC_USB20_MASTER_CLK>;
3497 assigned-clock-rates = <19200000>, <60000000>;
3498
3499 power-domains = <&gcc USB30_GDSC>;
3500 qcom,select-utmi-as-pipe-clk;
3501 status = "disabled";
3502
3503 usb2_dwc3: usb@7600000 {
3504 compatible = "snps,dwc3";
3505 reg = <0x07600000 0xcc00>;
3506 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3507 phys = <&hsusb_phy2>;
3508 phy-names = "usb2-phy";
3509 maximum-speed = "high-speed";
3510 snps,dis_u2_susphy_quirk;
3511 snps,dis_enblslpm_quirk;
3512 };
3513 };
3514
3515 slimbam: dma-controller@9184000 {
3516 compatible = "qcom,bam-v1.7.0";
3517 qcom,controlled-remotely;
3518 reg = <0x09184000 0x32000>;
3519 num-channels = <31>;
3520 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3521 #dma-cells = <1>;
3522 qcom,ee = <1>;
3523 qcom,num-ees = <2>;
3524 };
3525
3526 slim_msm: slim-ngd@91c0000 {
3527 compatible = "qcom,slim-ngd-v1.5.0";
3528 reg = <0x091c0000 0x2c000>;
3529 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3530 dmas = <&slimbam 3>, <&slimbam 4>;
3531 dma-names = "rx", "tx";
3532 #address-cells = <1>;
3533 #size-cells = <0>;
3534
3535 status = "disabled";
3536 };
3537
3538 adsp_pil: remoteproc@9300000 {
3539 compatible = "qcom,msm8996-adsp-pil";
3540 reg = <0x09300000 0x80000>;
3541
3542 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3543 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3544 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3545 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3546 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3547 interrupt-names = "wdog", "fatal", "ready",
3548 "handover", "stop-ack";
3549
3550 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3551 clock-names = "xo";
3552
3553 memory-region = <&adsp_mem>;
3554
3555 qcom,smem-states = <&adsp_smp2p_out 0>;
3556 qcom,smem-state-names = "stop";
3557
3558 power-domains = <&rpmpd MSM8996_VDDCX>;
3559 power-domain-names = "cx";
3560
3561 status = "disabled";
3562
3563 glink-edge {
3564 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3565 label = "lpass";
3566 qcom,remote-pid = <2>;
3567 mboxes = <&apcs_glb 9>;
3568 };
3569
3570
3571 smd-edge {
3572 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3573
3574 label = "lpass";
3575 mboxes = <&apcs_glb 8>;
3576 qcom,smd-edge = <1>;
3577 qcom,remote-pid = <2>;
3578
3579 apr {
3580 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3581 compatible = "qcom,apr-v2";
3582 qcom,smd-channels = "apr_audio_svc";
3583 qcom,domain = <APR_DOMAIN_ADSP>;
3584 #address-cells = <1>;
3585 #size-cells = <0>;
3586
3587 service@3 {
3588 reg = <APR_SVC_ADSP_CORE>;
3589 compatible = "qcom,q6core";
3590 };
3591
3592 q6afe: service@4 {
3593 compatible = "qcom,q6afe";
3594 reg = <APR_SVC_AFE>;
3595 q6afedai: dais {
3596 compatible = "qcom,q6afe-dais";
3597 #address-cells = <1>;
3598 #size-cells = <0>;
3599 #sound-dai-cells = <1>;
3600 dai@1 {
3601 reg = <1>;
3602 };
3603 };
3604 };
3605
3606 q6asm: service@7 {
3607 compatible = "qcom,q6asm";
3608 reg = <APR_SVC_ASM>;
3609 q6asmdai: dais {
3610 compatible = "qcom,q6asm-dais";
3611 #address-cells = <1>;
3612 #size-cells = <0>;
3613 #sound-dai-cells = <1>;
3614 iommus = <&lpass_q6_smmu 1>;
3615 };
3616 };
3617
3618 q6adm: service@8 {
3619 compatible = "qcom,q6adm";
3620 reg = <APR_SVC_ADM>;
3621 q6routing: routing {
3622 compatible = "qcom,q6adm-routing";
3623 #sound-dai-cells = <0>;
3624 };
3625 };
3626 };
3627
3628 fastrpc {
3629 compatible = "qcom,fastrpc";
3630 qcom,smd-channels = "fastrpcsmd-apps-dsp";
3631 label = "adsp";
3632 qcom,non-secure-domain;
3633 #address-cells = <1>;
3634 #size-cells = <0>;
3635
3636 cb@5 {
3637 compatible = "qcom,fastrpc-compute-cb";
3638 reg = <5>;
3639 iommus = <&lpass_q6_smmu 5>;
3640 };
3641
3642 cb@6 {
3643 compatible = "qcom,fastrpc-compute-cb";
3644 reg = <6>;
3645 iommus = <&lpass_q6_smmu 6>;
3646 };
3647
3648 cb@7 {
3649 compatible = "qcom,fastrpc-compute-cb";
3650 reg = <7>;
3651 iommus = <&lpass_q6_smmu 7>;
3652 };
3653
3654 cb@8 {
3655 compatible = "qcom,fastrpc-compute-cb";
3656 reg = <8>;
3657 iommus = <&lpass_q6_smmu 8>;
3658 };
3659
3660 cb@9 {
3661 compatible = "qcom,fastrpc-compute-cb";
3662 reg = <9>;
3663 iommus = <&lpass_q6_smmu 9>;
3664 };
3665
3666 cb@10 {
3667 compatible = "qcom,fastrpc-compute-cb";
3668 reg = <10>;
3669 iommus = <&lpass_q6_smmu 10>;
3670 };
3671
3672 cb@11 {
3673 compatible = "qcom,fastrpc-compute-cb";
3674 reg = <11>;
3675 iommus = <&lpass_q6_smmu 11>;
3676 };
3677
3678 cb@12 {
3679 compatible = "qcom,fastrpc-compute-cb";
3680 reg = <12>;
3681 iommus = <&lpass_q6_smmu 12>;
3682 };
3683 };
3684 };
3685 };
3686
3687 apcs_glb: mailbox@9820000 {
3688 compatible = "qcom,msm8996-apcs-hmss-global";
3689 reg = <0x09820000 0x1000>;
3690
3691 #mbox-cells = <1>;
3692 #clock-cells = <0>;
3693 };
3694
3695 timer@9840000 {
3696 #address-cells = <1>;
3697 #size-cells = <1>;
3698 ranges;
3699 compatible = "arm,armv7-timer-mem";
3700 reg = <0x09840000 0x1000>;
3701 clock-frequency = <19200000>;
3702
3703 frame@9850000 {
3704 frame-number = <0>;
3705 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3706 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3707 reg = <0x09850000 0x1000>,
3708 <0x09860000 0x1000>;
3709 };
3710
3711 frame@9870000 {
3712 frame-number = <1>;
3713 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3714 reg = <0x09870000 0x1000>;
3715 status = "disabled";
3716 };
3717
3718 frame@9880000 {
3719 frame-number = <2>;
3720 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3721 reg = <0x09880000 0x1000>;
3722 status = "disabled";
3723 };
3724
3725 frame@9890000 {
3726 frame-number = <3>;
3727 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3728 reg = <0x09890000 0x1000>;
3729 status = "disabled";
3730 };
3731
3732 frame@98a0000 {
3733 frame-number = <4>;
3734 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3735 reg = <0x098a0000 0x1000>;
3736 status = "disabled";
3737 };
3738
3739 frame@98b0000 {
3740 frame-number = <5>;
3741 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3742 reg = <0x098b0000 0x1000>;
3743 status = "disabled";
3744 };
3745
3746 frame@98c0000 {
3747 frame-number = <6>;
3748 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3749 reg = <0x098c0000 0x1000>;
3750 status = "disabled";
3751 };
3752 };
3753
3754 saw3: syscon@9a10000 {
3755 compatible = "syscon";
3756 reg = <0x09a10000 0x1000>;
3757 };
3758
3759 cbf: clock-controller@9a11000 {
3760 compatible = "qcom,msm8996-cbf";
3761 reg = <0x09a11000 0x10000>;
3762 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3763 #clock-cells = <0>;
3764 #interconnect-cells = <1>;
3765 };
3766
3767 intc: interrupt-controller@9bc0000 {
3768 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3769 #address-cells = <0>;
3770 #interrupt-cells = <3>;
3771 interrupt-controller;
3772 #redistributor-regions = <1>;
3773 redistributor-stride = <0x0 0x40000>;
3774 reg = <0x09bc0000 0x10000>,
3775 <0x09c00000 0x100000>;
3776 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3777 };
3778 };
3779
3780 sound: sound {
3781 };
3782
3783 thermal-zones {
3784 cpu0-thermal {
3785 polling-delay-passive = <250>;
3786
3787 thermal-sensors = <&tsens0 3>;
3788
3789 trips {
3790 cpu0_alert0: trip-point0 {
3791 temperature = <75000>;
3792 hysteresis = <2000>;
3793 type = "passive";
3794 };
3795
3796 cpu0_crit: cpu-crit {
3797 temperature = <110000>;
3798 hysteresis = <2000>;
3799 type = "critical";
3800 };
3801 };
3802 };
3803
3804 cpu1-thermal {
3805 polling-delay-passive = <250>;
3806
3807 thermal-sensors = <&tsens0 5>;
3808
3809 trips {
3810 cpu1_alert0: trip-point0 {
3811 temperature = <75000>;
3812 hysteresis = <2000>;
3813 type = "passive";
3814 };
3815
3816 cpu1_crit: cpu-crit {
3817 temperature = <110000>;
3818 hysteresis = <2000>;
3819 type = "critical";
3820 };
3821 };
3822 };
3823
3824 cpu2-thermal {
3825 polling-delay-passive = <250>;
3826
3827 thermal-sensors = <&tsens0 8>;
3828
3829 trips {
3830 cpu2_alert0: trip-point0 {
3831 temperature = <75000>;
3832 hysteresis = <2000>;
3833 type = "passive";
3834 };
3835
3836 cpu2_crit: cpu-crit {
3837 temperature = <110000>;
3838 hysteresis = <2000>;
3839 type = "critical";
3840 };
3841 };
3842 };
3843
3844 cpu3-thermal {
3845 polling-delay-passive = <250>;
3846
3847 thermal-sensors = <&tsens0 10>;
3848
3849 trips {
3850 cpu3_alert0: trip-point0 {
3851 temperature = <75000>;
3852 hysteresis = <2000>;
3853 type = "passive";
3854 };
3855
3856 cpu3_crit: cpu-crit {
3857 temperature = <110000>;
3858 hysteresis = <2000>;
3859 type = "critical";
3860 };
3861 };
3862 };
3863
3864 gpu-top-thermal {
3865 polling-delay-passive = <250>;
3866
3867 thermal-sensors = <&tsens1 6>;
3868
3869 trips {
3870 gpu1_alert0: trip-point0 {
3871 temperature = <90000>;
3872 hysteresis = <2000>;
3873 type = "passive";
3874 };
3875 };
3876
3877 cooling-maps {
3878 map0 {
3879 trip = <&gpu1_alert0>;
3880 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3881 };
3882 };
3883 };
3884
3885 gpu-bottom-thermal {
3886 polling-delay-passive = <250>;
3887
3888 thermal-sensors = <&tsens1 7>;
3889
3890 trips {
3891 gpu2_alert0: trip-point0 {
3892 temperature = <90000>;
3893 hysteresis = <2000>;
3894 type = "passive";
3895 };
3896 };
3897
3898 cooling-maps {
3899 map0 {
3900 trip = <&gpu2_alert0>;
3901 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3902 };
3903 };
3904 };
3905
3906 m4m-thermal {
3907 polling-delay-passive = <250>;
3908
3909 thermal-sensors = <&tsens0 1>;
3910
3911 trips {
3912 m4m_alert0: trip-point0 {
3913 temperature = <90000>;
3914 hysteresis = <2000>;
3915 type = "hot";
3916 };
3917 };
3918 };
3919
3920 l3-or-venus-thermal {
3921 polling-delay-passive = <250>;
3922
3923 thermal-sensors = <&tsens0 2>;
3924
3925 trips {
3926 l3_or_venus_alert0: trip-point0 {
3927 temperature = <90000>;
3928 hysteresis = <2000>;
3929 type = "hot";
3930 };
3931 };
3932 };
3933
3934 cluster0-l2-thermal {
3935 polling-delay-passive = <250>;
3936
3937 thermal-sensors = <&tsens0 7>;
3938
3939 trips {
3940 cluster0_l2_alert0: trip-point0 {
3941 temperature = <90000>;
3942 hysteresis = <2000>;
3943 type = "hot";
3944 };
3945 };
3946 };
3947
3948 cluster1-l2-thermal {
3949 polling-delay-passive = <250>;
3950
3951 thermal-sensors = <&tsens0 12>;
3952
3953 trips {
3954 cluster1_l2_alert0: trip-point0 {
3955 temperature = <90000>;
3956 hysteresis = <2000>;
3957 type = "hot";
3958 };
3959 };
3960 };
3961
3962 camera-thermal {
3963 polling-delay-passive = <250>;
3964
3965 thermal-sensors = <&tsens1 1>;
3966
3967 trips {
3968 camera_alert0: trip-point0 {
3969 temperature = <90000>;
3970 hysteresis = <2000>;
3971 type = "hot";
3972 };
3973 };
3974 };
3975
3976 q6-dsp-thermal {
3977 polling-delay-passive = <250>;
3978
3979 thermal-sensors = <&tsens1 2>;
3980
3981 trips {
3982 q6_dsp_alert0: trip-point0 {
3983 temperature = <90000>;
3984 hysteresis = <2000>;
3985 type = "hot";
3986 };
3987 };
3988 };
3989
3990 mem-thermal {
3991 polling-delay-passive = <250>;
3992
3993 thermal-sensors = <&tsens1 3>;
3994
3995 trips {
3996 mem_alert0: trip-point0 {
3997 temperature = <90000>;
3998 hysteresis = <2000>;
3999 type = "hot";
4000 };
4001 };
4002 };
4003
4004 modemtx-thermal {
4005 polling-delay-passive = <250>;
4006
4007 thermal-sensors = <&tsens1 4>;
4008
4009 trips {
4010 modemtx_alert0: trip-point0 {
4011 temperature = <90000>;
4012 hysteresis = <2000>;
4013 type = "hot";
4014 };
4015 };
4016 };
4017 };
4018
4019 timer {
4020 compatible = "arm,armv8-timer";
4021 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
4022 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
4023 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
4024 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
4025 };
4026};