tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare Ethernet PCS
8
9maintainers:
10 - Serge Semin <fancer.lancer@gmail.com>
11
12description:
13 Synopsys DesignWare Ethernet Physical Coding Sublayer provides an interface
14 between Media Access Control and Physical Medium Attachment Sublayer through
15 the Media Independent Interface (XGMII, USXGMII, XLGMII, GMII, etc)
16 controlled by means of the IEEE std. Clause 45 registers set. The PCS can be
17 optionally synthesized with a vendor-specific interface connected to
18 Synopsys PMA (also called DesignWare Consumer/Enterprise PHY) although in
19 general it can be used to communicate with any compatible PHY.
20
21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
22 by means of the APB3/MCI interfaces. In the later case the XPCS can be mapped
23 right to the system IO memory space.
24
25properties:
26 compatible:
27 oneOf:
28 - description: Synopsys DesignWare XPCS with none or unknown PMA
29 const: snps,dw-xpcs
30 - description: Synopsys DesignWare XPCS with Consumer Gen1 3G PMA
31 const: snps,dw-xpcs-gen1-3g
32 - description: Synopsys DesignWare XPCS with Consumer Gen2 3G PMA
33 const: snps,dw-xpcs-gen2-3g
34 - description: Synopsys DesignWare XPCS with Consumer Gen2 6G PMA
35 const: snps,dw-xpcs-gen2-6g
36 - description: Synopsys DesignWare XPCS with Consumer Gen4 3G PMA
37 const: snps,dw-xpcs-gen4-3g
38 - description: Synopsys DesignWare XPCS with Consumer Gen4 6G PMA
39 const: snps,dw-xpcs-gen4-6g
40 - description: Synopsys DesignWare XPCS with Consumer Gen5 10G PMA
41 const: snps,dw-xpcs-gen5-10g
42 - description: Synopsys DesignWare XPCS with Consumer Gen5 12G PMA
43 const: snps,dw-xpcs-gen5-12g
44
45 reg:
46 items:
47 - description:
48 In case of the MDIO management interface this just a 5-bits ID
49 of the MDIO bus device. If DW XPCS CSRs space is accessed over the
50 MCI or APB3 management interfaces, then the space mapping can be
51 either 'direct' or 'indirect'. In the former case all Clause 45
52 registers are contiguously mapped within the address space
53 MMD '[20:16]', Reg '[15:0]'. In the later case the space is divided
54 to the multiple 256 register sets. There is a special viewport CSR
55 which is responsible for the set selection. The upper part of
56 the CSR address MMD+REG[20:8] is supposed to be written in there
57 so the corresponding subset would be mapped to the lowest 255 CSRs.
58
59 reg-names:
60 items:
61 - enum: [ direct, indirect ]
62
63 reg-io-width:
64 description:
65 The way the CSRs are mapped to the memory is platform depended. Since
66 each Clause 45 CSR is of 16-bits wide the access instructions must be
67 two bytes aligned at least.
68 default: 2
69 enum: [ 2, 4 ]
70
71 interrupts:
72 description:
73 System interface interrupt output (sbd_intr_o) indicating Clause 73/37
74 auto-negotiation events':' Page received, AN is completed or incompatible
75 link partner.
76 maxItems: 1
77
78 clocks:
79 description:
80 The MCI and APB3 interfaces are supposed to be equipped with a clock
81 source connected to the clk_csr_i line.
82
83 PCS/PMA layer can be clocked by an internal reference clock source
84 (phyN_core_refclk) or by an externally connected (phyN_pad_refclk) clock
85 generator. Both clocks can be supplied at a time.
86 minItems: 1
87 maxItems: 3
88
89 clock-names:
90 oneOf:
91 - minItems: 1
92 items: # MDIO
93 - enum: [core, pad]
94 - const: pad
95 - minItems: 1
96 items: # MCI or APB
97 - const: csr
98 - enum: [core, pad]
99 - const: pad
100
101required:
102 - compatible
103 - reg
104
105additionalProperties: false
106
107examples:
108 - |
109 #include <dt-bindings/interrupt-controller/irq.h>
110
111 ethernet-pcs@1f05d000 {
112 compatible = "snps,dw-xpcs";
113 reg = <0x1f05d000 0x1000>;
114 reg-names = "indirect";
115
116 reg-io-width = <4>;
117
118 interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
119
120 clocks = <&ccu_pclk>, <&ccu_core>, <&ccu_pad>;
121 clock-names = "csr", "core", "pad";
122 };
123 - |
124 mdio-bus {
125 #address-cells = <1>;
126 #size-cells = <0>;
127
128 ethernet-pcs@0 {
129 compatible = "snps,dw-xpcs";
130 reg = <0>;
131
132 clocks = <&ccu_core>, <&ccu_pad>;
133 clock-names = "core", "pad";
134 };
135 };
136...