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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Amlogic Meson DWMAC Ethernet controller
9
10maintainers:
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13
14# We need a select here so we don't match all nodes with 'snps,dwmac'
15select:
16 properties:
17 compatible:
18 contains:
19 enum:
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
24 - amlogic,meson-axg-dwmac
25 - amlogic,meson-g12a-dwmac
26 required:
27 - compatible
28
29allOf:
30 - $ref: snps,dwmac.yaml#
31 - if:
32 properties:
33 compatible:
34 contains:
35 enum:
36 - amlogic,meson8b-dwmac
37 - amlogic,meson8m2-dwmac
38 - amlogic,meson-gxbb-dwmac
39 - amlogic,meson-axg-dwmac
40 - amlogic,meson-g12a-dwmac
41
42 then:
43 properties:
44 clocks:
45 minItems: 3
46 items:
47 - description: GMAC main clock
48 - description: First parent clock of the internal mux
49 - description: Second parent clock of the internal mux
50 - description: The clock which drives the timing adjustment logic
51
52 clock-names:
53 minItems: 3
54 items:
55 - const: stmmaceth
56 - const: clkin0
57 - const: clkin1
58 - const: timing-adjustment
59
60 amlogic,tx-delay-ns:
61 enum: [0, 2, 4, 6]
62 default: 2
63 description:
64 The internal RGMII TX clock delay (provided by this driver)
65 in nanoseconds. When phy-mode is set to "rgmii" then the TX
66 delay should be explicitly configured. When the phy-mode is
67 set to either "rgmii-id" or "rgmii-txid" the TX clock delay
68 is already provided by the PHY. In that case this property
69 should be set to 0ns (which disables the TX clock delay in
70 the MAC to prevent the clock from going off because both
71 PHY and MAC are adding a delay). Any configuration is
72 ignored when the phy-mode is set to "rmii".
73
74 amlogic,rx-delay-ns:
75 deprecated: true
76 enum:
77 - 0
78 - 2
79 default: 0
80 description:
81 The internal RGMII RX clock delay in nanoseconds. Deprecated, use
82 rx-internal-delay-ps instead.
83
84 rx-internal-delay-ps:
85 default: 0
86
87 - if:
88 properties:
89 compatible:
90 contains:
91 enum:
92 - amlogic,meson8b-dwmac
93 - amlogic,meson8m2-dwmac
94 - amlogic,meson-gxbb-dwmac
95 - amlogic,meson-axg-dwmac
96 then:
97 properties:
98 rx-internal-delay-ps:
99 enum:
100 - 0
101 - 2000
102
103 - if:
104 properties:
105 compatible:
106 contains:
107 enum:
108 - amlogic,meson-g12a-dwmac
109 then:
110 properties:
111 rx-internal-delay-ps:
112 enum:
113 - 0
114 - 200
115 - 400
116 - 600
117 - 800
118 - 1000
119 - 1200
120 - 1400
121 - 1600
122 - 1800
123 - 2000
124 - 2200
125 - 2400
126 - 2600
127 - 2800
128 - 3000
129
130properties:
131 compatible:
132 additionalItems: true
133 maxItems: 3
134 items:
135 - enum:
136 - amlogic,meson6-dwmac
137 - amlogic,meson8b-dwmac
138 - amlogic,meson8m2-dwmac
139 - amlogic,meson-gxbb-dwmac
140 - amlogic,meson-axg-dwmac
141 - amlogic,meson-g12a-dwmac
142 contains:
143 enum:
144 - snps,dwmac-3.70a
145 - snps,dwmac
146
147 reg:
148 items:
149 - description:
150 The first register range should be the one of the DWMAC controller
151 - description:
152 The second range is for the Amlogic specific configuration
153 (for example the PRG_ETHERNET register range on Meson8b and newer)
154
155 interrupts:
156 maxItems: 1
157
158 interrupt-names:
159 const: macirq
160
161required:
162 - compatible
163 - reg
164 - interrupts
165 - interrupt-names
166 - clocks
167 - clock-names
168 - phy-mode
169
170unevaluatedProperties: false
171
172examples:
173 - |
174 ethmac: ethernet@c9410000 {
175 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
176 reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
177 interrupts = <8>;
178 interrupt-names = "macirq";
179 clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
180 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
181 phy-mode = "rgmii";
182 };