tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6title: LogicoreIP designed compatible with Xilinx ZYNQ family.
7
8maintainers:
9 - Rohit Visavalia <rohit.visavalia@amd.com>
10
11description:
12 LogicoreIP design to provide the isolation between processing system
13 and programmable logic. Also provides the list of register set to configure
14 the frequency.
15
16properties:
17 compatible:
18 items:
19 - enum:
20 - xlnx,vcu
21 - xlnx,vcu-logicoreip-1.0
22
23 reg:
24 maxItems: 1
25
26 clocks:
27 items:
28 - description: pll ref clocksource
29 - description: aclk
30
31 clock-names:
32 items:
33 - const: pll_ref
34 - const: aclk
35
36 reset-gpios:
37 maxItems: 1
38
39required:
40 - reg
41 - clocks
42 - clock-names
43
44additionalProperties: false
45
46examples:
47 - |
48 #include <dt-bindings/gpio/gpio.h>
49 fpga {
50 #address-cells = <2>;
51 #size-cells = <2>;
52 xlnx_vcu: vcu@a0040000 {
53 compatible = "xlnx,vcu-logicoreip-1.0";
54 reg = <0x0 0xa0040000 0x0 0x1000>;
55 reset-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>;
56 clocks = <&si570_1>, <&clkc 71>;
57 clock-names = "pll_ref", "aclk";
58 };
59 };