tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
3#include <linux/device.h>
4#include <linux/module.h>
5#include <linux/slab.h>
6
7#include "cxlmem.h"
8#include "cxlpci.h"
9
10/**
11 * DOC: cxl port
12 *
13 * The port driver enumerates dport via PCI and scans for HDM
14 * (Host-managed-Device-Memory) decoder resources via the
15 * @component_reg_phys value passed in by the agent that registered the
16 * port. All descendant ports of a CXL root port (described by platform
17 * firmware) are managed in this drivers context. Each driver instance
18 * is responsible for tearing down the driver context of immediate
19 * descendant ports. The locking for this is validated by
20 * CONFIG_PROVE_CXL_LOCKING.
21 *
22 * The primary service this driver provides is presenting APIs to other
23 * drivers to utilize the decoders, and indicating to userspace (via bind
24 * status) the connectivity of the CXL.mem protocol throughout the
25 * PCIe topology.
26 */
27
28static void schedule_detach(void *cxlmd)
29{
30 schedule_cxl_memdev_detach(cxlmd);
31}
32
33static int discover_region(struct device *dev, void *unused)
34{
35 struct cxl_endpoint_decoder *cxled;
36 int rc;
37
38 if (!is_endpoint_decoder(dev))
39 return 0;
40
41 cxled = to_cxl_endpoint_decoder(dev);
42 if ((cxled->cxld.flags & CXL_DECODER_F_ENABLE) == 0)
43 return 0;
44
45 if (cxled->state != CXL_DECODER_STATE_AUTO)
46 return 0;
47
48 /*
49 * Region enumeration is opportunistic, if this add-event fails,
50 * continue to the next endpoint decoder.
51 */
52 rc = cxl_add_to_region(cxled);
53 if (rc)
54 dev_dbg(dev, "failed to add to region: %#llx-%#llx\n",
55 cxled->cxld.hpa_range.start, cxled->cxld.hpa_range.end);
56
57 return 0;
58}
59
60static int cxl_switch_port_probe(struct cxl_port *port)
61{
62 /* Reset nr_dports for rebind of driver */
63 port->nr_dports = 0;
64
65 /* Cache the data early to ensure is_visible() works */
66 read_cdat_data(port);
67
68 return 0;
69}
70
71static int cxl_endpoint_port_probe(struct cxl_port *port)
72{
73 struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
74 int rc;
75
76 /* Cache the data early to ensure is_visible() works */
77 read_cdat_data(port);
78 cxl_endpoint_parse_cdat(port);
79
80 get_device(&cxlmd->dev);
81 rc = devm_add_action_or_reset(&port->dev, schedule_detach, cxlmd);
82 if (rc)
83 return rc;
84
85 rc = devm_cxl_endpoint_decoders_setup(port);
86 if (rc)
87 return rc;
88
89 /*
90 * Now that all endpoint decoders are successfully enumerated, try to
91 * assemble regions from committed decoders
92 */
93 device_for_each_child(&port->dev, NULL, discover_region);
94
95 return 0;
96}
97
98static int cxl_port_probe(struct device *dev)
99{
100 struct cxl_port *port = to_cxl_port(dev);
101
102 if (is_cxl_endpoint(port))
103 return cxl_endpoint_port_probe(port);
104 return cxl_switch_port_probe(port);
105}
106
107static ssize_t CDAT_read(struct file *filp, struct kobject *kobj,
108 const struct bin_attribute *bin_attr, char *buf,
109 loff_t offset, size_t count)
110{
111 struct device *dev = kobj_to_dev(kobj);
112 struct cxl_port *port = to_cxl_port(dev);
113
114 if (!port->cdat_available)
115 return -ENXIO;
116
117 if (!port->cdat.table)
118 return 0;
119
120 return memory_read_from_buffer(buf, count, &offset,
121 port->cdat.table,
122 port->cdat.length);
123}
124
125static const BIN_ATTR_ADMIN_RO(CDAT, 0);
126
127static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
128 const struct bin_attribute *attr, int i)
129{
130 struct device *dev = kobj_to_dev(kobj);
131 struct cxl_port *port = to_cxl_port(dev);
132
133 if ((attr == &bin_attr_CDAT) && port->cdat_available)
134 return attr->attr.mode;
135
136 return 0;
137}
138
139static const struct bin_attribute *const cxl_cdat_bin_attributes[] = {
140 &bin_attr_CDAT,
141 NULL,
142};
143
144static const struct attribute_group cxl_cdat_attribute_group = {
145 .bin_attrs = cxl_cdat_bin_attributes,
146 .is_bin_visible = cxl_port_bin_attr_is_visible,
147};
148
149static const struct attribute_group *cxl_port_attribute_groups[] = {
150 &cxl_cdat_attribute_group,
151 NULL,
152};
153
154static struct cxl_driver cxl_port_driver = {
155 .name = "cxl_port",
156 .probe = cxl_port_probe,
157 .id = CXL_DEVICE_PORT,
158 .drv = {
159 .dev_groups = cxl_port_attribute_groups,
160 },
161};
162
163static int __init cxl_port_init(void)
164{
165 return cxl_driver_register(&cxl_port_driver);
166}
167/*
168 * Be ready to immediately enable ports emitted by the platform CXL root
169 * (e.g. cxl_acpi) when CONFIG_CXL_PORT=y.
170 */
171subsys_initcall(cxl_port_init);
172
173static void __exit cxl_port_exit(void)
174{
175 cxl_driver_unregister(&cxl_port_driver);
176}
177module_exit(cxl_port_exit);
178
179MODULE_DESCRIPTION("CXL: Port enumeration and services");
180MODULE_LICENSE("GPL v2");
181MODULE_IMPORT_NS("CXL");
182MODULE_ALIAS_CXL(CXL_DEVICE_PORT);