tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef SOC15_H
24#define SOC15_H
25
26#define GFX9_NUM_GFX_RINGS 1
27#define GFX9_NUM_COMPUTE_RINGS 8
28
29/*
30 * PM4
31 */
32#define PACKET_TYPE0 0
33#define PACKET_TYPE1 1
34#define PACKET_TYPE2 2
35#define PACKET_TYPE3 3
36
37#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
38#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
39#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
40#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
41#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
42 ((reg) & 0xFFFF) | \
43 ((n) & 0x3FFF) << 16)
44#define CP_PACKET2 0x80000000
45#define PACKET2_PAD_SHIFT 0
46#define PACKET2_PAD_MASK (0x3fffffff << 0)
47
48#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
49
50#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
51 (((op) & 0xFF) << 8) | \
52 ((n) & 0x3FFF) << 16)
53
54#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
55
56#define PACKETJ_CONDITION_CHECK0 0
57#define PACKETJ_CONDITION_CHECK1 1
58#define PACKETJ_CONDITION_CHECK2 2
59#define PACKETJ_CONDITION_CHECK3 3
60#define PACKETJ_CONDITION_CHECK4 4
61#define PACKETJ_CONDITION_CHECK5 5
62#define PACKETJ_CONDITION_CHECK6 6
63#define PACKETJ_CONDITION_CHECK7 7
64
65#define PACKETJ_TYPE0 0
66#define PACKETJ_TYPE1 1
67#define PACKETJ_TYPE2 2
68#define PACKETJ_TYPE3 3
69#define PACKETJ_TYPE4 4
70#define PACKETJ_TYPE5 5
71#define PACKETJ_TYPE6 6
72#define PACKETJ_TYPE7 7
73
74#define PACKETJ(reg, r, cond, type) ((reg & 0x3FFFF) | \
75 ((r & 0x3F) << 18) | \
76 ((cond & 0xF) << 24) | \
77 ((type & 0xF) << 28))
78
79#define CP_PACKETJ_NOP 0x60000000
80#define CP_PACKETJ_GET_REG(x) ((x) & 0x3FFFF)
81#define CP_PACKETJ_GET_RES(x) (((x) >> 18) & 0x3F)
82#define CP_PACKETJ_GET_COND(x) (((x) >> 24) & 0xF)
83#define CP_PACKETJ_GET_TYPE(x) (((x) >> 28) & 0xF)
84
85/* Packet 3 types */
86#define PACKET3_NOP 0x10
87#define PACKET3_SET_BASE 0x11
88#define PACKET3_BASE_INDEX(x) ((x) << 0)
89#define CE_PARTITION_BASE 3
90#define PACKET3_CLEAR_STATE 0x12
91#define PACKET3_INDEX_BUFFER_SIZE 0x13
92#define PACKET3_DISPATCH_DIRECT 0x15
93#define PACKET3_DISPATCH_INDIRECT 0x16
94#define PACKET3_ATOMIC_GDS 0x1D
95#define PACKET3_ATOMIC_MEM 0x1E
96#define PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned)(x)) & 0x3F) << 0)
97#define PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned)(x)) & 0xF) << 8)
98#define PACKET3_ATOMIC_MEM__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
99#define PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x)) << 0)
100#define PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x)) << 0)
101#define PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned)(x)) << 0)
102#define PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned)(x)) << 0)
103#define PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned)(x)) << 0)
104#define PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned)(x)) << 0)
105#define PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned)(x)) & 0x1FFF) << 0)
106#define PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC 0
107#define PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED 1
108#define PACKET3_OCCLUSION_QUERY 0x1F
109#define PACKET3_SET_PREDICATION 0x20
110#define PACKET3_REG_RMW 0x21
111#define PACKET3_COND_EXEC 0x22
112#define PACKET3_PRED_EXEC 0x23
113#define PACKET3_PRED_EXEC__EXEC_COUNT(x) ((((unsigned)(x)) & 0x3FFF) << 0)
114#define PACKET3_PRED_EXEC__VIRTUAL_XCC_ID_SELECT(x) ((((unsigned)(x)) & 0xFF) << 24)
115#define PACKET3_DRAW_INDIRECT 0x24
116#define PACKET3_DRAW_INDEX_INDIRECT 0x25
117#define PACKET3_INDEX_BASE 0x26
118#define PACKET3_DRAW_INDEX_2 0x27
119#define PACKET3_CONTEXT_CONTROL 0x28
120#define PACKET3_INDEX_TYPE 0x2A
121#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
122#define PACKET3_DRAW_INDEX_AUTO 0x2D
123#define PACKET3_NUM_INSTANCES 0x2F
124#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
125#define PACKET3_INDIRECT_BUFFER_CONST 0x33
126#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
127#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
128#define PACKET3_DRAW_PREAMBLE 0x36
129#define PACKET3_WRITE_DATA 0x37
130#define WRITE_DATA_DST_SEL(x) ((x) << 8)
131 /* 0 - register
132 * 1 - memory (sync - via GRBM)
133 * 2 - gl2
134 * 3 - gds
135 * 4 - reserved
136 * 5 - memory (async - direct)
137 */
138#define WR_ONE_ADDR (1 << 16)
139#define WR_CONFIRM (1 << 20)
140#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
141 /* 0 - LRU
142 * 1 - Stream
143 */
144#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
145 /* 0 - me
146 * 1 - pfp
147 * 2 - ce
148 */
149#define PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8)
150#define PACKET3_WRITE_DATA__ADDR_INCR(x) ((((unsigned)(x)) & 0x1) << 16)
151#define PACKET3_WRITE_DATA__RESUME_VF_MI300(x) ((((unsigned)(x)) & 0x1) << 19)
152#define PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20)
153#define PACKET3_WRITE_DATA__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
154#define PACKET3_WRITE_DATA__DST_MMREG_ADDR(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
155#define PACKET3_WRITE_DATA__DST_GDS_ADDR(x) ((((unsigned)(x)) & 0xFFFF) << 0)
156#define PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
157#define PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned)(x))
158#define PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER 0
159#define PACKET3_WRITE_DATA__DST_SEL__TC_L2 2
160#define PACKET3_WRITE_DATA__DST_SEL__GDS 3
161#define PACKET3_WRITE_DATA__DST_SEL__MEMORY 5
162#define PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE 6
163#define PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS 0
164#define PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS 1
165#define PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION 0
166#define PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION 1
167#define PACKET3_WRITE_DATA__CACHE_POLICY__LRU 0
168#define PACKET3_WRITE_DATA__CACHE_POLICY__STREAM 1
169#define PACKET3_WRITE_DATA__CACHE_POLICY__NOA 2
170#define PACKET3_WRITE_DATA__CACHE_POLICY__BYPASS 3
171#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
172#define PACKET3_MEM_SEMAPHORE 0x39
173# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
174# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
175# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
176# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
177#define PACKET3_WAIT_REG_MEM 0x3C
178#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
179 /* 0 - always
180 * 1 - <
181 * 2 - <=
182 * 3 - ==
183 * 4 - !=
184 * 5 - >=
185 * 6 - >
186 */
187#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
188 /* 0 - reg
189 * 1 - mem
190 */
191#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
192 /* 0 - wait_reg_mem
193 * 1 - wr_wait_wr_reg
194 */
195#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
196 /* 0 - me
197 * 1 - pfp
198 */
199#define PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned)(x)) & 0x7) << 0)
200#define PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned)(x)) & 0x3) << 4)
201#define PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned)(x)) & 0x3) << 6)
202#define PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 22)
203#define PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned)(x)) & 0x1) << 24)
204#define PACKET3_WAIT_REG_MEM__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
205#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
206#define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
207#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
208#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned)(x))
209#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
210#define PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned)(x))
211#define PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x))
212#define PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0)
213#define PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) & 0x1) << 31)
214#define PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS 0
215#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE 1
216#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE 2
217#define PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE 3
218#define PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE 4
219#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE 5
220#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE 6
221#define PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE 0
222#define PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE 1
223#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM 0
224#define PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG 1
225#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE 3
226#define PACKET3_INDIRECT_BUFFER 0x3F
227#define INDIRECT_BUFFER_VALID (1 << 23)
228#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
229 /* 0 - LRU
230 * 1 - Stream
231 * 2 - Bypass
232 */
233#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21)
234#define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30)
235#define PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
236#define PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned)(x))
237#define PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned)(x)) & 0xFFFFF) << 0)
238#define PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned)(x)) & 0x1) << 20)
239#define PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned)(x)) & 0x1) << 21)
240#define PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned)(x)) & 0x1) << 23)
241#define PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned)(x)) & 0xF) << 24)
242#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 28)
243#define PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) & 0x1) << 31)
244#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__LRU 0
245#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__STREAM 1
246#define PACKET3_COPY_DATA 0x40
247#define PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned)(x)) & 0xF) << 0)
248#define PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8)
249#define PACKET3_COPY_DATA__SRC_CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 13)
250#define PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned)(x)) & 0x1) << 16)
251#define PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20)
252#define PACKET3_COPY_DATA__DST_CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
253#define PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 29)
254#define PACKET3_COPY_DATA__SRC_REG_OFFSET(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
255#define PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
256#define PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
257#define PACKET3_COPY_DATA__SRC_GDS_ADDR_LO(x) ((((unsigned)(x)) & 0xFFFF) << 0)
258#define PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x))
259#define PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned)(x))
260#define PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned)(x))
261#define PACKET3_COPY_DATA__DST_REG_OFFSET(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
262#define PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
263#define PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
264#define PACKET3_COPY_DATA__DST_GDS_ADDR_LO(x) ((((unsigned)(x)) & 0xFFFF) << 0)
265#define PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned)(x))
266#define PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER 0
267#define PACKET3_COPY_DATA__SRC_SEL__MEMORY 1
268#define PACKET3_COPY_DATA__SRC_SEL__TC_L2 2
269#define PACKET3_COPY_DATA__SRC_SEL__GDS 3
270#define PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS 4
271#define PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA 5
272#define PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA 6
273#define PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA0 7
274#define PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA1 8
275#define PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT 9
276#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER 0
277#define PACKET3_COPY_DATA__DST_SEL__TC_L2 2
278#define PACKET3_COPY_DATA__DST_SEL__GDS 3
279#define PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS 4
280#define PACKET3_COPY_DATA__DST_SEL__MEMORY 5
281#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC 6
282#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__LRU 0
283#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM 1
284#define PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA 0
285#define PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA 1
286#define PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION 0
287#define PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION 1
288#define PACKET3_COPY_DATA__DST_CACHE_POLICY__LRU 0
289#define PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM 1
290#define PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT 0
291#define PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE 1
292#define PACKET3_PFP_SYNC_ME 0x42
293#define PACKET3_COND_WRITE 0x45
294#define PACKET3_EVENT_WRITE 0x46
295#define EVENT_TYPE(x) ((x) << 0)
296#define EVENT_INDEX(x) ((x) << 8)
297 /* 0 - any non-TS event
298 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
299 * 2 - SAMPLE_PIPELINESTAT
300 * 3 - SAMPLE_STREAMOUTSTAT*
301 * 4 - *S_PARTIAL_FLUSH
302 */
303#define PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0)
304#define PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8)
305#define PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned)(x)) & 0x1) << 31)
306#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE(x) ((((unsigned)(x)) & 0x3) << 29)
307#define PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
308#define PACKET3_EVENT_WRITE__ADDRESS_HI(x) (((unsigned)(x)) << 0)
309#define PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER 0
310#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTATS 2
311#define PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH 4
312#define PACKET3_RELEASE_MEM 0x49
313#define EVENT_TYPE(x) ((x) << 0)
314#define EVENT_INDEX(x) ((x) << 8)
315#define EOP_TCL1_VOL_ACTION_EN (1 << 12)
316#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
317#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
318#define EOP_TCL1_ACTION_EN (1 << 16)
319#define EOP_TC_ACTION_EN (1 << 17) /* L2 */
320#define EOP_TC_NC_ACTION_EN (1 << 19)
321#define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */
322#define EOP_EXEC (1 << 28) /* For Trailing Fence */
323
324#define DATA_SEL(x) ((x) << 29)
325 /* 0 - discard
326 * 1 - send low 32bit data
327 * 2 - send 64bit data
328 * 3 - send 64bit GPU counter value
329 * 4 - send 64bit sys counter value
330 */
331#define INT_SEL(x) ((x) << 24)
332 /* 0 - none
333 * 1 - interrupt only (DATA_SEL = 0)
334 * 2 - interrupt when data write is confirmed
335 */
336#define DST_SEL(x) ((x) << 16)
337 /* 0 - MC
338 * 1 - TC/L2
339 */
340
341
342
343#define PACKET3_PREAMBLE_CNTL 0x4A
344# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
345# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
346#define PACKET3_DMA_DATA 0x50
347/* 1. header
348 * 2. CONTROL
349 * 3. SRC_ADDR_LO or DATA [31:0]
350 * 4. SRC_ADDR_HI [31:0]
351 * 5. DST_ADDR_LO [31:0]
352 * 6. DST_ADDR_HI [7:0]
353 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
354 */
355/* CONTROL */
356# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
357 /* 0 - ME
358 * 1 - PFP
359 */
360# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
361 /* 0 - LRU
362 * 1 - Stream
363 */
364# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
365 /* 0 - DST_ADDR using DAS
366 * 1 - GDS
367 * 3 - DST_ADDR using L2
368 */
369# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
370 /* 0 - LRU
371 * 1 - Stream
372 */
373# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
374 /* 0 - SRC_ADDR using SAS
375 * 1 - GDS
376 * 2 - DATA
377 * 3 - SRC_ADDR using L2
378 */
379# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
380/* COMMAND */
381# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
382 /* 0 - memory
383 * 1 - register
384 */
385# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
386 /* 0 - memory
387 * 1 - register
388 */
389# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
390# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
391# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
392#define PACKET3_ACQUIRE_MEM 0x58
393/* 1. HEADER
394 * 2. COHER_CNTL [30:0]
395 * 2.1 ENGINE_SEL [31:31]
396 * 3. COHER_SIZE [31:0]
397 * 4. COHER_SIZE_HI [7:0]
398 * 5. COHER_BASE_LO [31:0]
399 * 6. COHER_BASE_HI [23:0]
400 * 7. POLL_INTERVAL [15:0]
401 */
402/* COHER_CNTL fields for CP_COHER_CNTL */
403#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3)
404#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) ((x) << 4)
405#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5)
406#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15)
407#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) ((x) << 18)
408#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) ((x) << 22)
409#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) << 23)
410#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) << 25)
411#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) << 26)
412#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27)
413#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28)
414#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29)
415#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30)
416#define PACKET3_REWIND 0x59
417#define PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned)(x))
418#define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned)(x)) & 0xFF) << 0)
419#define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI_VG10(x) ((((unsigned)(x)) & 0xFFFFFF) << 0)
420#define PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned)(x))
421#define PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned)(x)) & 0xFFFFFF) << 0)
422#define PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0)
423#define PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x7FF) << 0)
424#define PACKET3_LOAD_UCONFIG_REG 0x5E
425#define PACKET3_LOAD_SH_REG 0x5F
426#define PACKET3_LOAD_CONFIG_REG 0x60
427#define PACKET3_LOAD_CONTEXT_REG 0x61
428#define PACKET3_SET_CONFIG_REG 0x68
429#define PACKET3_SET_CONFIG_REG_START 0x00002000
430#define PACKET3_SET_CONFIG_REG_END 0x00002c00
431#define PACKET3_SET_CONTEXT_REG 0x69
432#define PACKET3_SET_CONTEXT_REG_START 0x0000a000
433#define PACKET3_SET_CONTEXT_REG_END 0x0000a400
434#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
435#define PACKET3_SET_SH_REG 0x76
436#define PACKET3_SET_SH_REG_START 0x00002c00
437#define PACKET3_SET_SH_REG_END 0x00003000
438#define PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0)
439#define PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned)(x)) & 0x1F) << 23)
440#define PACKET3_SET_SH_REG__INDEX(x) ((((unsigned)(x)) & 0xF) << 28)
441#define PACKET3_SET_SH_REG_OFFSET 0x77
442#define PACKET3_SET_QUEUE_REG 0x78
443#define PACKET3_SET_UCONFIG_REG 0x79
444#define PACKET3_SET_UCONFIG_REG_START 0x0000c000
445#define PACKET3_SET_UCONFIG_REG_END 0x0000c400
446#define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28)
447#define PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0)
448#define PACKET3_SCRATCH_RAM_WRITE 0x7D
449#define PACKET3_SCRATCH_RAM_READ 0x7E
450#define PACKET3_LOAD_CONST_RAM 0x80
451#define PACKET3_WRITE_CONST_RAM 0x81
452#define PACKET3_DUMP_CONST_RAM 0x83
453#define PACKET3_INCREMENT_CE_COUNTER 0x84
454#define PACKET3_INCREMENT_DE_COUNTER 0x85
455#define PACKET3_WAIT_ON_CE_COUNTER 0x86
456#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
457#define PACKET3_SWITCH_BUFFER 0x8B
458#define PACKET3_FRAME_CONTROL 0x90
459# define FRAME_TMZ (1 << 0)
460# define FRAME_CMD(x) ((x) << 28)
461 /*
462 * x=0: tmz_begin
463 * x=1: tmz_end
464 */
465
466#define PACKET3_INVALIDATE_TLBS 0x98
467# define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0)
468# define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4)
469# define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5)
470# define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29)
471#define PACKET3_SET_RESOURCES 0xA0
472/* 1. header
473 * 2. CONTROL
474 * 3. QUEUE_MASK_LO [31:0]
475 * 4. QUEUE_MASK_HI [31:0]
476 * 5. GWS_MASK_LO [31:0]
477 * 6. GWS_MASK_HI [31:0]
478 * 7. OAC_MASK [15:0]
479 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0]
480 */
481# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0)
482# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)
483# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29)
484#define PACKET3_MAP_QUEUES 0xA2
485/* 1. header
486 * 2. CONTROL
487 * 3. CONTROL2
488 * 4. MQD_ADDR_LO [31:0]
489 * 5. MQD_ADDR_HI [31:0]
490 * 6. WPTR_ADDR_LO [31:0]
491 * 7. WPTR_ADDR_HI [31:0]
492 */
493/* CONTROL */
494# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
495# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8)
496# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13)
497# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16)
498# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18)
499# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21)
500# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24)
501# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
502# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
503/* CONTROL2 */
504# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1)
505# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)
506#define PACKET3_UNMAP_QUEUES 0xA3
507/* 1. header
508 * 2. CONTROL
509 * 3. CONTROL2
510 * 4. CONTROL3
511 * 5. CONTROL4
512 * 6. CONTROL5
513 */
514/* CONTROL */
515# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0)
516 /* 0 - PREEMPT_QUEUES
517 * 1 - RESET_QUEUES
518 * 2 - DISABLE_PROCESS_QUEUES
519 * 3 - PREEMPT_QUEUES_NO_UNMAP
520 */
521# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
522# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
523# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
524/* CONTROL2a */
525# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0)
526/* CONTROL2b */
527# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)
528/* CONTROL3a */
529# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)
530/* CONTROL3b */
531# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0)
532/* CONTROL4 */
533# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)
534/* CONTROL5 */
535# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)
536#define PACKET3_QUERY_STATUS 0xA4
537/* 1. header
538 * 2. CONTROL
539 * 3. CONTROL2
540 * 4. ADDR_LO [31:0]
541 * 5. ADDR_HI [31:0]
542 * 6. DATA_LO [31:0]
543 * 7. DATA_HI [31:0]
544 */
545/* CONTROL */
546# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0)
547# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28)
548# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30)
549/* CONTROL2a */
550# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0)
551/* CONTROL2b */
552# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2)
553# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25)
554
555#define PACKET3_RUN_CLEANER_SHADER_9_0 0xD7
556/* 1. header
557 * 2. RESERVED [31:0]
558 */
559
560#define PACKET3_RUN_CLEANER_SHADER 0xD2
561/* 1. header
562 * 2. RESERVED [31:0]
563 */
564
565#define VCE_CMD_NO_OP 0x00000000
566#define VCE_CMD_END 0x00000001
567#define VCE_CMD_IB 0x00000002
568#define VCE_CMD_FENCE 0x00000003
569#define VCE_CMD_TRAP 0x00000004
570#define VCE_CMD_IB_AUTO 0x00000005
571#define VCE_CMD_SEMAPHORE 0x00000006
572
573#define VCE_CMD_IB_VM 0x00000102
574#define VCE_CMD_WAIT_GE 0x00000106
575#define VCE_CMD_UPDATE_PTB 0x00000107
576#define VCE_CMD_FLUSH_TLB 0x00000108
577#define VCE_CMD_REG_WRITE 0x00000109
578#define VCE_CMD_REG_WAIT 0x0000010a
579
580#define HEVC_ENC_CMD_NO_OP 0x00000000
581#define HEVC_ENC_CMD_END 0x00000001
582#define HEVC_ENC_CMD_FENCE 0x00000003
583#define HEVC_ENC_CMD_TRAP 0x00000004
584#define HEVC_ENC_CMD_IB_VM 0x00000102
585#define HEVC_ENC_CMD_REG_WRITE 0x00000109
586#define HEVC_ENC_CMD_REG_WAIT 0x0000010a
587
588#endif