tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

kernel / drivers / pinctrl / qcom / pinctrl-sa8775p.c
at v6.18-rc4 1558 lines 46 kB view raw
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2022,2025, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2023, Linaro Limited 5 */ 6 7#include <linux/module.h> 8#include <linux/of.h> 9#include <linux/platform_device.h> 10 11#include "pinctrl-msm.h" 12 13#define REG_BASE 0x100000 14#define REG_SIZE 0x1000 15#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\ 16 { \ 17 .grp = PINCTRL_PINGROUP("gpio" #id, \ 18 gpio##id##_pins, \ 19 ARRAY_SIZE(gpio##id##_pins)), \ 20 .funcs = (int[]){ \ 21 msm_mux_gpio, /* gpio mode */ \ 22 msm_mux_##f1, \ 23 msm_mux_##f2, \ 24 msm_mux_##f3, \ 25 msm_mux_##f4, \ 26 msm_mux_##f5, \ 27 msm_mux_##f6, \ 28 msm_mux_##f7, \ 29 msm_mux_##f8, \ 30 msm_mux_##f9 \ 31 }, \ 32 .nfuncs = 10, \ 33 .ctl_reg = REG_BASE + REG_SIZE * id, \ 34 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 35 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 36 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 37 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 38 .mux_bit = 2, \ 39 .pull_bit = 0, \ 40 .drv_bit = 6, \ 41 .egpio_enable = 12, \ 42 .egpio_present = 11, \ 43 .oe_bit = 9, \ 44 .in_bit = 0, \ 45 .out_bit = 1, \ 46 .intr_enable_bit = 0, \ 47 .intr_status_bit = 0, \ 48 .intr_target_bit = 5, \ 49 .intr_target_width = 4, \ 50 .intr_target_kpss_val = 3, \ 51 .intr_raw_status_bit = 4, \ 52 .intr_polarity_bit = 1, \ 53 .intr_detection_bit = 2, \ 54 .intr_detection_width = 2, \ 55 } 56 57#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 58 { \ 59 .grp = PINCTRL_PINGROUP(#pg_name, \ 60 pg_name##_pins, \ 61 ARRAY_SIZE(pg_name##_pins)), \ 62 .ctl_reg = ctl, \ 63 .io_reg = 0, \ 64 .intr_cfg_reg = 0, \ 65 .intr_status_reg = 0, \ 66 .intr_target_reg = 0, \ 67 .mux_bit = -1, \ 68 .pull_bit = pull, \ 69 .drv_bit = drv, \ 70 .oe_bit = -1, \ 71 .in_bit = -1, \ 72 .out_bit = -1, \ 73 .intr_enable_bit = -1, \ 74 .intr_status_bit = -1, \ 75 .intr_target_bit = -1, \ 76 .intr_raw_status_bit = -1, \ 77 .intr_polarity_bit = -1, \ 78 .intr_detection_bit = -1, \ 79 .intr_detection_width = -1, \ 80 } 81 82#define UFS_RESET(pg_name, offset) \ 83 { \ 84 .grp = PINCTRL_PINGROUP(#pg_name, \ 85 pg_name##_pins, \ 86 ARRAY_SIZE(pg_name##_pins)), \ 87 .ctl_reg = offset, \ 88 .io_reg = offset + 0x4, \ 89 .intr_cfg_reg = 0, \ 90 .intr_status_reg = 0, \ 91 .intr_target_reg = 0, \ 92 .mux_bit = -1, \ 93 .pull_bit = 3, \ 94 .drv_bit = 0, \ 95 .oe_bit = -1, \ 96 .in_bit = -1, \ 97 .out_bit = 0, \ 98 .intr_enable_bit = -1, \ 99 .intr_status_bit = -1, \ 100 .intr_target_bit = -1, \ 101 .intr_raw_status_bit = -1, \ 102 .intr_polarity_bit = -1, \ 103 .intr_detection_bit = -1, \ 104 .intr_detection_width = -1, \ 105 } 106 107#define QUP_I3C(qup_mode, qup_offset) \ 108 { \ 109 .mode = qup_mode, \ 110 .offset = qup_offset, \ 111 } 112 113#define QUP_I3C_6_MODE_OFFSET 0xAF000 114#define QUP_I3C_7_MODE_OFFSET 0xB0000 115#define QUP_I3C_13_MODE_OFFSET 0xB1000 116#define QUP_I3C_14_MODE_OFFSET 0xB2000 117 118static const struct pinctrl_pin_desc sa8775p_pins[] = { 119 PINCTRL_PIN(0, "GPIO_0"), 120 PINCTRL_PIN(1, "GPIO_1"), 121 PINCTRL_PIN(2, "GPIO_2"), 122 PINCTRL_PIN(3, "GPIO_3"), 123 PINCTRL_PIN(4, "GPIO_4"), 124 PINCTRL_PIN(5, "GPIO_5"), 125 PINCTRL_PIN(6, "GPIO_6"), 126 PINCTRL_PIN(7, "GPIO_7"), 127 PINCTRL_PIN(8, "GPIO_8"), 128 PINCTRL_PIN(9, "GPIO_9"), 129 PINCTRL_PIN(10, "GPIO_10"), 130 PINCTRL_PIN(11, "GPIO_11"), 131 PINCTRL_PIN(12, "GPIO_12"), 132 PINCTRL_PIN(13, "GPIO_13"), 133 PINCTRL_PIN(14, "GPIO_14"), 134 PINCTRL_PIN(15, "GPIO_15"), 135 PINCTRL_PIN(16, "GPIO_16"), 136 PINCTRL_PIN(17, "GPIO_17"), 137 PINCTRL_PIN(18, "GPIO_18"), 138 PINCTRL_PIN(19, "GPIO_19"), 139 PINCTRL_PIN(20, "GPIO_20"), 140 PINCTRL_PIN(21, "GPIO_21"), 141 PINCTRL_PIN(22, "GPIO_22"), 142 PINCTRL_PIN(23, "GPIO_23"), 143 PINCTRL_PIN(24, "GPIO_24"), 144 PINCTRL_PIN(25, "GPIO_25"), 145 PINCTRL_PIN(26, "GPIO_26"), 146 PINCTRL_PIN(27, "GPIO_27"), 147 PINCTRL_PIN(28, "GPIO_28"), 148 PINCTRL_PIN(29, "GPIO_29"), 149 PINCTRL_PIN(30, "GPIO_30"), 150 PINCTRL_PIN(31, "GPIO_31"), 151 PINCTRL_PIN(32, "GPIO_32"), 152 PINCTRL_PIN(33, "GPIO_33"), 153 PINCTRL_PIN(34, "GPIO_34"), 154 PINCTRL_PIN(35, "GPIO_35"), 155 PINCTRL_PIN(36, "GPIO_36"), 156 PINCTRL_PIN(37, "GPIO_37"), 157 PINCTRL_PIN(38, "GPIO_38"), 158 PINCTRL_PIN(39, "GPIO_39"), 159 PINCTRL_PIN(40, "GPIO_40"), 160 PINCTRL_PIN(41, "GPIO_41"), 161 PINCTRL_PIN(42, "GPIO_42"), 162 PINCTRL_PIN(43, "GPIO_43"), 163 PINCTRL_PIN(44, "GPIO_44"), 164 PINCTRL_PIN(45, "GPIO_45"), 165 PINCTRL_PIN(46, "GPIO_46"), 166 PINCTRL_PIN(47, "GPIO_47"), 167 PINCTRL_PIN(48, "GPIO_48"), 168 PINCTRL_PIN(49, "GPIO_49"), 169 PINCTRL_PIN(50, "GPIO_50"), 170 PINCTRL_PIN(51, "GPIO_51"), 171 PINCTRL_PIN(52, "GPIO_52"), 172 PINCTRL_PIN(53, "GPIO_53"), 173 PINCTRL_PIN(54, "GPIO_54"), 174 PINCTRL_PIN(55, "GPIO_55"), 175 PINCTRL_PIN(56, "GPIO_56"), 176 PINCTRL_PIN(57, "GPIO_57"), 177 PINCTRL_PIN(58, "GPIO_58"), 178 PINCTRL_PIN(59, "GPIO_59"), 179 PINCTRL_PIN(60, "GPIO_60"), 180 PINCTRL_PIN(61, "GPIO_61"), 181 PINCTRL_PIN(62, "GPIO_62"), 182 PINCTRL_PIN(63, "GPIO_63"), 183 PINCTRL_PIN(64, "GPIO_64"), 184 PINCTRL_PIN(65, "GPIO_65"), 185 PINCTRL_PIN(66, "GPIO_66"), 186 PINCTRL_PIN(67, "GPIO_67"), 187 PINCTRL_PIN(68, "GPIO_68"), 188 PINCTRL_PIN(69, "GPIO_69"), 189 PINCTRL_PIN(70, "GPIO_70"), 190 PINCTRL_PIN(71, "GPIO_71"), 191 PINCTRL_PIN(72, "GPIO_72"), 192 PINCTRL_PIN(73, "GPIO_73"), 193 PINCTRL_PIN(74, "GPIO_74"), 194 PINCTRL_PIN(75, "GPIO_75"), 195 PINCTRL_PIN(76, "GPIO_76"), 196 PINCTRL_PIN(77, "GPIO_77"), 197 PINCTRL_PIN(78, "GPIO_78"), 198 PINCTRL_PIN(79, "GPIO_79"), 199 PINCTRL_PIN(80, "GPIO_80"), 200 PINCTRL_PIN(81, "GPIO_81"), 201 PINCTRL_PIN(82, "GPIO_82"), 202 PINCTRL_PIN(83, "GPIO_83"), 203 PINCTRL_PIN(84, "GPIO_84"), 204 PINCTRL_PIN(85, "GPIO_85"), 205 PINCTRL_PIN(86, "GPIO_86"), 206 PINCTRL_PIN(87, "GPIO_87"), 207 PINCTRL_PIN(88, "GPIO_88"), 208 PINCTRL_PIN(89, "GPIO_89"), 209 PINCTRL_PIN(90, "GPIO_90"), 210 PINCTRL_PIN(91, "GPIO_91"), 211 PINCTRL_PIN(92, "GPIO_92"), 212 PINCTRL_PIN(93, "GPIO_93"), 213 PINCTRL_PIN(94, "GPIO_94"), 214 PINCTRL_PIN(95, "GPIO_95"), 215 PINCTRL_PIN(96, "GPIO_96"), 216 PINCTRL_PIN(97, "GPIO_97"), 217 PINCTRL_PIN(98, "GPIO_98"), 218 PINCTRL_PIN(99, "GPIO_99"), 219 PINCTRL_PIN(100, "GPIO_100"), 220 PINCTRL_PIN(101, "GPIO_101"), 221 PINCTRL_PIN(102, "GPIO_102"), 222 PINCTRL_PIN(103, "GPIO_103"), 223 PINCTRL_PIN(104, "GPIO_104"), 224 PINCTRL_PIN(105, "GPIO_105"), 225 PINCTRL_PIN(106, "GPIO_106"), 226 PINCTRL_PIN(107, "GPIO_107"), 227 PINCTRL_PIN(108, "GPIO_108"), 228 PINCTRL_PIN(109, "GPIO_109"), 229 PINCTRL_PIN(110, "GPIO_110"), 230 PINCTRL_PIN(111, "GPIO_111"), 231 PINCTRL_PIN(112, "GPIO_112"), 232 PINCTRL_PIN(113, "GPIO_113"), 233 PINCTRL_PIN(114, "GPIO_114"), 234 PINCTRL_PIN(115, "GPIO_115"), 235 PINCTRL_PIN(116, "GPIO_116"), 236 PINCTRL_PIN(117, "GPIO_117"), 237 PINCTRL_PIN(118, "GPIO_118"), 238 PINCTRL_PIN(119, "GPIO_119"), 239 PINCTRL_PIN(120, "GPIO_120"), 240 PINCTRL_PIN(121, "GPIO_121"), 241 PINCTRL_PIN(122, "GPIO_122"), 242 PINCTRL_PIN(123, "GPIO_123"), 243 PINCTRL_PIN(124, "GPIO_124"), 244 PINCTRL_PIN(125, "GPIO_125"), 245 PINCTRL_PIN(126, "GPIO_126"), 246 PINCTRL_PIN(127, "GPIO_127"), 247 PINCTRL_PIN(128, "GPIO_128"), 248 PINCTRL_PIN(129, "GPIO_129"), 249 PINCTRL_PIN(130, "GPIO_130"), 250 PINCTRL_PIN(131, "GPIO_131"), 251 PINCTRL_PIN(132, "GPIO_132"), 252 PINCTRL_PIN(133, "GPIO_133"), 253 PINCTRL_PIN(134, "GPIO_134"), 254 PINCTRL_PIN(135, "GPIO_135"), 255 PINCTRL_PIN(136, "GPIO_136"), 256 PINCTRL_PIN(137, "GPIO_137"), 257 PINCTRL_PIN(138, "GPIO_138"), 258 PINCTRL_PIN(139, "GPIO_139"), 259 PINCTRL_PIN(140, "GPIO_140"), 260 PINCTRL_PIN(141, "GPIO_141"), 261 PINCTRL_PIN(142, "GPIO_142"), 262 PINCTRL_PIN(143, "GPIO_143"), 263 PINCTRL_PIN(144, "GPIO_144"), 264 PINCTRL_PIN(145, "GPIO_145"), 265 PINCTRL_PIN(146, "GPIO_146"), 266 PINCTRL_PIN(147, "GPIO_147"), 267 PINCTRL_PIN(148, "GPIO_148"), 268 PINCTRL_PIN(149, "UFS_RESET"), 269 PINCTRL_PIN(150, "SDC1_RCLK"), 270 PINCTRL_PIN(151, "SDC1_CLK"), 271 PINCTRL_PIN(152, "SDC1_CMD"), 272 PINCTRL_PIN(153, "SDC1_DATA"), 273}; 274 275#define DECLARE_MSM_GPIO_PINS(pin) \ 276 static const unsigned int gpio##pin##_pins[] = { pin } 277DECLARE_MSM_GPIO_PINS(0); 278DECLARE_MSM_GPIO_PINS(1); 279DECLARE_MSM_GPIO_PINS(2); 280DECLARE_MSM_GPIO_PINS(3); 281DECLARE_MSM_GPIO_PINS(4); 282DECLARE_MSM_GPIO_PINS(5); 283DECLARE_MSM_GPIO_PINS(6); 284DECLARE_MSM_GPIO_PINS(7); 285DECLARE_MSM_GPIO_PINS(8); 286DECLARE_MSM_GPIO_PINS(9); 287DECLARE_MSM_GPIO_PINS(10); 288DECLARE_MSM_GPIO_PINS(11); 289DECLARE_MSM_GPIO_PINS(12); 290DECLARE_MSM_GPIO_PINS(13); 291DECLARE_MSM_GPIO_PINS(14); 292DECLARE_MSM_GPIO_PINS(15); 293DECLARE_MSM_GPIO_PINS(16); 294DECLARE_MSM_GPIO_PINS(17); 295DECLARE_MSM_GPIO_PINS(18); 296DECLARE_MSM_GPIO_PINS(19); 297DECLARE_MSM_GPIO_PINS(20); 298DECLARE_MSM_GPIO_PINS(21); 299DECLARE_MSM_GPIO_PINS(22); 300DECLARE_MSM_GPIO_PINS(23); 301DECLARE_MSM_GPIO_PINS(24); 302DECLARE_MSM_GPIO_PINS(25); 303DECLARE_MSM_GPIO_PINS(26); 304DECLARE_MSM_GPIO_PINS(27); 305DECLARE_MSM_GPIO_PINS(28); 306DECLARE_MSM_GPIO_PINS(29); 307DECLARE_MSM_GPIO_PINS(30); 308DECLARE_MSM_GPIO_PINS(31); 309DECLARE_MSM_GPIO_PINS(32); 310DECLARE_MSM_GPIO_PINS(33); 311DECLARE_MSM_GPIO_PINS(34); 312DECLARE_MSM_GPIO_PINS(35); 313DECLARE_MSM_GPIO_PINS(36); 314DECLARE_MSM_GPIO_PINS(37); 315DECLARE_MSM_GPIO_PINS(38); 316DECLARE_MSM_GPIO_PINS(39); 317DECLARE_MSM_GPIO_PINS(40); 318DECLARE_MSM_GPIO_PINS(41); 319DECLARE_MSM_GPIO_PINS(42); 320DECLARE_MSM_GPIO_PINS(43); 321DECLARE_MSM_GPIO_PINS(44); 322DECLARE_MSM_GPIO_PINS(45); 323DECLARE_MSM_GPIO_PINS(46); 324DECLARE_MSM_GPIO_PINS(47); 325DECLARE_MSM_GPIO_PINS(48); 326DECLARE_MSM_GPIO_PINS(49); 327DECLARE_MSM_GPIO_PINS(50); 328DECLARE_MSM_GPIO_PINS(51); 329DECLARE_MSM_GPIO_PINS(52); 330DECLARE_MSM_GPIO_PINS(53); 331DECLARE_MSM_GPIO_PINS(54); 332DECLARE_MSM_GPIO_PINS(55); 333DECLARE_MSM_GPIO_PINS(56); 334DECLARE_MSM_GPIO_PINS(57); 335DECLARE_MSM_GPIO_PINS(58); 336DECLARE_MSM_GPIO_PINS(59); 337DECLARE_MSM_GPIO_PINS(60); 338DECLARE_MSM_GPIO_PINS(61); 339DECLARE_MSM_GPIO_PINS(62); 340DECLARE_MSM_GPIO_PINS(63); 341DECLARE_MSM_GPIO_PINS(64); 342DECLARE_MSM_GPIO_PINS(65); 343DECLARE_MSM_GPIO_PINS(66); 344DECLARE_MSM_GPIO_PINS(67); 345DECLARE_MSM_GPIO_PINS(68); 346DECLARE_MSM_GPIO_PINS(69); 347DECLARE_MSM_GPIO_PINS(70); 348DECLARE_MSM_GPIO_PINS(71); 349DECLARE_MSM_GPIO_PINS(72); 350DECLARE_MSM_GPIO_PINS(73); 351DECLARE_MSM_GPIO_PINS(74); 352DECLARE_MSM_GPIO_PINS(75); 353DECLARE_MSM_GPIO_PINS(76); 354DECLARE_MSM_GPIO_PINS(77); 355DECLARE_MSM_GPIO_PINS(78); 356DECLARE_MSM_GPIO_PINS(79); 357DECLARE_MSM_GPIO_PINS(80); 358DECLARE_MSM_GPIO_PINS(81); 359DECLARE_MSM_GPIO_PINS(82); 360DECLARE_MSM_GPIO_PINS(83); 361DECLARE_MSM_GPIO_PINS(84); 362DECLARE_MSM_GPIO_PINS(85); 363DECLARE_MSM_GPIO_PINS(86); 364DECLARE_MSM_GPIO_PINS(87); 365DECLARE_MSM_GPIO_PINS(88); 366DECLARE_MSM_GPIO_PINS(89); 367DECLARE_MSM_GPIO_PINS(90); 368DECLARE_MSM_GPIO_PINS(91); 369DECLARE_MSM_GPIO_PINS(92); 370DECLARE_MSM_GPIO_PINS(93); 371DECLARE_MSM_GPIO_PINS(94); 372DECLARE_MSM_GPIO_PINS(95); 373DECLARE_MSM_GPIO_PINS(96); 374DECLARE_MSM_GPIO_PINS(97); 375DECLARE_MSM_GPIO_PINS(98); 376DECLARE_MSM_GPIO_PINS(99); 377DECLARE_MSM_GPIO_PINS(100); 378DECLARE_MSM_GPIO_PINS(101); 379DECLARE_MSM_GPIO_PINS(102); 380DECLARE_MSM_GPIO_PINS(103); 381DECLARE_MSM_GPIO_PINS(104); 382DECLARE_MSM_GPIO_PINS(105); 383DECLARE_MSM_GPIO_PINS(106); 384DECLARE_MSM_GPIO_PINS(107); 385DECLARE_MSM_GPIO_PINS(108); 386DECLARE_MSM_GPIO_PINS(109); 387DECLARE_MSM_GPIO_PINS(110); 388DECLARE_MSM_GPIO_PINS(111); 389DECLARE_MSM_GPIO_PINS(112); 390DECLARE_MSM_GPIO_PINS(113); 391DECLARE_MSM_GPIO_PINS(114); 392DECLARE_MSM_GPIO_PINS(115); 393DECLARE_MSM_GPIO_PINS(116); 394DECLARE_MSM_GPIO_PINS(117); 395DECLARE_MSM_GPIO_PINS(118); 396DECLARE_MSM_GPIO_PINS(119); 397DECLARE_MSM_GPIO_PINS(120); 398DECLARE_MSM_GPIO_PINS(121); 399DECLARE_MSM_GPIO_PINS(122); 400DECLARE_MSM_GPIO_PINS(123); 401DECLARE_MSM_GPIO_PINS(124); 402DECLARE_MSM_GPIO_PINS(125); 403DECLARE_MSM_GPIO_PINS(126); 404DECLARE_MSM_GPIO_PINS(127); 405DECLARE_MSM_GPIO_PINS(128); 406DECLARE_MSM_GPIO_PINS(129); 407DECLARE_MSM_GPIO_PINS(130); 408DECLARE_MSM_GPIO_PINS(131); 409DECLARE_MSM_GPIO_PINS(132); 410DECLARE_MSM_GPIO_PINS(133); 411DECLARE_MSM_GPIO_PINS(134); 412DECLARE_MSM_GPIO_PINS(135); 413DECLARE_MSM_GPIO_PINS(136); 414DECLARE_MSM_GPIO_PINS(137); 415DECLARE_MSM_GPIO_PINS(138); 416DECLARE_MSM_GPIO_PINS(139); 417DECLARE_MSM_GPIO_PINS(140); 418DECLARE_MSM_GPIO_PINS(141); 419DECLARE_MSM_GPIO_PINS(142); 420DECLARE_MSM_GPIO_PINS(143); 421DECLARE_MSM_GPIO_PINS(144); 422DECLARE_MSM_GPIO_PINS(145); 423DECLARE_MSM_GPIO_PINS(146); 424DECLARE_MSM_GPIO_PINS(147); 425DECLARE_MSM_GPIO_PINS(148); 426 427static const unsigned int ufs_reset_pins[] = { 149 }; 428static const unsigned int sdc1_rclk_pins[] = { 150 }; 429static const unsigned int sdc1_clk_pins[] = { 151 }; 430static const unsigned int sdc1_cmd_pins[] = { 152 }; 431static const unsigned int sdc1_data_pins[] = { 153 }; 432 433enum sa8775p_functions { 434 msm_mux_gpio, 435 msm_mux_atest_char, 436 msm_mux_atest_usb2, 437 msm_mux_audio_ref, 438 msm_mux_cam_mclk, 439 msm_mux_cci_async, 440 msm_mux_cci_i2c, 441 msm_mux_cci_timer0, 442 msm_mux_cci_timer1, 443 msm_mux_cci_timer2, 444 msm_mux_cci_timer3, 445 msm_mux_cci_timer4, 446 msm_mux_cci_timer5, 447 msm_mux_cci_timer6, 448 msm_mux_cci_timer7, 449 msm_mux_cci_timer8, 450 msm_mux_cci_timer9, 451 msm_mux_cri_trng, 452 msm_mux_cri_trng0, 453 msm_mux_cri_trng1, 454 msm_mux_dbg_out, 455 msm_mux_ddr_bist, 456 msm_mux_ddr_pxi0, 457 msm_mux_ddr_pxi1, 458 msm_mux_ddr_pxi2, 459 msm_mux_ddr_pxi3, 460 msm_mux_ddr_pxi4, 461 msm_mux_ddr_pxi5, 462 msm_mux_edp0_hot, 463 msm_mux_edp0_lcd, 464 msm_mux_edp1_hot, 465 msm_mux_edp1_lcd, 466 msm_mux_edp2_hot, 467 msm_mux_edp2_lcd, 468 msm_mux_edp3_hot, 469 msm_mux_edp3_lcd, 470 msm_mux_egpio, 471 msm_mux_emac0_mcg0, 472 msm_mux_emac0_mcg1, 473 msm_mux_emac0_mcg2, 474 msm_mux_emac0_mcg3, 475 msm_mux_emac0_mdc, 476 msm_mux_emac0_mdio, 477 msm_mux_emac0_ptp_aux, 478 msm_mux_emac0_ptp_pps, 479 msm_mux_emac1_mcg0, 480 msm_mux_emac1_mcg1, 481 msm_mux_emac1_mcg2, 482 msm_mux_emac1_mcg3, 483 msm_mux_emac1_mdc, 484 msm_mux_emac1_mdio, 485 msm_mux_emac1_ptp_aux, 486 msm_mux_emac1_ptp_pps, 487 msm_mux_gcc_gp1, 488 msm_mux_gcc_gp2, 489 msm_mux_gcc_gp3, 490 msm_mux_gcc_gp4, 491 msm_mux_gcc_gp5, 492 msm_mux_hs0_mi2s, 493 msm_mux_hs1_mi2s, 494 msm_mux_hs2_mi2s, 495 msm_mux_ibi_i3c, 496 msm_mux_jitter_bist, 497 msm_mux_mdp0_vsync0, 498 msm_mux_mdp0_vsync1, 499 msm_mux_mdp0_vsync2, 500 msm_mux_mdp0_vsync3, 501 msm_mux_mdp0_vsync4, 502 msm_mux_mdp0_vsync5, 503 msm_mux_mdp0_vsync6, 504 msm_mux_mdp0_vsync7, 505 msm_mux_mdp0_vsync8, 506 msm_mux_mdp1_vsync0, 507 msm_mux_mdp1_vsync1, 508 msm_mux_mdp1_vsync2, 509 msm_mux_mdp1_vsync3, 510 msm_mux_mdp1_vsync4, 511 msm_mux_mdp1_vsync5, 512 msm_mux_mdp1_vsync6, 513 msm_mux_mdp1_vsync7, 514 msm_mux_mdp1_vsync8, 515 msm_mux_mdp_vsync, 516 msm_mux_mi2s1_data0, 517 msm_mux_mi2s1_data1, 518 msm_mux_mi2s1_sck, 519 msm_mux_mi2s1_ws, 520 msm_mux_mi2s2_data0, 521 msm_mux_mi2s2_data1, 522 msm_mux_mi2s2_sck, 523 msm_mux_mi2s2_ws, 524 msm_mux_mi2s_mclk0, 525 msm_mux_mi2s_mclk1, 526 msm_mux_pcie0_clkreq, 527 msm_mux_pcie1_clkreq, 528 msm_mux_phase_flag, 529 msm_mux_pll_bist, 530 msm_mux_pll_clk, 531 msm_mux_prng_rosc0, 532 msm_mux_prng_rosc1, 533 msm_mux_prng_rosc2, 534 msm_mux_prng_rosc3, 535 msm_mux_qdss_cti, 536 msm_mux_qdss_gpio, 537 msm_mux_qup0_se0, 538 msm_mux_qup0_se1, 539 msm_mux_qup0_se2, 540 msm_mux_qup0_se3, 541 msm_mux_qup0_se4, 542 msm_mux_qup0_se5, 543 msm_mux_qup1_se0, 544 msm_mux_qup1_se1, 545 msm_mux_qup1_se2, 546 msm_mux_qup1_se3, 547 msm_mux_qup1_se4, 548 msm_mux_qup1_se5, 549 msm_mux_qup1_se6, 550 msm_mux_qup2_se0, 551 msm_mux_qup2_se1, 552 msm_mux_qup2_se2, 553 msm_mux_qup2_se3, 554 msm_mux_qup2_se4, 555 msm_mux_qup2_se5, 556 msm_mux_qup2_se6, 557 msm_mux_qup3_se0, 558 msm_mux_sail_top, 559 msm_mux_sailss_emac0, 560 msm_mux_sailss_ospi, 561 msm_mux_sgmii_phy, 562 msm_mux_tb_trig, 563 msm_mux_tgu_ch0, 564 msm_mux_tgu_ch1, 565 msm_mux_tgu_ch2, 566 msm_mux_tgu_ch3, 567 msm_mux_tgu_ch4, 568 msm_mux_tgu_ch5, 569 msm_mux_tsense_pwm1, 570 msm_mux_tsense_pwm2, 571 msm_mux_tsense_pwm3, 572 msm_mux_tsense_pwm4, 573 msm_mux_usb2phy_ac, 574 msm_mux_vsense_trigger, 575 msm_mux__, 576}; 577 578static const char * const gpio_groups[] = { 579 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 580 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 581 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 582 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 583 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 584 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 585 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 586 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 587 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 588 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 589 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 590 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 591 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 592 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 593 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 594 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 595 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 596 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 597 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", 598 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", 599 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", 600 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", 601 "gpio147", "gpio148", 602}; 603 604static const char * const atest_char_groups[] = { 605 "gpio27", "gpio58", "gpio59", "gpio89", "gpio90", 606}; 607 608static const char * const atest_usb2_groups[] = { 609 "gpio58", "gpio59", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", 610 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", 611 "gpio105", 612}; 613 614static const char * const audio_ref_groups[] = { 615 "gpio113", 616}; 617 618static const char * const cam_mclk_groups[] = { 619 "gpio72", "gpio73", "gpio74", "gpio75", 620}; 621 622static const char * const cci_async_groups[] = { 623 "gpio50", "gpio66", "gpio68", "gpio69", "gpio70", "gpio71", 624}; 625 626static const char * const cci_i2c_groups[] = { 627 "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", 628 "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", 629 "gpio66", "gpio67", 630}; 631 632static const char * const cci_timer0_groups[] = { 633 "gpio68", 634}; 635 636static const char * const cci_timer1_groups[] = { 637 "gpio69", 638}; 639 640static const char * const cci_timer2_groups[] = { 641 "gpio70", 642}; 643 644static const char * const cci_timer3_groups[] = { 645 "gpio71", 646}; 647 648static const char * const cci_timer4_groups[] = { 649 "gpio52", 650}; 651 652static const char * const cci_timer5_groups[] = { 653 "gpio53", 654}; 655 656static const char * const cci_timer6_groups[] = { 657 "gpio54", 658}; 659 660static const char * const cci_timer7_groups[] = { 661 "gpio55", 662}; 663 664static const char * const cci_timer8_groups[] = { 665 "gpio56", 666}; 667 668static const char * const cci_timer9_groups[] = { 669 "gpio57", 670}; 671 672static const char * const cri_trng_groups[] = { 673 "gpio99", 674}; 675 676static const char * const cri_trng0_groups[] = { 677 "gpio97", 678}; 679 680static const char * const cri_trng1_groups[] = { 681 "gpio98", 682}; 683 684static const char * const dbg_out_groups[] = { 685 "gpio144", 686}; 687 688static const char * const ddr_bist_groups[] = { 689 "gpio56", "gpio57", "gpio58", "gpio59", 690}; 691 692static const char * const ddr_pxi0_groups[] = { 693 "gpio33", "gpio34", 694}; 695 696static const char * const ddr_pxi1_groups[] = { 697 "gpio52", "gpio53", 698}; 699 700static const char * const ddr_pxi2_groups[] = { 701 "gpio55", "gpio86", 702}; 703 704static const char * const ddr_pxi3_groups[] = { 705 "gpio87", "gpio88", 706}; 707 708static const char * const ddr_pxi4_groups[] = { 709 "gpio89", "gpio90", 710}; 711 712static const char * const ddr_pxi5_groups[] = { 713 "gpio118", "gpio119", 714}; 715 716static const char * const edp0_hot_groups[] = { 717 "gpio101", 718}; 719 720static const char * const edp0_lcd_groups[] = { 721 "gpio44", 722}; 723 724static const char * const edp1_hot_groups[] = { 725 "gpio102", 726}; 727 728static const char * const edp1_lcd_groups[] = { 729 "gpio45", 730}; 731 732static const char * const edp2_hot_groups[] = { 733 "gpio104", 734}; 735 736static const char * const edp2_lcd_groups[] = { 737 "gpio48", 738}; 739 740static const char * const edp3_hot_groups[] = { 741 "gpio103", 742}; 743 744static const char * const edp3_lcd_groups[] = { 745 "gpio49", 746}; 747 748static const char *const egpio_groups[] = { 749 "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", 750 "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", 751 "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", 752 "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", 753}; 754 755static const char * const emac0_mcg0_groups[] = { 756 "gpio12", 757}; 758 759static const char * const emac0_mcg1_groups[] = { 760 "gpio13", 761}; 762 763static const char * const emac0_mcg2_groups[] = { 764 "gpio14", 765}; 766 767static const char * const emac0_mcg3_groups[] = { 768 "gpio15", 769}; 770 771static const char * const emac0_mdc_groups[] = { 772 "gpio8", 773}; 774 775static const char * const emac0_mdio_groups[] = { 776 "gpio9", 777}; 778 779static const char * const emac0_ptp_aux_groups[] = { 780 "gpio6", "gpio10", "gpio11", "gpio12", 781}; 782 783static const char * const emac0_ptp_pps_groups[] = { 784 "gpio6", "gpio10", "gpio11", "gpio12", 785}; 786 787static const char * const emac1_mcg0_groups[] = { 788 "gpio16", 789 790}; 791 792static const char * const emac1_mcg1_groups[] = { 793 "gpio17", 794}; 795 796static const char * const emac1_mcg2_groups[] = { 797 "gpio18", 798}; 799 800static const char * const emac1_mcg3_groups[] = { 801 "gpio19", 802}; 803 804static const char * const emac1_mdc_groups[] = { 805 "gpio20", 806}; 807 808static const char * const emac1_mdio_groups[] = { 809 "gpio21", 810}; 811 812static const char * const emac1_ptp_aux_groups[] = { 813 "gpio6", "gpio10", "gpio11", "gpio12", 814}; 815 816static const char * const emac1_ptp_pps_groups[] = { 817 "gpio6", "gpio10", "gpio11", "gpio12", 818}; 819 820static const char * const gcc_gp1_groups[] = { 821 "gpio51", "gpio82", 822}; 823 824static const char * const gcc_gp2_groups[] = { 825 "gpio52", "gpio83", 826}; 827 828static const char * const gcc_gp3_groups[] = { 829 "gpio53", "gpio84", 830}; 831 832static const char * const gcc_gp4_groups[] = { 833 "gpio33", "gpio55", 834}; 835 836static const char * const gcc_gp5_groups[] = { 837 "gpio34", "gpio42", 838}; 839 840static const char * const hs0_mi2s_groups[] = { 841 "gpio114", "gpio115", "gpio116", "gpio117", 842}; 843 844static const char * const hs1_mi2s_groups[] = { 845 "gpio118", "gpio119", "gpio120", "gpio121", 846}; 847 848static const char * const hs2_mi2s_groups[] = { 849 "gpio122", "gpio123", "gpio124", "gpio125", 850}; 851 852static const char * const ibi_i3c_groups[] = { 853 "gpio40", "gpio41", "gpio42", "gpio43", "gpio80", "gpio81", "gpio84", 854 "gpio85", 855}; 856 857static const char * const jitter_bist_groups[] = { 858 "gpio86", 859}; 860 861static const char * const mdp0_vsync0_groups[] = { 862 "gpio57", 863}; 864 865static const char * const mdp0_vsync1_groups[] = { 866 "gpio58", 867}; 868 869static const char * const mdp0_vsync2_groups[] = { 870 "gpio59", 871}; 872 873static const char * const mdp0_vsync3_groups[] = { 874 "gpio80", 875}; 876 877static const char * const mdp0_vsync4_groups[] = { 878 "gpio81", 879}; 880 881static const char * const mdp0_vsync5_groups[] = { 882 "gpio91", 883}; 884 885static const char * const mdp0_vsync6_groups[] = { 886 "gpio92", 887}; 888 889static const char * const mdp0_vsync7_groups[] = { 890 "gpio93", 891}; 892 893static const char * const mdp0_vsync8_groups[] = { 894 "gpio94", 895}; 896 897static const char * const mdp1_vsync0_groups[] = { 898 "gpio40", 899}; 900 901static const char * const mdp1_vsync1_groups[] = { 902 "gpio41", 903}; 904 905static const char * const mdp1_vsync2_groups[] = { 906 "gpio42", 907}; 908 909static const char * const mdp1_vsync3_groups[] = { 910 "gpio43", 911}; 912 913static const char * const mdp1_vsync4_groups[] = { 914 "gpio46", 915}; 916 917static const char * const mdp1_vsync5_groups[] = { 918 "gpio47", 919}; 920 921static const char * const mdp1_vsync6_groups[] = { 922 "gpio51", 923}; 924 925static const char * const mdp1_vsync7_groups[] = { 926 "gpio52", 927}; 928 929static const char * const mdp1_vsync8_groups[] = { 930 "gpio50", 931}; 932 933static const char * const mdp_vsync_groups[] = { 934 "gpio82", "gpio83", "gpio84", 935}; 936 937static const char * const mi2s1_data0_groups[] = { 938 "gpio108", 939}; 940 941static const char * const mi2s1_data1_groups[] = { 942 "gpio109", 943}; 944 945static const char * const mi2s1_sck_groups[] = { 946 "gpio106", 947}; 948 949static const char * const mi2s1_ws_groups[] = { 950 "gpio107", 951}; 952 953static const char * const mi2s2_data0_groups[] = { 954 "gpio112", 955}; 956 957static const char * const mi2s2_data1_groups[] = { 958 "gpio113", 959}; 960 961static const char * const mi2s2_sck_groups[] = { 962 "gpio110", 963}; 964 965static const char * const mi2s2_ws_groups[] = { 966 "gpio111", 967}; 968 969static const char * const mi2s_mclk0_groups[] = { 970 "gpio105", 971}; 972 973static const char * const mi2s_mclk1_groups[] = { 974 "gpio117", 975}; 976 977static const char * const pcie0_clkreq_groups[] = { 978 "gpio1", 979}; 980 981static const char * const pcie1_clkreq_groups[] = { 982 "gpio3", 983}; 984 985static const char * const phase_flag_groups[] = { 986 "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", 987 "gpio32", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio56", 988 "gpio57", "gpio98", "gpio99", "gpio106", "gpio107", "gpio108", 989 "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", 990 "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", 991}; 992 993static const char * const pll_bist_groups[] = { 994 "gpio114", 995}; 996 997static const char * const pll_clk_groups[] = { 998 "gpio87", 999}; 1000 1001static const char * const prng_rosc0_groups[] = { 1002 "gpio101", 1003}; 1004 1005static const char * const prng_rosc1_groups[] = { 1006 "gpio102", 1007}; 1008 1009static const char * const prng_rosc2_groups[] = { 1010 "gpio103", 1011}; 1012 1013static const char * const prng_rosc3_groups[] = { 1014 "gpio104", 1015}; 1016 1017static const char * const qdss_cti_groups[] = { 1018 "gpio26", "gpio27", "gpio38", "gpio39", "gpio48", "gpio49", "gpio50", 1019 "gpio51", 1020}; 1021 1022static const char * const qdss_gpio_groups[] = { 1023 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio28", 1024 "gpio29", "gpio30", "gpio31", "gpio60", "gpio61", "gpio62", "gpio63", 1025 "gpio64", "gpio65", "gpio66", "gpio67", "gpio105", "gpio106", "gpio107", 1026 "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", 1027 "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", 1028 "gpio120", "gpio121", "gpio122", 1029}; 1030 1031static const char * const qup0_se0_groups[] = { 1032 "gpio20", "gpio21", "gpio22", "gpio23", 1033}; 1034 1035static const char * const qup0_se1_groups[] = { 1036 "gpio24", "gpio25", "gpio26", "gpio27", 1037}; 1038 1039static const char * const qup0_se2_groups[] = { 1040 "gpio36", "gpio37", "gpio38", "gpio39", 1041}; 1042 1043static const char * const qup0_se3_groups[] = { 1044 "gpio28", "gpio29", "gpio30", "gpio31", 1045}; 1046 1047static const char * const qup0_se4_groups[] = { 1048 "gpio32", "gpio33", "gpio34", "gpio35", 1049}; 1050 1051static const char * const qup0_se5_groups[] = { 1052 "gpio36", "gpio37", "gpio38", "gpio39", 1053}; 1054 1055static const char * const qup1_se0_groups[] = { 1056 "gpio40", "gpio41", "gpio42", "gpio43", 1057}; 1058 1059static const char * const qup1_se1_groups[] = { 1060 "gpio40", "gpio41", "gpio42", "gpio43", 1061}; 1062 1063static const char * const qup1_se2_groups[] = { 1064 "gpio44", "gpio45", "gpio46", "gpio47", 1065}; 1066 1067static const char * const qup1_se3_groups[] = { 1068 "gpio44", "gpio45", "gpio46", "gpio47", 1069}; 1070 1071static const char * const qup1_se4_groups[] = { 1072 "gpio48", "gpio49", "gpio50", "gpio51", 1073}; 1074 1075static const char * const qup1_se5_groups[] = { 1076 "gpio52", "gpio53", "gpio54", "gpio55", 1077}; 1078 1079static const char * const qup1_se6_groups[] = { 1080 "gpio56", "gpio56", "gpio57", "gpio57", 1081}; 1082 1083static const char * const qup2_se0_groups[] = { 1084 "gpio80", "gpio81", "gpio82", "gpio83", 1085}; 1086 1087static const char * const qup2_se1_groups[] = { 1088 "gpio84", "gpio85", "gpio99", "gpio100", 1089}; 1090 1091static const char * const qup2_se2_groups[] = { 1092 "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", 1093}; 1094 1095static const char * const qup2_se3_groups[] = { 1096 "gpio91", "gpio92", "gpio93", "gpio94", 1097}; 1098 1099static const char * const qup2_se4_groups[] = { 1100 "gpio95", "gpio96", "gpio97", "gpio98", 1101}; 1102 1103static const char * const qup2_se5_groups[] = { 1104 "gpio84", "gpio85", "gpio99", "gpio100", 1105}; 1106 1107static const char * const qup2_se6_groups[] = { 1108 "gpio95", "gpio96", "gpio97", "gpio98", 1109}; 1110 1111static const char * const qup3_se0_groups[] = { 1112 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", 1113}; 1114 1115static const char * const sail_top_groups[] = { 1116 "gpio13", "gpio14", "gpio15", "gpio16", 1117}; 1118 1119static const char * const sailss_emac0_groups[] = { 1120 "gpio18", "gpio19", 1121}; 1122 1123static const char * const sailss_ospi_groups[] = { 1124 "gpio18", "gpio19", 1125}; 1126 1127static const char * const sgmii_phy_groups[] = { 1128 "gpio7", "gpio26", 1129}; 1130 1131static const char * const tb_trig_groups[] = { 1132 "gpio17", "gpio17", 1133}; 1134 1135static const char * const tgu_ch0_groups[] = { 1136 "gpio46", 1137}; 1138 1139static const char * const tgu_ch1_groups[] = { 1140 "gpio47", 1141}; 1142 1143static const char * const tgu_ch2_groups[] = { 1144 "gpio36", 1145}; 1146 1147static const char * const tgu_ch3_groups[] = { 1148 "gpio37", 1149}; 1150 1151static const char * const tgu_ch4_groups[] = { 1152 "gpio38", 1153}; 1154 1155static const char * const tgu_ch5_groups[] = { 1156 "gpio39", 1157}; 1158 1159static const char * const tsense_pwm1_groups[] = { 1160 "gpio104", 1161}; 1162 1163static const char * const tsense_pwm2_groups[] = { 1164 "gpio103", 1165}; 1166 1167static const char * const tsense_pwm3_groups[] = { 1168 "gpio102", 1169}; 1170 1171static const char * const tsense_pwm4_groups[] = { 1172 "gpio101", 1173}; 1174 1175static const char * const usb2phy_ac_groups[] = { 1176 "gpio10", "gpio11", "gpio12", 1177}; 1178 1179static const char * const vsense_trigger_groups[] = { 1180 "gpio111", 1181}; 1182 1183static const struct pinfunction sa8775p_functions[] = { 1184 MSM_GPIO_PIN_FUNCTION(gpio), 1185 MSM_PIN_FUNCTION(atest_char), 1186 MSM_PIN_FUNCTION(atest_usb2), 1187 MSM_PIN_FUNCTION(audio_ref), 1188 MSM_PIN_FUNCTION(cam_mclk), 1189 MSM_PIN_FUNCTION(cci_async), 1190 MSM_PIN_FUNCTION(cci_i2c), 1191 MSM_PIN_FUNCTION(cci_timer0), 1192 MSM_PIN_FUNCTION(cci_timer1), 1193 MSM_PIN_FUNCTION(cci_timer2), 1194 MSM_PIN_FUNCTION(cci_timer3), 1195 MSM_PIN_FUNCTION(cci_timer4), 1196 MSM_PIN_FUNCTION(cci_timer5), 1197 MSM_PIN_FUNCTION(cci_timer6), 1198 MSM_PIN_FUNCTION(cci_timer7), 1199 MSM_PIN_FUNCTION(cci_timer8), 1200 MSM_PIN_FUNCTION(cci_timer9), 1201 MSM_PIN_FUNCTION(cri_trng), 1202 MSM_PIN_FUNCTION(cri_trng0), 1203 MSM_PIN_FUNCTION(cri_trng1), 1204 MSM_PIN_FUNCTION(dbg_out), 1205 MSM_PIN_FUNCTION(ddr_bist), 1206 MSM_PIN_FUNCTION(ddr_pxi0), 1207 MSM_PIN_FUNCTION(ddr_pxi1), 1208 MSM_PIN_FUNCTION(ddr_pxi2), 1209 MSM_PIN_FUNCTION(ddr_pxi3), 1210 MSM_PIN_FUNCTION(ddr_pxi4), 1211 MSM_PIN_FUNCTION(ddr_pxi5), 1212 MSM_PIN_FUNCTION(edp0_hot), 1213 MSM_PIN_FUNCTION(edp0_lcd), 1214 MSM_PIN_FUNCTION(edp1_hot), 1215 MSM_PIN_FUNCTION(edp1_lcd), 1216 MSM_PIN_FUNCTION(edp2_hot), 1217 MSM_PIN_FUNCTION(edp2_lcd), 1218 MSM_PIN_FUNCTION(edp3_hot), 1219 MSM_PIN_FUNCTION(edp3_lcd), 1220 MSM_GPIO_PIN_FUNCTION(egpio), 1221 MSM_PIN_FUNCTION(emac0_mcg0), 1222 MSM_PIN_FUNCTION(emac0_mcg1), 1223 MSM_PIN_FUNCTION(emac0_mcg2), 1224 MSM_PIN_FUNCTION(emac0_mcg3), 1225 MSM_PIN_FUNCTION(emac0_mdc), 1226 MSM_PIN_FUNCTION(emac0_mdio), 1227 MSM_PIN_FUNCTION(emac0_ptp_aux), 1228 MSM_PIN_FUNCTION(emac0_ptp_pps), 1229 MSM_PIN_FUNCTION(emac1_mcg0), 1230 MSM_PIN_FUNCTION(emac1_mcg1), 1231 MSM_PIN_FUNCTION(emac1_mcg2), 1232 MSM_PIN_FUNCTION(emac1_mcg3), 1233 MSM_PIN_FUNCTION(emac1_mdc), 1234 MSM_PIN_FUNCTION(emac1_mdio), 1235 MSM_PIN_FUNCTION(emac1_ptp_aux), 1236 MSM_PIN_FUNCTION(emac1_ptp_pps), 1237 MSM_PIN_FUNCTION(gcc_gp1), 1238 MSM_PIN_FUNCTION(gcc_gp2), 1239 MSM_PIN_FUNCTION(gcc_gp3), 1240 MSM_PIN_FUNCTION(gcc_gp4), 1241 MSM_PIN_FUNCTION(gcc_gp5), 1242 MSM_PIN_FUNCTION(hs0_mi2s), 1243 MSM_PIN_FUNCTION(hs1_mi2s), 1244 MSM_PIN_FUNCTION(hs2_mi2s), 1245 MSM_PIN_FUNCTION(ibi_i3c), 1246 MSM_PIN_FUNCTION(jitter_bist), 1247 MSM_PIN_FUNCTION(mdp0_vsync0), 1248 MSM_PIN_FUNCTION(mdp0_vsync1), 1249 MSM_PIN_FUNCTION(mdp0_vsync2), 1250 MSM_PIN_FUNCTION(mdp0_vsync3), 1251 MSM_PIN_FUNCTION(mdp0_vsync4), 1252 MSM_PIN_FUNCTION(mdp0_vsync5), 1253 MSM_PIN_FUNCTION(mdp0_vsync6), 1254 MSM_PIN_FUNCTION(mdp0_vsync7), 1255 MSM_PIN_FUNCTION(mdp0_vsync8), 1256 MSM_PIN_FUNCTION(mdp1_vsync0), 1257 MSM_PIN_FUNCTION(mdp1_vsync1), 1258 MSM_PIN_FUNCTION(mdp1_vsync2), 1259 MSM_PIN_FUNCTION(mdp1_vsync3), 1260 MSM_PIN_FUNCTION(mdp1_vsync4), 1261 MSM_PIN_FUNCTION(mdp1_vsync5), 1262 MSM_PIN_FUNCTION(mdp1_vsync6), 1263 MSM_PIN_FUNCTION(mdp1_vsync7), 1264 MSM_PIN_FUNCTION(mdp1_vsync8), 1265 MSM_PIN_FUNCTION(mdp_vsync), 1266 MSM_PIN_FUNCTION(mi2s1_data0), 1267 MSM_PIN_FUNCTION(mi2s1_data1), 1268 MSM_PIN_FUNCTION(mi2s1_sck), 1269 MSM_PIN_FUNCTION(mi2s1_ws), 1270 MSM_PIN_FUNCTION(mi2s2_data0), 1271 MSM_PIN_FUNCTION(mi2s2_data1), 1272 MSM_PIN_FUNCTION(mi2s2_sck), 1273 MSM_PIN_FUNCTION(mi2s2_ws), 1274 MSM_PIN_FUNCTION(mi2s_mclk0), 1275 MSM_PIN_FUNCTION(mi2s_mclk1), 1276 MSM_PIN_FUNCTION(pcie0_clkreq), 1277 MSM_PIN_FUNCTION(pcie1_clkreq), 1278 MSM_PIN_FUNCTION(phase_flag), 1279 MSM_PIN_FUNCTION(pll_bist), 1280 MSM_PIN_FUNCTION(pll_clk), 1281 MSM_PIN_FUNCTION(prng_rosc0), 1282 MSM_PIN_FUNCTION(prng_rosc1), 1283 MSM_PIN_FUNCTION(prng_rosc2), 1284 MSM_PIN_FUNCTION(prng_rosc3), 1285 MSM_PIN_FUNCTION(qdss_cti), 1286 MSM_PIN_FUNCTION(qdss_gpio), 1287 MSM_PIN_FUNCTION(qup0_se0), 1288 MSM_PIN_FUNCTION(qup0_se1), 1289 MSM_PIN_FUNCTION(qup0_se2), 1290 MSM_PIN_FUNCTION(qup0_se3), 1291 MSM_PIN_FUNCTION(qup0_se4), 1292 MSM_PIN_FUNCTION(qup0_se5), 1293 MSM_PIN_FUNCTION(qup1_se0), 1294 MSM_PIN_FUNCTION(qup1_se1), 1295 MSM_PIN_FUNCTION(qup1_se2), 1296 MSM_PIN_FUNCTION(qup1_se3), 1297 MSM_PIN_FUNCTION(qup1_se4), 1298 MSM_PIN_FUNCTION(qup1_se5), 1299 MSM_PIN_FUNCTION(qup1_se6), 1300 MSM_PIN_FUNCTION(qup2_se0), 1301 MSM_PIN_FUNCTION(qup2_se1), 1302 MSM_PIN_FUNCTION(qup2_se2), 1303 MSM_PIN_FUNCTION(qup2_se3), 1304 MSM_PIN_FUNCTION(qup2_se4), 1305 MSM_PIN_FUNCTION(qup2_se5), 1306 MSM_PIN_FUNCTION(qup2_se6), 1307 MSM_PIN_FUNCTION(qup3_se0), 1308 MSM_PIN_FUNCTION(sail_top), 1309 MSM_PIN_FUNCTION(sailss_emac0), 1310 MSM_PIN_FUNCTION(sailss_ospi), 1311 MSM_PIN_FUNCTION(sgmii_phy), 1312 MSM_PIN_FUNCTION(tb_trig), 1313 MSM_PIN_FUNCTION(tgu_ch0), 1314 MSM_PIN_FUNCTION(tgu_ch1), 1315 MSM_PIN_FUNCTION(tgu_ch2), 1316 MSM_PIN_FUNCTION(tgu_ch3), 1317 MSM_PIN_FUNCTION(tgu_ch4), 1318 MSM_PIN_FUNCTION(tgu_ch5), 1319 MSM_PIN_FUNCTION(tsense_pwm1), 1320 MSM_PIN_FUNCTION(tsense_pwm2), 1321 MSM_PIN_FUNCTION(tsense_pwm3), 1322 MSM_PIN_FUNCTION(tsense_pwm4), 1323 MSM_PIN_FUNCTION(usb2phy_ac), 1324 MSM_PIN_FUNCTION(vsense_trigger), 1325}; 1326 1327/* 1328 * Every pin is maintained as a single group, and missing or non-existing pin 1329 * would be maintained as dummy group to synchronize pin group index with 1330 * pin descriptor registered with pinctrl core. 1331 * Clients would not be able to request these dummy pin groups. 1332 */ 1333static const struct msm_pingroup sa8775p_groups[] = { 1334 [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _), 1335 [1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _), 1336 [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _), 1337 [3] = PINGROUP(3, pcie1_clkreq, _, _, _, _, _, _, _, _), 1338 [4] = PINGROUP(4, _, _, _, _, _, _, _, _, _), 1339 [5] = PINGROUP(5, _, _, _, _, _, _, _, _, _), 1340 [6] = PINGROUP(6, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, 1341 _, _, _, _, _), 1342 [7] = PINGROUP(7, sgmii_phy, _, _, _, _, _, _, _, _), 1343 [8] = PINGROUP(8, emac0_mdc, _, _, _, _, _, _, _, _), 1344 [9] = PINGROUP(9, emac0_mdio, _, _, _, _, _, _, _, _), 1345 [10] = PINGROUP(10, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, 1346 _, _, _, _), 1347 [11] = PINGROUP(11, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, 1348 _, _, _, _), 1349 [12] = PINGROUP(12, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, 1350 emac0_mcg0, _, _, _), 1351 [13] = PINGROUP(13, qup3_se0, emac0_mcg1, _, _, sail_top, _, _, _, _), 1352 [14] = PINGROUP(14, qup3_se0, emac0_mcg2, _, _, sail_top, _, _, _, _), 1353 [15] = PINGROUP(15, qup3_se0, emac0_mcg3, _, _, sail_top, _, _, _, _), 1354 [16] = PINGROUP(16, qup3_se0, emac1_mcg0, _, _, sail_top, _, _, _, _), 1355 [17] = PINGROUP(17, qup3_se0, tb_trig, tb_trig, emac1_mcg1, _, _, _, _, _), 1356 [18] = PINGROUP(18, qup3_se0, emac1_mcg2, _, _, sailss_ospi, sailss_emac0, _, _, _), 1357 [19] = PINGROUP(19, qup3_se0, emac1_mcg3, _, _, sailss_ospi, sailss_emac0, _, _, _), 1358 [20] = PINGROUP(20, qup0_se0, emac1_mdc, qdss_gpio, _, _, _, _, _, _), 1359 [21] = PINGROUP(21, qup0_se0, emac1_mdio, qdss_gpio, _, _, _, _, _, _), 1360 [22] = PINGROUP(22, qup0_se0, qdss_gpio, _, _, _, _, _, _, _), 1361 [23] = PINGROUP(23, qup0_se0, qdss_gpio, _, _, _, _, _, _, _), 1362 [24] = PINGROUP(24, qup0_se1, qdss_gpio, _, _, _, _, _, _, _), 1363 [25] = PINGROUP(25, qup0_se1, phase_flag, _, qdss_gpio, _, _, _, _, _), 1364 [26] = PINGROUP(26, sgmii_phy, qup0_se1, qdss_cti, phase_flag, _, _, _, _, _), 1365 [27] = PINGROUP(27, qup0_se1, qdss_cti, phase_flag, _, atest_char, _, _, _, _), 1366 [28] = PINGROUP(28, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), 1367 [29] = PINGROUP(29, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), 1368 [30] = PINGROUP(30, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), 1369 [31] = PINGROUP(31, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), 1370 [32] = PINGROUP(32, qup0_se4, phase_flag, _, _, _, _, _, _, _), 1371 [33] = PINGROUP(33, qup0_se4, gcc_gp4, _, ddr_pxi0, _, _, _, _, _), 1372 [34] = PINGROUP(34, qup0_se4, gcc_gp5, _, ddr_pxi0, _, _, _, _, _), 1373 [35] = PINGROUP(35, qup0_se4, phase_flag, _, _, _, _, _, _, _), 1374 [36] = PINGROUP(36, qup0_se2, qup0_se5, phase_flag, tgu_ch2, _, _, _, _, _), 1375 [37] = PINGROUP(37, qup0_se2, qup0_se5, phase_flag, tgu_ch3, _, _, _, _, _), 1376 [38] = PINGROUP(38, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch4, _, _, _, _), 1377 [39] = PINGROUP(39, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch5, _, _, _, _), 1378 [40] = PINGROUP(40, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync0, _, _, _, _, _), 1379 [41] = PINGROUP(41, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync1, _, _, _, _, _), 1380 [42] = PINGROUP(42, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync2, gcc_gp5, _, _, _, _), 1381 [43] = PINGROUP(43, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync3, _, _, _, _, _), 1382 [44] = PINGROUP(44, qup1_se2, qup1_se3, edp0_lcd, _, _, _, _, _, _), 1383 [45] = PINGROUP(45, qup1_se2, qup1_se3, edp1_lcd, _, _, _, _, _, _), 1384 [46] = PINGROUP(46, qup1_se3, qup1_se2, mdp1_vsync4, tgu_ch0, _, _, _, _, _), 1385 [47] = PINGROUP(47, qup1_se3, qup1_se2, mdp1_vsync5, tgu_ch1, _, _, _, _, _), 1386 [48] = PINGROUP(48, qup1_se4, qdss_cti, edp2_lcd, _, _, _, _, _, _), 1387 [49] = PINGROUP(49, qup1_se4, qdss_cti, edp3_lcd, _, _, _, _, _, _), 1388 [50] = PINGROUP(50, qup1_se4, cci_async, qdss_cti, mdp1_vsync8, _, _, _, _, _), 1389 [51] = PINGROUP(51, qup1_se4, qdss_cti, mdp1_vsync6, gcc_gp1, _, _, _, _, _), 1390 [52] = PINGROUP(52, qup1_se5, cci_timer4, cci_i2c, mdp1_vsync7, gcc_gp2, _, ddr_pxi1, _, _), 1391 [53] = PINGROUP(53, qup1_se5, cci_timer5, cci_i2c, gcc_gp3, _, ddr_pxi1, _, _, _), 1392 [54] = PINGROUP(54, qup1_se5, cci_timer6, cci_i2c, _, _, _, _, _, _), 1393 [55] = PINGROUP(55, qup1_se5, cci_timer7, cci_i2c, gcc_gp4, _, ddr_pxi2, _, _, _), 1394 [56] = PINGROUP(56, qup1_se6, qup1_se6, cci_timer8, cci_i2c, phase_flag, 1395 ddr_bist, _, _, _), 1396 [57] = PINGROUP(57, qup1_se6, qup1_se6, cci_timer9, cci_i2c, mdp0_vsync0, 1397 phase_flag, ddr_bist, _, _), 1398 [58] = PINGROUP(58, cci_i2c, mdp0_vsync1, ddr_bist, _, atest_usb2, atest_char, _, _, _), 1399 [59] = PINGROUP(59, cci_i2c, mdp0_vsync2, ddr_bist, _, atest_usb2, atest_char, _, _, _), 1400 [60] = PINGROUP(60, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1401 [61] = PINGROUP(61, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1402 [62] = PINGROUP(62, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1403 [63] = PINGROUP(63, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1404 [64] = PINGROUP(64, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1405 [65] = PINGROUP(65, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1406 [66] = PINGROUP(66, cci_i2c, cci_async, qdss_gpio, _, _, _, _, _, _), 1407 [67] = PINGROUP(67, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1408 [68] = PINGROUP(68, cci_timer0, cci_async, _, _, _, _, _, _, _), 1409 [69] = PINGROUP(69, cci_timer1, cci_async, _, _, _, _, _, _, _), 1410 [70] = PINGROUP(70, cci_timer2, cci_async, _, _, _, _, _, _, _), 1411 [71] = PINGROUP(71, cci_timer3, cci_async, _, _, _, _, _, _, _), 1412 [72] = PINGROUP(72, cam_mclk, _, _, _, _, _, _, _, _), 1413 [73] = PINGROUP(73, cam_mclk, _, _, _, _, _, _, _, _), 1414 [74] = PINGROUP(74, cam_mclk, _, _, _, _, _, _, _, _), 1415 [75] = PINGROUP(75, cam_mclk, _, _, _, _, _, _, _, _), 1416 [76] = PINGROUP(76, _, _, _, _, _, _, _, _, _), 1417 [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _), 1418 [78] = PINGROUP(78, _, _, _, _, _, _, _, _, _), 1419 [79] = PINGROUP(79, _, _, _, _, _, _, _, _, _), 1420 [80] = PINGROUP(80, qup2_se0, ibi_i3c, mdp0_vsync3, _, _, _, _, _, _), 1421 [81] = PINGROUP(81, qup2_se0, ibi_i3c, mdp0_vsync4, _, _, _, _, _, _), 1422 [82] = PINGROUP(82, qup2_se0, mdp_vsync, gcc_gp1, _, _, _, _, _, _), 1423 [83] = PINGROUP(83, qup2_se0, mdp_vsync, gcc_gp2, _, _, _, _, _, _), 1424 [84] = PINGROUP(84, qup2_se1, qup2_se5, ibi_i3c, mdp_vsync, gcc_gp3, _, _, _, _), 1425 [85] = PINGROUP(85, qup2_se1, qup2_se5, ibi_i3c, _, _, _, _, _, _), 1426 [86] = PINGROUP(86, qup2_se2, jitter_bist, atest_usb2, ddr_pxi2, _, _, _, _, _), 1427 [87] = PINGROUP(87, qup2_se2, pll_clk, atest_usb2, ddr_pxi3, _, _, _, _, _), 1428 [88] = PINGROUP(88, qup2_se2, _, atest_usb2, ddr_pxi3, _, _, _, _, _), 1429 [89] = PINGROUP(89, qup2_se2, _, atest_usb2, ddr_pxi4, atest_char, _, _, _, _), 1430 [90] = PINGROUP(90, qup2_se2, _, atest_usb2, ddr_pxi4, atest_char, _, _, _, _), 1431 [91] = PINGROUP(91, qup2_se3, mdp0_vsync5, _, atest_usb2, _, _, _, _, _), 1432 [92] = PINGROUP(92, qup2_se3, mdp0_vsync6, _, atest_usb2, _, _, _, _, _), 1433 [93] = PINGROUP(93, qup2_se3, mdp0_vsync7, _, atest_usb2, _, _, _, _, _), 1434 [94] = PINGROUP(94, qup2_se3, mdp0_vsync8, _, atest_usb2, _, _, _, _, _), 1435 [95] = PINGROUP(95, qup2_se4, qup2_se6, _, atest_usb2, _, _, _, _, _), 1436 [96] = PINGROUP(96, qup2_se4, qup2_se6, _, atest_usb2, _, _, _, _, _), 1437 [97] = PINGROUP(97, qup2_se6, qup2_se4, cri_trng0, _, atest_usb2, _, _, _, _), 1438 [98] = PINGROUP(98, qup2_se6, qup2_se4, phase_flag, cri_trng1, _, _, _, _, _), 1439 [99] = PINGROUP(99, qup2_se5, qup2_se1, phase_flag, cri_trng, _, _, _, _, _), 1440 [100] = PINGROUP(100, qup2_se5, qup2_se1, _, _, _, _, _, _, _), 1441 [101] = PINGROUP(101, edp0_hot, prng_rosc0, tsense_pwm4, _, _, _, _, _, _), 1442 [102] = PINGROUP(102, edp1_hot, prng_rosc1, tsense_pwm3, _, _, _, _, _, _), 1443 [103] = PINGROUP(103, edp3_hot, prng_rosc2, tsense_pwm2, _, _, _, _, _, _), 1444 [104] = PINGROUP(104, edp2_hot, prng_rosc3, tsense_pwm1, _, _, _, _, _, _), 1445 [105] = PINGROUP(105, mi2s_mclk0, _, qdss_gpio, atest_usb2, _, _, _, _, _), 1446 [106] = PINGROUP(106, mi2s1_sck, phase_flag, _, qdss_gpio, _, _, _, _, _), 1447 [107] = PINGROUP(107, mi2s1_ws, phase_flag, _, qdss_gpio, _, _, _, _, _), 1448 [108] = PINGROUP(108, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, _, _, _), 1449 [109] = PINGROUP(109, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, _, _, _), 1450 [110] = PINGROUP(110, mi2s2_sck, phase_flag, _, qdss_gpio, _, _, _, _, _), 1451 [111] = PINGROUP(111, mi2s2_ws, phase_flag, _, qdss_gpio, vsense_trigger, _, _, _, _), 1452 [112] = PINGROUP(112, mi2s2_data0, phase_flag, _, qdss_gpio, _, _, _, _, _), 1453 [113] = PINGROUP(113, mi2s2_data1, audio_ref, phase_flag, _, qdss_gpio, _, _, _, _), 1454 [114] = PINGROUP(114, hs0_mi2s, pll_bist, phase_flag, _, qdss_gpio, _, _, _, _), 1455 [115] = PINGROUP(115, hs0_mi2s, _, qdss_gpio, _, _, _, _, _, _), 1456 [116] = PINGROUP(116, hs0_mi2s, _, qdss_gpio, _, _, _, _, _, _), 1457 [117] = PINGROUP(117, hs0_mi2s, mi2s_mclk1, _, qdss_gpio, _, _, _, _, _), 1458 [118] = PINGROUP(118, hs1_mi2s, _, qdss_gpio, ddr_pxi5, _, _, _, _, _), 1459 [119] = PINGROUP(119, hs1_mi2s, _, qdss_gpio, ddr_pxi5, _, _, _, _, _), 1460 [120] = PINGROUP(120, hs1_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), 1461 [121] = PINGROUP(121, hs1_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), 1462 [122] = PINGROUP(122, hs2_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), 1463 [123] = PINGROUP(123, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), 1464 [124] = PINGROUP(124, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), 1465 [125] = PINGROUP(125, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), 1466 [126] = PINGROUP(126, _, _, _, _, _, _, _, _, egpio), 1467 [127] = PINGROUP(127, _, _, _, _, _, _, _, _, egpio), 1468 [128] = PINGROUP(128, _, _, _, _, _, _, _, _, egpio), 1469 [129] = PINGROUP(129, _, _, _, _, _, _, _, _, egpio), 1470 [130] = PINGROUP(130, _, _, _, _, _, _, _, _, egpio), 1471 [131] = PINGROUP(131, _, _, _, _, _, _, _, _, egpio), 1472 [132] = PINGROUP(132, _, _, _, _, _, _, _, _, egpio), 1473 [133] = PINGROUP(133, _, _, _, _, _, _, _, _, egpio), 1474 [134] = PINGROUP(134, _, _, _, _, _, _, _, _, egpio), 1475 [135] = PINGROUP(135, _, _, _, _, _, _, _, _, egpio), 1476 [136] = PINGROUP(136, _, _, _, _, _, _, _, _, egpio), 1477 [137] = PINGROUP(137, _, _, _, _, _, _, _, _, egpio), 1478 [138] = PINGROUP(138, _, _, _, _, _, _, _, _, egpio), 1479 [139] = PINGROUP(139, _, _, _, _, _, _, _, _, egpio), 1480 [140] = PINGROUP(140, _, _, _, _, _, _, _, _, egpio), 1481 [141] = PINGROUP(141, _, _, _, _, _, _, _, _, egpio), 1482 [142] = PINGROUP(142, _, _, _, _, _, _, _, _, egpio), 1483 [143] = PINGROUP(143, _, _, _, _, _, _, _, _, egpio), 1484 [144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, egpio), 1485 [145] = PINGROUP(145, _, _, _, _, _, _, _, _, egpio), 1486 [146] = PINGROUP(146, _, _, _, _, _, _, _, _, egpio), 1487 [147] = PINGROUP(147, _, _, _, _, _, _, _, _, egpio), 1488 [148] = PINGROUP(148, _, _, _, _, _, _, _, _, egpio), 1489 [149] = UFS_RESET(ufs_reset, 0x1a2000), 1490 [150] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x199000, 15, 0), 1491 [151] = SDC_QDSD_PINGROUP(sdc1_clk, 0x199000, 13, 6), 1492 [152] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x199000, 11, 3), 1493 [153] = SDC_QDSD_PINGROUP(sdc1_data, 0x199000, 9, 0), 1494}; 1495 1496static const struct msm_gpio_wakeirq_map sa8775p_pdc_map[] = { 1497 { 0, 169 }, { 1, 174 }, { 2, 170 }, { 3, 175 }, { 4, 171 }, { 5, 173 }, 1498 { 6, 172 }, { 7, 182 }, { 10, 220 }, { 11, 213 }, { 12, 221 }, 1499 { 16, 230 }, { 19, 231 }, { 20, 232 }, { 23, 233 }, { 24, 234 }, 1500 { 26, 223 }, { 27, 235 }, { 28, 209 }, { 29, 176 }, { 30, 200 }, 1501 { 31, 201 }, { 32, 212 }, { 35, 177 }, { 36, 178 }, { 39, 184 }, 1502 { 40, 185 }, { 41, 227 }, { 42, 186 }, { 43, 228 }, { 45, 187 }, 1503 { 47, 188 }, { 48, 194 }, { 51, 195 }, { 52, 196 }, { 55, 197 }, 1504 { 56, 198 }, { 57, 236 }, { 58, 192 }, { 59, 193 }, { 72, 179 }, 1505 { 73, 180 }, { 74, 181 }, { 75, 202 }, { 76, 183 }, { 77, 189 }, 1506 { 78, 190 }, { 79, 191 }, { 80, 199 }, { 83, 204 }, { 84, 205 }, 1507 { 85, 229 }, { 86, 206 }, { 89, 207 }, { 91, 208 }, { 94, 214 }, 1508 { 95, 215 }, { 96, 237 }, { 97, 216 }, { 98, 238 }, { 99, 217 }, 1509 { 100, 239 }, { 105, 219 }, { 106, 210 }, { 107, 211 }, { 108, 222 }, 1510 { 109, 203 }, { 145, 225 }, { 146, 226 }, 1511}; 1512 1513static const struct msm_pinctrl_soc_data sa8775p_pinctrl = { 1514 .pins = sa8775p_pins, 1515 .npins = ARRAY_SIZE(sa8775p_pins), 1516 .functions = sa8775p_functions, 1517 .nfunctions = ARRAY_SIZE(sa8775p_functions), 1518 .groups = sa8775p_groups, 1519 .ngroups = ARRAY_SIZE(sa8775p_groups), 1520 .ngpios = 150, 1521 .wakeirq_map = sa8775p_pdc_map, 1522 .nwakeirq_map = ARRAY_SIZE(sa8775p_pdc_map), 1523 .egpio_func = 9, 1524}; 1525 1526static int sa8775p_pinctrl_probe(struct platform_device *pdev) 1527{ 1528 return msm_pinctrl_probe(pdev, &sa8775p_pinctrl); 1529} 1530 1531static const struct of_device_id sa8775p_pinctrl_of_match[] = { 1532 { .compatible = "qcom,sa8775p-tlmm", }, 1533 { }, 1534}; 1535MODULE_DEVICE_TABLE(of, sa8775p_pinctrl_of_match); 1536 1537static struct platform_driver sa8775p_pinctrl_driver = { 1538 .driver = { 1539 .name = "sa8775p-tlmm", 1540 .of_match_table = sa8775p_pinctrl_of_match, 1541 }, 1542 .probe = sa8775p_pinctrl_probe, 1543}; 1544 1545static int __init sa8775p_pinctrl_init(void) 1546{ 1547 return platform_driver_register(&sa8775p_pinctrl_driver); 1548} 1549arch_initcall(sa8775p_pinctrl_init); 1550 1551static void __exit sa8775p_pinctrl_exit(void) 1552{ 1553 platform_driver_unregister(&sa8775p_pinctrl_driver); 1554} 1555module_exit(sa8775p_pinctrl_exit); 1556 1557MODULE_DESCRIPTION("QTI SA8775P pinctrl driver"); 1558MODULE_LICENSE("GPL");