tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 */
5
6#ifndef _UFS_MEDIATEK_H
7#define _UFS_MEDIATEK_H
8
9#include <linux/bitops.h>
10
11/*
12 * MCQ define and struct
13 */
14#define UFSHCD_MAX_Q_NR 8
15#define MTK_MCQ_INVALID_IRQ 0xFFFF
16
17/* REG_UFS_MMIO_OPT_CTRL_0 160h */
18#define EHS_EN BIT(0)
19#define PFM_IMPV BIT(1)
20#define MCQ_MULTI_INTR_EN BIT(2)
21#define MCQ_CMB_INTR_EN BIT(3)
22#define MCQ_AH8 BIT(4)
23
24#define MCQ_INTR_EN_MSK (MCQ_MULTI_INTR_EN | MCQ_CMB_INTR_EN)
25
26/*
27 * Vendor specific UFSHCI Registers
28 */
29#define REG_UFS_XOUFS_CTRL 0x140
30#define REG_UFS_REFCLK_CTRL 0x144
31#define REG_UFS_MMIO_OPT_CTRL_0 0x160
32#define REG_UFS_EXTREG 0x2100
33#define REG_UFS_MPHYCTRL 0x2200
34#define REG_UFS_MTK_IP_VER 0x2240
35#define REG_UFS_REJECT_MON 0x22AC
36#define REG_UFS_DEBUG_SEL 0x22C0
37#define REG_UFS_PROBE 0x22C8
38#define REG_UFS_DEBUG_SEL_B0 0x22D0
39#define REG_UFS_DEBUG_SEL_B1 0x22D4
40#define REG_UFS_DEBUG_SEL_B2 0x22D8
41#define REG_UFS_DEBUG_SEL_B3 0x22DC
42
43#define REG_UFS_MTK_SQD 0x2800
44#define REG_UFS_MTK_SQIS 0x2814
45#define REG_UFS_MTK_CQD 0x281C
46#define REG_UFS_MTK_CQIS 0x2824
47
48#define REG_UFS_MCQ_STRIDE 0x30
49
50/*
51 * Ref-clk control
52 *
53 * Values for register REG_UFS_REFCLK_CTRL
54 */
55#define REFCLK_RELEASE 0x0
56#define REFCLK_REQUEST BIT(0)
57#define REFCLK_ACK BIT(1)
58
59#define REFCLK_REQ_TIMEOUT_US 3000
60#define REFCLK_DEFAULT_WAIT_US 32
61
62/*
63 * Other attributes
64 */
65#define VS_DEBUGCLOCKENABLE 0xD0A1
66#define VS_SAVEPOWERCONTROL 0xD0A6
67#define VS_UNIPROPOWERDOWNCONTROL 0xD0A8
68
69/*
70 * Vendor specific link state
71 */
72enum {
73 VS_LINK_DISABLED = 0,
74 VS_LINK_DOWN = 1,
75 VS_LINK_UP = 2,
76 VS_LINK_HIBERN8 = 3,
77 VS_LINK_LOST = 4,
78 VS_LINK_CFG = 5,
79};
80
81/*
82 * Vendor specific host controller state
83 */
84enum {
85 VS_HCE_RESET = 0,
86 VS_HCE_BASE = 1,
87 VS_HCE_OOCPR_WAIT = 2,
88 VS_HCE_DME_RESET = 3,
89 VS_HCE_MIDDLE = 4,
90 VS_HCE_DME_ENABLE = 5,
91 VS_HCE_DEFAULTS = 6,
92 VS_HIB_IDLEEN = 7,
93 VS_HIB_ENTER = 8,
94 VS_HIB_ENTER_CONF = 9,
95 VS_HIB_MIDDLE = 10,
96 VS_HIB_WAITTIMER = 11,
97 VS_HIB_EXIT_CONF = 12,
98 VS_HIB_EXIT = 13,
99};
100
101/*
102 * VS_DEBUGCLOCKENABLE
103 */
104enum {
105 TX_SYMBOL_CLK_REQ_FORCE = 5,
106};
107
108/*
109 * VS_SAVEPOWERCONTROL
110 */
111enum {
112 RX_SYMBOL_CLK_GATE_EN = 0,
113 SYS_CLK_GATE_EN = 2,
114 TX_CLK_GATE_EN = 3,
115};
116
117/*
118 * Host capability
119 */
120enum ufs_mtk_host_caps {
121 UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0,
122 UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1,
123 UFS_MTK_CAP_DISABLE_AH8 = 1 << 2,
124 UFS_MTK_CAP_BROKEN_VCC = 1 << 3,
125
126 /*
127 * Override UFS_MTK_CAP_BROKEN_VCC's behavior to
128 * allow vccqx upstream to enter LPM
129 */
130 UFS_MTK_CAP_ALLOW_VCCQX_LPM = 1 << 5,
131 UFS_MTK_CAP_PMC_VIA_FASTAUTO = 1 << 6,
132 UFS_MTK_CAP_TX_SKEW_FIX = 1 << 7,
133 UFS_MTK_CAP_DISABLE_MCQ = 1 << 8,
134 /* Control MTCMOS with RTFF */
135 UFS_MTK_CAP_RTFF_MTCMOS = 1 << 9,
136
137 UFS_MTK_CAP_MCQ_BROKEN_RTC = 1 << 10,
138};
139
140struct ufs_mtk_crypt_cfg {
141 struct regulator *reg_vcore;
142 struct clk *clk_crypt_perf;
143 struct clk *clk_crypt_mux;
144 struct clk *clk_crypt_lp;
145 int vcore_volt;
146};
147
148struct ufs_mtk_clk {
149 struct ufs_clk_info *ufs_sel_clki; /* Mux */
150 struct ufs_clk_info *ufs_sel_max_clki; /* Max src */
151 struct ufs_clk_info *ufs_sel_min_clki; /* Min src */
152 struct ufs_clk_info *ufs_fde_clki; /* Mux */
153 struct ufs_clk_info *ufs_fde_max_clki; /* Max src */
154 struct ufs_clk_info *ufs_fde_min_clki; /* Min src */
155 struct regulator *reg_vcore;
156 int vcore_volt;
157};
158
159struct ufs_mtk_hw_ver {
160 u8 step;
161 u8 minor;
162 u8 major;
163};
164
165struct ufs_mtk_mcq_intr_info {
166 struct ufs_hba *hba;
167 u32 irq;
168 u8 qid;
169};
170
171struct ufs_mtk_host {
172 struct phy *mphy;
173 struct regulator *reg_va09;
174 struct reset_control *hci_reset;
175 struct reset_control *unipro_reset;
176 struct reset_control *crypto_reset;
177 struct reset_control *mphy_reset;
178 struct ufs_hba *hba;
179 struct ufs_mtk_crypt_cfg *crypt;
180 struct ufs_mtk_clk mclk;
181 struct ufs_mtk_hw_ver hw_ver;
182 enum ufs_mtk_host_caps caps;
183 bool mphy_powered_on;
184 bool unipro_lpm;
185 bool ref_clk_enabled;
186 bool clk_scale_up;
187 u16 ref_clk_ungating_wait_us;
188 u16 ref_clk_gating_wait_us;
189 u32 ip_ver;
190 bool legacy_ip_ver;
191
192 bool mcq_set_intr;
193 bool is_mcq_intr_enabled;
194 int mcq_nr_intr;
195 struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR];
196 struct device *phy_dev;
197};
198
199/* MTK delay of autosuspend: 500 ms */
200#define MTK_RPM_AUTOSUSPEND_DELAY_MS 500
201
202/* MTK RTT support number */
203#define MTK_MAX_NUM_RTT 2
204
205/* UFSHCI MTK ip version value */
206enum {
207 /* UFSHCI 3.1 */
208 IP_VER_MT6983 = 0x10360000,
209 IP_VER_MT6878 = 0x10420200,
210
211 /* UFSHCI 4.0 */
212 IP_VER_MT6897 = 0x10440000,
213 IP_VER_MT6989 = 0x10450000,
214 IP_VER_MT6899 = 0x10450100,
215 IP_VER_MT6991_A0 = 0x10460000,
216 IP_VER_MT6991_B0 = 0x10470000,
217 IP_VER_MT6993 = 0x10480000,
218
219 IP_VER_NONE = 0xFFFFFFFF
220};
221
222enum ip_ver_legacy {
223 IP_LEGACY_VER_MT6781 = 0x10380000,
224 IP_LEGACY_VER_MT6879 = 0x10360000,
225 IP_LEGACY_VER_MT6893 = 0x20160706
226};
227
228#endif /* !_UFS_MEDIATEK_H */