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Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/gpio/driver.h>
7#include <linux/module.h>
8#include <linux/of.h>
9#include <linux/of_irq.h>
10#include <linux/platform_device.h>
11#include <linux/regmap.h>
12#include <linux/seq_file.h>
13#include <linux/slab.h>
14#include <linux/string_choices.h>
15#include <linux/types.h>
16
17#include <linux/pinctrl/pinconf-generic.h>
18#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/pinmux.h>
20
21#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
22
23#include "../core.h"
24#include "../pinctrl-utils.h"
25
26#define PMIC_MPP_ADDRESS_RANGE 0x100
27
28/*
29 * Pull Up Values - it indicates whether a pull-up should be
30 * applied for bidirectional mode only. The hardware ignores the
31 * configuration when operating in other modes.
32 */
33#define PMIC_MPP_PULL_UP_0P6KOHM 0
34#define PMIC_MPP_PULL_UP_10KOHM 1
35#define PMIC_MPP_PULL_UP_30KOHM 2
36#define PMIC_MPP_PULL_UP_OPEN 3
37
38/* type registers base address bases */
39#define PMIC_MPP_REG_TYPE 0x4
40#define PMIC_MPP_REG_SUBTYPE 0x5
41
42/* mpp peripheral type and subtype values */
43#define PMIC_MPP_TYPE 0x11
44#define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3
45#define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4
46#define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5
47#define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6
48#define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7
49#define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf
50
51#define PMIC_MPP_REG_RT_STS 0x10
52#define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
53
54/* control register base address bases */
55#define PMIC_MPP_REG_MODE_CTL 0x40
56#define PMIC_MPP_REG_DIG_VIN_CTL 0x41
57#define PMIC_MPP_REG_DIG_PULL_CTL 0x42
58#define PMIC_MPP_REG_DIG_IN_CTL 0x43
59#define PMIC_MPP_REG_EN_CTL 0x46
60#define PMIC_MPP_REG_AOUT_CTL 0x48
61#define PMIC_MPP_REG_AIN_CTL 0x4a
62#define PMIC_MPP_REG_SINK_CTL 0x4c
63
64/* PMIC_MPP_REG_MODE_CTL */
65#define PMIC_MPP_REG_MODE_VALUE_MASK 0x1
66#define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1
67#define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7
68#define PMIC_MPP_REG_MODE_DIR_SHIFT 4
69#define PMIC_MPP_REG_MODE_DIR_MASK 0x7
70
71/* PMIC_MPP_REG_DIG_VIN_CTL */
72#define PMIC_MPP_REG_VIN_SHIFT 0
73#define PMIC_MPP_REG_VIN_MASK 0x7
74
75/* PMIC_MPP_REG_DIG_PULL_CTL */
76#define PMIC_MPP_REG_PULL_SHIFT 0
77#define PMIC_MPP_REG_PULL_MASK 0x7
78
79/* PMIC_MPP_REG_EN_CTL */
80#define PMIC_MPP_REG_MASTER_EN_SHIFT 7
81
82/* PMIC_MPP_REG_AIN_CTL */
83#define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0
84#define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7
85
86#define PMIC_MPP_MODE_DIGITAL_INPUT 0
87#define PMIC_MPP_MODE_DIGITAL_OUTPUT 1
88#define PMIC_MPP_MODE_DIGITAL_BIDIR 2
89#define PMIC_MPP_MODE_ANALOG_BIDIR 3
90#define PMIC_MPP_MODE_ANALOG_INPUT 4
91#define PMIC_MPP_MODE_ANALOG_OUTPUT 5
92#define PMIC_MPP_MODE_CURRENT_SINK 6
93
94#define PMIC_MPP_SELECTOR_NORMAL 0
95#define PMIC_MPP_SELECTOR_PAIRED 1
96#define PMIC_MPP_SELECTOR_DTEST_FIRST 4
97
98#define PMIC_MPP_PHYSICAL_OFFSET 1
99
100/* Qualcomm specific pin configurations */
101#define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1)
102#define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2)
103#define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3)
104#define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4)
105
106/**
107 * struct pmic_mpp_pad - keep current MPP settings
108 * @base: Address base in SPMI device.
109 * @is_enabled: Set to false when MPP should be put in high Z state.
110 * @out_value: Cached pin output value.
111 * @output_enabled: Set to true if MPP output logic is enabled.
112 * @input_enabled: Set to true if MPP input buffer logic is enabled.
113 * @paired: Pin operates in paired mode
114 * @has_pullup: Pin has support to configure pullup
115 * @num_sources: Number of power-sources supported by this MPP.
116 * @power_source: Current power-source used.
117 * @amux_input: Set the source for analog input.
118 * @aout_level: Analog output level
119 * @pullup: Pullup resistor value. Valid in Bidirectional mode only.
120 * @function: See pmic_mpp_functions[].
121 * @drive_strength: Amount of current in sink mode
122 * @dtest: DTEST route selector
123 */
124struct pmic_mpp_pad {
125 u16 base;
126 bool is_enabled;
127 bool out_value;
128 bool output_enabled;
129 bool input_enabled;
130 bool paired;
131 bool has_pullup;
132 unsigned int num_sources;
133 unsigned int power_source;
134 unsigned int amux_input;
135 unsigned int aout_level;
136 unsigned int pullup;
137 unsigned int function;
138 unsigned int drive_strength;
139 unsigned int dtest;
140};
141
142struct pmic_mpp_state {
143 struct device *dev;
144 struct regmap *map;
145 struct pinctrl_dev *ctrl;
146 struct gpio_chip chip;
147};
148
149static const struct pinconf_generic_params pmic_mpp_bindings[] = {
150 {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0},
151 {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0},
152 {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0},
153 {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0},
154};
155
156#ifdef CONFIG_DEBUG_FS
157static const struct pin_config_item pmic_conf_items[] = {
158 PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true),
159 PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true),
160 PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true),
161 PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false),
162};
163#endif
164
165static const char *const pmic_mpp_groups[] = {
166 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8",
167};
168
169#define PMIC_MPP_DIGITAL 0
170#define PMIC_MPP_ANALOG 1
171#define PMIC_MPP_SINK 2
172
173static const char *const pmic_mpp_functions[] = {
174 "digital", "analog", "sink"
175};
176
177static int pmic_mpp_read(struct pmic_mpp_state *state,
178 struct pmic_mpp_pad *pad, unsigned int addr)
179{
180 unsigned int val;
181 int ret;
182
183 ret = regmap_read(state->map, pad->base + addr, &val);
184 if (ret < 0)
185 dev_err(state->dev, "read 0x%x failed\n", addr);
186 else
187 ret = val;
188
189 return ret;
190}
191
192static int pmic_mpp_write(struct pmic_mpp_state *state,
193 struct pmic_mpp_pad *pad, unsigned int addr,
194 unsigned int val)
195{
196 int ret;
197
198 ret = regmap_write(state->map, pad->base + addr, val);
199 if (ret < 0)
200 dev_err(state->dev, "write 0x%x failed\n", addr);
201
202 return ret;
203}
204
205static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev)
206{
207 /* Every PIN is a group */
208 return pctldev->desc->npins;
209}
210
211static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev,
212 unsigned pin)
213{
214 return pctldev->desc->pins[pin].name;
215}
216
217static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev,
218 unsigned pin,
219 const unsigned **pins, unsigned *num_pins)
220{
221 *pins = &pctldev->desc->pins[pin].number;
222 *num_pins = 1;
223 return 0;
224}
225
226static const struct pinctrl_ops pmic_mpp_pinctrl_ops = {
227 .get_groups_count = pmic_mpp_get_groups_count,
228 .get_group_name = pmic_mpp_get_group_name,
229 .get_group_pins = pmic_mpp_get_group_pins,
230 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
231 .dt_free_map = pinctrl_utils_free_map,
232};
233
234static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev)
235{
236 return ARRAY_SIZE(pmic_mpp_functions);
237}
238
239static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev,
240 unsigned function)
241{
242 return pmic_mpp_functions[function];
243}
244
245static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev,
246 unsigned function,
247 const char *const **groups,
248 unsigned *const num_qgroups)
249{
250 *groups = pmic_mpp_groups;
251 *num_qgroups = pctldev->desc->npins;
252 return 0;
253}
254
255static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state,
256 struct pmic_mpp_pad *pad)
257{
258 unsigned int mode;
259 unsigned int sel;
260 unsigned int val;
261 unsigned int en;
262
263 switch (pad->function) {
264 case PMIC_MPP_ANALOG:
265 if (pad->input_enabled && pad->output_enabled)
266 mode = PMIC_MPP_MODE_ANALOG_BIDIR;
267 else if (pad->input_enabled)
268 mode = PMIC_MPP_MODE_ANALOG_INPUT;
269 else
270 mode = PMIC_MPP_MODE_ANALOG_OUTPUT;
271 break;
272 case PMIC_MPP_DIGITAL:
273 if (pad->input_enabled && pad->output_enabled)
274 mode = PMIC_MPP_MODE_DIGITAL_BIDIR;
275 else if (pad->input_enabled)
276 mode = PMIC_MPP_MODE_DIGITAL_INPUT;
277 else
278 mode = PMIC_MPP_MODE_DIGITAL_OUTPUT;
279 break;
280 case PMIC_MPP_SINK:
281 default:
282 mode = PMIC_MPP_MODE_CURRENT_SINK;
283 break;
284 }
285
286 if (pad->dtest)
287 sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1;
288 else if (pad->paired)
289 sel = PMIC_MPP_SELECTOR_PAIRED;
290 else
291 sel = PMIC_MPP_SELECTOR_NORMAL;
292
293 en = !!pad->out_value;
294
295 val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT |
296 sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT |
297 en;
298
299 return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val);
300}
301
302static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function,
303 unsigned pin)
304{
305 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
306 struct pmic_mpp_pad *pad;
307 unsigned int val;
308 int ret;
309
310 pad = pctldev->desc->pins[pin].drv_data;
311
312 pad->function = function;
313
314 ret = pmic_mpp_write_mode_ctl(state, pad);
315 if (ret < 0)
316 return ret;
317
318 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
319
320 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
321}
322
323static const struct pinmux_ops pmic_mpp_pinmux_ops = {
324 .get_functions_count = pmic_mpp_get_functions_count,
325 .get_function_name = pmic_mpp_get_function_name,
326 .get_function_groups = pmic_mpp_get_function_groups,
327 .set_mux = pmic_mpp_set_mux,
328};
329
330static int pmic_mpp_config_get(struct pinctrl_dev *pctldev,
331 unsigned int pin, unsigned long *config)
332{
333 unsigned param = pinconf_to_config_param(*config);
334 struct pmic_mpp_pad *pad;
335 unsigned arg = 0;
336
337 pad = pctldev->desc->pins[pin].drv_data;
338
339 switch (param) {
340 case PIN_CONFIG_BIAS_DISABLE:
341 if (pad->pullup != PMIC_MPP_PULL_UP_OPEN)
342 return -EINVAL;
343 arg = 1;
344 break;
345 case PIN_CONFIG_BIAS_PULL_UP:
346 switch (pad->pullup) {
347 case PMIC_MPP_PULL_UP_0P6KOHM:
348 arg = 600;
349 break;
350 case PMIC_MPP_PULL_UP_10KOHM:
351 arg = 10000;
352 break;
353 case PMIC_MPP_PULL_UP_30KOHM:
354 arg = 30000;
355 break;
356 default:
357 return -EINVAL;
358 }
359 break;
360 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
361 if (pad->is_enabled)
362 return -EINVAL;
363 arg = 1;
364 break;
365 case PIN_CONFIG_POWER_SOURCE:
366 arg = pad->power_source;
367 break;
368 case PIN_CONFIG_INPUT_ENABLE:
369 if (!pad->input_enabled)
370 return -EINVAL;
371 arg = 1;
372 break;
373 case PIN_CONFIG_LEVEL:
374 arg = pad->out_value;
375 break;
376 case PMIC_MPP_CONF_DTEST_SELECTOR:
377 arg = pad->dtest;
378 break;
379 case PMIC_MPP_CONF_AMUX_ROUTE:
380 arg = pad->amux_input;
381 break;
382 case PMIC_MPP_CONF_PAIRED:
383 if (!pad->paired)
384 return -EINVAL;
385 arg = 1;
386 break;
387 case PIN_CONFIG_DRIVE_STRENGTH:
388 arg = pad->drive_strength;
389 break;
390 case PMIC_MPP_CONF_ANALOG_LEVEL:
391 arg = pad->aout_level;
392 break;
393 default:
394 return -EINVAL;
395 }
396
397 /* Convert register value to pinconf value */
398 *config = pinconf_to_config_packed(param, arg);
399 return 0;
400}
401
402static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
403 unsigned long *configs, unsigned nconfs)
404{
405 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
406 struct pmic_mpp_pad *pad;
407 unsigned param, arg;
408 unsigned int val;
409 int i, ret;
410
411 pad = pctldev->desc->pins[pin].drv_data;
412
413 /* Make it possible to enable the pin, by not setting high impedance */
414 pad->is_enabled = true;
415
416 for (i = 0; i < nconfs; i++) {
417 param = pinconf_to_config_param(configs[i]);
418 arg = pinconf_to_config_argument(configs[i]);
419
420 switch (param) {
421 case PIN_CONFIG_BIAS_DISABLE:
422 pad->pullup = PMIC_MPP_PULL_UP_OPEN;
423 break;
424 case PIN_CONFIG_BIAS_PULL_UP:
425 switch (arg) {
426 case 600:
427 pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM;
428 break;
429 case 10000:
430 pad->pullup = PMIC_MPP_PULL_UP_10KOHM;
431 break;
432 case 30000:
433 pad->pullup = PMIC_MPP_PULL_UP_30KOHM;
434 break;
435 default:
436 return -EINVAL;
437 }
438 break;
439 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
440 pad->is_enabled = false;
441 break;
442 case PIN_CONFIG_POWER_SOURCE:
443 if (arg >= pad->num_sources)
444 return -EINVAL;
445 pad->power_source = arg;
446 break;
447 case PIN_CONFIG_INPUT_ENABLE:
448 pad->input_enabled = arg ? true : false;
449 break;
450 case PIN_CONFIG_LEVEL:
451 pad->output_enabled = true;
452 pad->out_value = arg;
453 break;
454 case PMIC_MPP_CONF_DTEST_SELECTOR:
455 pad->dtest = arg;
456 break;
457 case PIN_CONFIG_DRIVE_STRENGTH:
458 pad->drive_strength = arg;
459 break;
460 case PMIC_MPP_CONF_AMUX_ROUTE:
461 if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4)
462 return -EINVAL;
463 pad->amux_input = arg;
464 break;
465 case PMIC_MPP_CONF_ANALOG_LEVEL:
466 pad->aout_level = arg;
467 break;
468 case PMIC_MPP_CONF_PAIRED:
469 pad->paired = !!arg;
470 break;
471 default:
472 return -EINVAL;
473 }
474 }
475
476 val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT;
477
478 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val);
479 if (ret < 0)
480 return ret;
481
482 if (pad->has_pullup) {
483 val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT;
484
485 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL,
486 val);
487 if (ret < 0)
488 return ret;
489 }
490
491 val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK;
492
493 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val);
494 if (ret < 0)
495 return ret;
496
497 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level);
498 if (ret < 0)
499 return ret;
500
501 ret = pmic_mpp_write_mode_ctl(state, pad);
502 if (ret < 0)
503 return ret;
504
505 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_SINK_CTL, pad->drive_strength);
506 if (ret < 0)
507 return ret;
508
509 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
510
511 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
512}
513
514static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
515 struct seq_file *s, unsigned pin)
516{
517 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
518 struct pmic_mpp_pad *pad;
519 int ret;
520
521 static const char *const biases[] = {
522 "0.6kOhm", "10kOhm", "30kOhm", "Disabled"
523 };
524
525 pad = pctldev->desc->pins[pin].drv_data;
526
527 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET);
528
529 if (!pad->is_enabled) {
530 seq_puts(s, " ---");
531 } else {
532
533 if (pad->input_enabled) {
534 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
535 if (ret < 0)
536 return;
537
538 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
539 pad->out_value = ret;
540 }
541
542 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
543 seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]);
544 seq_printf(s, " vin-%d", pad->power_source);
545 seq_printf(s, " %d", pad->aout_level);
546 if (pad->has_pullup)
547 seq_printf(s, " %-8s", biases[pad->pullup]);
548 seq_printf(s, " %-4s", str_high_low(pad->out_value));
549 if (pad->dtest)
550 seq_printf(s, " dtest%d", pad->dtest);
551 if (pad->paired)
552 seq_puts(s, " paired");
553 }
554}
555
556static const struct pinconf_ops pmic_mpp_pinconf_ops = {
557 .is_generic = true,
558 .pin_config_group_get = pmic_mpp_config_get,
559 .pin_config_group_set = pmic_mpp_config_set,
560 .pin_config_group_dbg_show = pmic_mpp_config_dbg_show,
561};
562
563static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin)
564{
565 struct pmic_mpp_state *state = gpiochip_get_data(chip);
566 unsigned long config;
567
568 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
569
570 return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
571}
572
573static int pmic_mpp_direction_output(struct gpio_chip *chip,
574 unsigned pin, int val)
575{
576 struct pmic_mpp_state *state = gpiochip_get_data(chip);
577 unsigned long config;
578
579 config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
580
581 return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
582}
583
584static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin)
585{
586 struct pmic_mpp_state *state = gpiochip_get_data(chip);
587 struct pmic_mpp_pad *pad;
588 int ret;
589
590 pad = state->ctrl->desc->pins[pin].drv_data;
591
592 if (pad->input_enabled) {
593 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
594 if (ret < 0)
595 return ret;
596
597 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
598 }
599
600 return !!pad->out_value;
601}
602
603static int pmic_mpp_set(struct gpio_chip *chip, unsigned int pin, int value)
604{
605 struct pmic_mpp_state *state = gpiochip_get_data(chip);
606 unsigned long config;
607
608 config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
609
610 return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
611}
612
613static int pmic_mpp_of_xlate(struct gpio_chip *chip,
614 const struct of_phandle_args *gpio_desc,
615 u32 *flags)
616{
617 if (chip->of_gpio_n_cells < 2)
618 return -EINVAL;
619
620 if (flags)
621 *flags = gpio_desc->args[1];
622
623 return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET;
624}
625
626static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
627{
628 struct pmic_mpp_state *state = gpiochip_get_data(chip);
629 unsigned i;
630
631 for (i = 0; i < chip->ngpio; i++) {
632 pmic_mpp_config_dbg_show(state->ctrl, s, i);
633 seq_puts(s, "\n");
634 }
635}
636
637static const struct gpio_chip pmic_mpp_gpio_template = {
638 .direction_input = pmic_mpp_direction_input,
639 .direction_output = pmic_mpp_direction_output,
640 .get = pmic_mpp_get,
641 .set = pmic_mpp_set,
642 .request = gpiochip_generic_request,
643 .free = gpiochip_generic_free,
644 .of_xlate = pmic_mpp_of_xlate,
645 .dbg_show = pmic_mpp_dbg_show,
646};
647
648static int pmic_mpp_populate(struct pmic_mpp_state *state,
649 struct pmic_mpp_pad *pad)
650{
651 int type, subtype, val, dir;
652 unsigned int sel;
653
654 type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE);
655 if (type < 0)
656 return type;
657
658 if (type != PMIC_MPP_TYPE) {
659 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
660 type, pad->base);
661 return -ENODEV;
662 }
663
664 subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE);
665 if (subtype < 0)
666 return subtype;
667
668 switch (subtype) {
669 case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT:
670 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT:
671 case PMIC_MPP_SUBTYPE_4CH_NO_SINK:
672 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK:
673 case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC:
674 pad->num_sources = 4;
675 break;
676 case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC:
677 pad->num_sources = 8;
678 break;
679 default:
680 dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n",
681 subtype, pad->base);
682 return -ENODEV;
683 }
684
685 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL);
686 if (val < 0)
687 return val;
688
689 pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK;
690
691 dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT;
692 dir &= PMIC_MPP_REG_MODE_DIR_MASK;
693
694 switch (dir) {
695 case PMIC_MPP_MODE_DIGITAL_INPUT:
696 pad->input_enabled = true;
697 pad->output_enabled = false;
698 pad->function = PMIC_MPP_DIGITAL;
699 break;
700 case PMIC_MPP_MODE_DIGITAL_OUTPUT:
701 pad->input_enabled = false;
702 pad->output_enabled = true;
703 pad->function = PMIC_MPP_DIGITAL;
704 break;
705 case PMIC_MPP_MODE_DIGITAL_BIDIR:
706 pad->input_enabled = true;
707 pad->output_enabled = true;
708 pad->function = PMIC_MPP_DIGITAL;
709 break;
710 case PMIC_MPP_MODE_ANALOG_BIDIR:
711 pad->input_enabled = true;
712 pad->output_enabled = true;
713 pad->function = PMIC_MPP_ANALOG;
714 break;
715 case PMIC_MPP_MODE_ANALOG_INPUT:
716 pad->input_enabled = true;
717 pad->output_enabled = false;
718 pad->function = PMIC_MPP_ANALOG;
719 break;
720 case PMIC_MPP_MODE_ANALOG_OUTPUT:
721 pad->input_enabled = false;
722 pad->output_enabled = true;
723 pad->function = PMIC_MPP_ANALOG;
724 break;
725 case PMIC_MPP_MODE_CURRENT_SINK:
726 pad->input_enabled = false;
727 pad->output_enabled = true;
728 pad->function = PMIC_MPP_SINK;
729 break;
730 default:
731 dev_err(state->dev, "unknown MPP direction\n");
732 return -ENODEV;
733 }
734
735 sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
736 sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK;
737
738 if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST)
739 pad->dtest = sel + 1;
740 else if (sel == PMIC_MPP_SELECTOR_PAIRED)
741 pad->paired = true;
742
743 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL);
744 if (val < 0)
745 return val;
746
747 pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT;
748 pad->power_source &= PMIC_MPP_REG_VIN_MASK;
749
750 if (subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT &&
751 subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK) {
752 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
753 if (val < 0)
754 return val;
755
756 pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT;
757 pad->pullup &= PMIC_MPP_REG_PULL_MASK;
758 pad->has_pullup = true;
759 }
760
761 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL);
762 if (val < 0)
763 return val;
764
765 pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT;
766 pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK;
767
768 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL);
769 if (val < 0)
770 return val;
771
772 pad->drive_strength = val;
773
774 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL);
775 if (val < 0)
776 return val;
777
778 pad->aout_level = val;
779
780 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL);
781 if (val < 0)
782 return val;
783
784 pad->is_enabled = !!val;
785
786 return 0;
787}
788
789static int pmic_mpp_domain_translate(struct irq_domain *domain,
790 struct irq_fwspec *fwspec,
791 unsigned long *hwirq,
792 unsigned int *type)
793{
794 struct pmic_mpp_state *state = container_of(domain->host_data,
795 struct pmic_mpp_state,
796 chip);
797
798 if (fwspec->param_count != 2 ||
799 fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
800 return -EINVAL;
801
802 *hwirq = fwspec->param[0] - PMIC_MPP_PHYSICAL_OFFSET;
803 *type = fwspec->param[1];
804
805 return 0;
806}
807
808static unsigned int pmic_mpp_child_offset_to_irq(struct gpio_chip *chip,
809 unsigned int offset)
810{
811 return offset + PMIC_MPP_PHYSICAL_OFFSET;
812}
813
814static int pmic_mpp_child_to_parent_hwirq(struct gpio_chip *chip,
815 unsigned int child_hwirq,
816 unsigned int child_type,
817 unsigned int *parent_hwirq,
818 unsigned int *parent_type)
819{
820 *parent_hwirq = child_hwirq + 0xc0;
821 *parent_type = child_type;
822
823 return 0;
824}
825
826static void pmic_mpp_irq_mask(struct irq_data *d)
827{
828 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
829
830 irq_chip_mask_parent(d);
831 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
832}
833
834static void pmic_mpp_irq_unmask(struct irq_data *d)
835{
836 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
837
838 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
839 irq_chip_unmask_parent(d);
840}
841
842static const struct irq_chip pmic_mpp_irq_chip = {
843 .name = "spmi-mpp",
844 .irq_ack = irq_chip_ack_parent,
845 .irq_mask = pmic_mpp_irq_mask,
846 .irq_unmask = pmic_mpp_irq_unmask,
847 .irq_set_type = irq_chip_set_type_parent,
848 .irq_set_wake = irq_chip_set_wake_parent,
849 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
850 GPIOCHIP_IRQ_RESOURCE_HELPERS,
851};
852
853static int pmic_mpp_probe(struct platform_device *pdev)
854{
855 struct irq_domain *parent_domain;
856 struct device_node *parent_node;
857 struct device *dev = &pdev->dev;
858 struct pinctrl_pin_desc *pindesc;
859 struct pinctrl_desc *pctrldesc;
860 struct pmic_mpp_pad *pad, *pads;
861 struct pmic_mpp_state *state;
862 struct gpio_irq_chip *girq;
863 int ret, npins, i;
864 u32 reg;
865
866 ret = of_property_read_u32(dev->of_node, "reg", ®);
867 if (ret < 0) {
868 dev_err(dev, "missing base address");
869 return ret;
870 }
871
872 npins = (uintptr_t) device_get_match_data(&pdev->dev);
873
874 BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups));
875
876 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
877 if (!state)
878 return -ENOMEM;
879
880 platform_set_drvdata(pdev, state);
881
882 state->dev = &pdev->dev;
883 state->map = dev_get_regmap(dev->parent, NULL);
884
885 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
886 if (!pindesc)
887 return -ENOMEM;
888
889 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
890 if (!pads)
891 return -ENOMEM;
892
893 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
894 if (!pctrldesc)
895 return -ENOMEM;
896
897 pctrldesc->pctlops = &pmic_mpp_pinctrl_ops;
898 pctrldesc->pmxops = &pmic_mpp_pinmux_ops;
899 pctrldesc->confops = &pmic_mpp_pinconf_ops;
900 pctrldesc->owner = THIS_MODULE;
901 pctrldesc->name = dev_name(dev);
902 pctrldesc->pins = pindesc;
903 pctrldesc->npins = npins;
904
905 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings);
906 pctrldesc->custom_params = pmic_mpp_bindings;
907#ifdef CONFIG_DEBUG_FS
908 pctrldesc->custom_conf_items = pmic_conf_items;
909#endif
910
911 for (i = 0; i < npins; i++, pindesc++) {
912 pad = &pads[i];
913 pindesc->drv_data = pad;
914 pindesc->number = i;
915 pindesc->name = pmic_mpp_groups[i];
916
917 pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE;
918
919 ret = pmic_mpp_populate(state, pad);
920 if (ret < 0)
921 return ret;
922 }
923
924 state->chip = pmic_mpp_gpio_template;
925 state->chip.parent = dev;
926 state->chip.base = -1;
927 state->chip.ngpio = npins;
928 state->chip.label = dev_name(dev);
929 state->chip.of_gpio_n_cells = 2;
930 state->chip.can_sleep = false;
931
932 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
933 if (IS_ERR(state->ctrl))
934 return PTR_ERR(state->ctrl);
935
936 parent_node = of_irq_find_parent(state->dev->of_node);
937 if (!parent_node)
938 return -ENXIO;
939
940 parent_domain = irq_find_host(parent_node);
941 of_node_put(parent_node);
942 if (!parent_domain)
943 return -ENXIO;
944
945 girq = &state->chip.irq;
946 gpio_irq_chip_set_chip(girq, &pmic_mpp_irq_chip);
947 girq->default_type = IRQ_TYPE_NONE;
948 girq->handler = handle_level_irq;
949 girq->fwnode = dev_fwnode(state->dev);
950 girq->parent_domain = parent_domain;
951 girq->child_to_parent_hwirq = pmic_mpp_child_to_parent_hwirq;
952 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_fourcell;
953 girq->child_offset_to_irq = pmic_mpp_child_offset_to_irq;
954 girq->child_irq_domain_ops.translate = pmic_mpp_domain_translate;
955
956 ret = gpiochip_add_data(&state->chip, state);
957 if (ret) {
958 dev_err(state->dev, "can't add gpio chip\n");
959 return ret;
960 }
961
962 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
963 if (ret) {
964 dev_err(dev, "failed to add pin range\n");
965 goto err_range;
966 }
967
968 return 0;
969
970err_range:
971 gpiochip_remove(&state->chip);
972 return ret;
973}
974
975static void pmic_mpp_remove(struct platform_device *pdev)
976{
977 struct pmic_mpp_state *state = platform_get_drvdata(pdev);
978
979 gpiochip_remove(&state->chip);
980}
981
982static const struct of_device_id pmic_mpp_of_match[] = {
983 { .compatible = "qcom,pm8019-mpp", .data = (void *) 6 },
984 { .compatible = "qcom,pm8226-mpp", .data = (void *) 8 },
985 { .compatible = "qcom,pm8841-mpp", .data = (void *) 4 },
986 { .compatible = "qcom,pm8916-mpp", .data = (void *) 4 },
987 { .compatible = "qcom,pm8937-mpp", .data = (void *) 4 },
988 { .compatible = "qcom,pm8941-mpp", .data = (void *) 8 },
989 { .compatible = "qcom,pm8950-mpp", .data = (void *) 4 },
990 { .compatible = "qcom,pmi8950-mpp", .data = (void *) 4 },
991 { .compatible = "qcom,pm8994-mpp", .data = (void *) 8 },
992 { .compatible = "qcom,pma8084-mpp", .data = (void *) 8 },
993 { .compatible = "qcom,pmi8994-mpp", .data = (void *) 4 },
994 { },
995};
996
997MODULE_DEVICE_TABLE(of, pmic_mpp_of_match);
998
999static struct platform_driver pmic_mpp_driver = {
1000 .driver = {
1001 .name = "qcom-spmi-mpp",
1002 .of_match_table = pmic_mpp_of_match,
1003 },
1004 .probe = pmic_mpp_probe,
1005 .remove = pmic_mpp_remove,
1006};
1007
1008module_platform_driver(pmic_mpp_driver);
1009
1010MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1011MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver");
1012MODULE_ALIAS("platform:qcom-spmi-mpp");
1013MODULE_LICENSE("GPL v2");