tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: STMicroelectronics STM32 Reset Clock Controller
8
9maintainers:
10 - Dario Binacchi <dario.binacchi@amarulasolutions.com>
11
12description: |
13 The RCC IP is both a reset and a clock controller.
14 The reset phandle argument is the bit number within the RCC registers bank,
15 starting from RCC base address.
16
17properties:
18 compatible:
19 oneOf:
20 - items:
21 - enum:
22 - st,stm32f42xx-rcc
23 - st,stm32f746-rcc
24 - st,stm32h743-rcc
25 - const: st,stm32-rcc
26 - items:
27 - enum:
28 - st,stm32f469-rcc
29 - const: st,stm32f42xx-rcc
30 - const: st,stm32-rcc
31 - items:
32 - enum:
33 - st,stm32f769-rcc
34 - const: st,stm32f746-rcc
35 - const: st,stm32-rcc
36
37 reg:
38 maxItems: 1
39
40 '#reset-cells':
41 const: 1
42
43 '#clock-cells':
44 enum: [1, 2]
45
46 clocks:
47 minItems: 2
48 maxItems: 3
49
50 st,syscfg:
51 $ref: /schemas/types.yaml#/definitions/phandle
52 description:
53 Phandle to system configuration controller. It can be used to control the
54 power domain circuitry.
55
56 st,ssc-modfreq-hz:
57 description:
58 The modulation frequency for main PLL (in Hz)
59
60 st,ssc-moddepth-permyriad:
61 $ref: /schemas/types.yaml#/definitions/uint32
62 description:
63 The modulation rate for main PLL (in permyriad, i.e. 0.01%)
64 minimum: 25
65 maximum: 200
66
67 st,ssc-modmethod:
68 $ref: /schemas/types.yaml#/definitions/string
69 description:
70 The modulation techniques for main PLL.
71 items:
72 enum:
73 - center-spread
74 - down-spread
75
76required:
77 - compatible
78 - reg
79 - '#reset-cells'
80 - '#clock-cells'
81 - clocks
82 - st,syscfg
83
84allOf:
85 - if:
86 properties:
87 compatible:
88 contains:
89 const: st,stm32h743-rcc
90 then:
91 properties:
92 '#clock-cells':
93 const: 1
94 description: |
95 The clock index for the specified type.
96 clocks:
97 items:
98 - description: high speed external (HSE) clock input
99 - description: low speed external (LSE) clock input
100 - description: Inter-IC sound (I2S) clock input
101 st,ssc-modfreq-hz: false
102 st,ssc-moddepth-permyriad: false
103 st,ssc-modmethod: false
104
105 else:
106 properties:
107 '#clock-cells':
108 const: 2
109 description: |
110 - The first cell is the clock type, possible values are 0 for
111 gated clocks and 1 otherwise.
112 - The second cell is the clock index for the specified type.
113 clocks:
114 items:
115 - description: high speed external (HSE) clock input
116 - description: Inter-IC sound (I2S) clock input
117
118additionalProperties: false
119
120examples:
121 # Reset and Clock Control Module node:
122 - |
123 clock-controller@40023800 {
124 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
125 reg = <0x40023800 0x400>;
126 #clock-cells = <2>;
127 #reset-cells = <1>;
128 clocks = <&clk_hse>, <&clk_i2s_ckin>;
129 st,syscfg = <&pwrcfg>;
130 st,ssc-modfreq-hz = <10000>;
131 st,ssc-moddepth-permyriad = <200>;
132 st,ssc-modmethod = "center-spread";
133 };
134 - |
135 clock-controller@58024400 {
136 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
137 reg = <0x58024400 0x400>;
138 #clock-cells = <1>;
139 #reset-cells = <1>;
140 clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
141 st,syscfg = <&pwrcfg>;
142 };
143
144...