tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#include "xe_wa.h"
7
8#include <drm/drm_managed.h>
9#include <kunit/visibility.h>
10#include <linux/compiler_types.h>
11#include <linux/fault-inject.h>
12
13#include <generated/xe_device_wa_oob.h>
14#include <generated/xe_wa_oob.h>
15
16#include "regs/xe_engine_regs.h"
17#include "regs/xe_gt_regs.h"
18#include "regs/xe_regs.h"
19#include "xe_device_types.h"
20#include "xe_force_wake.h"
21#include "xe_gt.h"
22#include "xe_hw_engine_types.h"
23#include "xe_mmio.h"
24#include "xe_platform_types.h"
25#include "xe_rtp.h"
26#include "xe_sriov.h"
27#include "xe_step.h"
28
29/**
30 * DOC: Hardware workarounds
31 *
32 * Hardware workarounds are register programming documented to be executed in
33 * the driver that fall outside of the normal programming sequences for a
34 * platform. There are some basic categories of workarounds, depending on
35 * how/when they are applied:
36 *
37 * - LRC workarounds: workarounds that touch registers that are
38 * saved/restored to/from the HW context image. The list is emitted (via Load
39 * Register Immediate commands) once when initializing the device and saved in
40 * the default context. That default context is then used on every context
41 * creation to have a "primed golden context", i.e. a context image that
42 * already contains the changes needed to all the registers. See
43 * drivers/gpu/drm/xe/xe_lrc.c for default context handling.
44 *
45 * - Engine workarounds: the list of these WAs is applied whenever the specific
46 * engine is reset. It's also possible that a set of engine classes share a
47 * common power domain and they are reset together. This happens on some
48 * platforms with render and compute engines. In this case (at least) one of
49 * them need to keeep the workaround programming: the approach taken in the
50 * driver is to tie those workarounds to the first compute/render engine that
51 * is registered. When executing with GuC submission, engine resets are
52 * outside of kernel driver control, hence the list of registers involved is
53 * written once, on engine initialization, and then passed to GuC, that
54 * saves/restores their values before/after the reset takes place. See
55 * drivers/gpu/drm/xe/xe_guc_ads.c for reference.
56 *
57 * - GT workarounds: the list of these WAs is applied whenever these registers
58 * revert to their default values: on GPU reset, suspend/resume [1]_, etc.
59 *
60 * - Register whitelist: some workarounds need to be implemented in userspace,
61 * but need to touch privileged registers. The whitelist in the kernel
62 * instructs the hardware to allow the access to happen. From the kernel side,
63 * this is just a special case of a MMIO workaround (as we write the list of
64 * these to/be-whitelisted registers to some special HW registers).
65 *
66 * - Workaround batchbuffers: buffers that get executed automatically by the
67 * hardware on every HW context restore. These buffers are created and
68 * programmed in the default context so the hardware always go through those
69 * programming sequences when switching contexts. The support for workaround
70 * batchbuffers is enabled via these hardware mechanisms:
71 *
72 * #. INDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer
73 * and an offset are provided in the default context, pointing the hardware
74 * to jump to that location when that offset is reached in the context
75 * restore. When a context is being restored, this is executed after the
76 * ring context, in the middle (or beginning) of the engine context image.
77 *
78 * #. BB_PER_CTX_PTR (also known as **post context restore bb**): A
79 * batchbuffer is provided in the default context, pointing the hardware to
80 * a buffer to continue executing after the engine registers are restored
81 * in a context restore sequence.
82 *
83 * Below is the timeline for a context restore sequence:
84 *
85 * .. code::
86 *
87 * INDIRECT_CTX_OFFSET
88 * |----------->|
89 * .------------.------------.-------------.------------.--------------.-----------.
90 * |Ring | Engine | Mid-context | Engine | Post-context | Ring |
91 * |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution |
92 * `------------'------------'-------------'------------'--------------'-----------'
93 *
94 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from
95 * a central place. Those are peppered around the rest of the code, as needed.
96 * There's a central place to control which workarounds are enabled:
97 * drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and
98 * drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds.
99 * These files only record which workarounds are enabled: during early device
100 * initialization those rules are evaluated and recorded by the driver. Then
101 * later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to
102 * implement them.
103 *
104 * .. [1] Technically, some registers are powercontext saved & restored, so they
105 * survive a suspend/resume. In practice, writing them again is not too
106 * costly and simplifies things, so it's the approach taken in the driver.
107 *
108 * .. note::
109 * Hardware workarounds in xe work the same way as in i915, with the
110 * difference of how they are maintained in the code. In xe it uses the
111 * xe_rtp infrastructure so the workarounds can be kept in tables, following
112 * a more declarative approach rather than procedural.
113 */
114
115#undef XE_REG_MCR
116#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
117
118__diag_push();
119__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
120
121static const struct xe_rtp_entry_sr gt_was[] = {
122 { XE_RTP_NAME("14011060649"),
123 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
124 ENGINE_CLASS(VIDEO_DECODE),
125 FUNC(xe_rtp_match_even_instance)),
126 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
127 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
128 },
129 { XE_RTP_NAME("14011059788"),
130 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
131 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
132 },
133 { XE_RTP_NAME("14015795083"),
134 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
135 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
136 },
137
138 /* DG1 */
139
140 { XE_RTP_NAME("1409420604"),
141 XE_RTP_RULES(PLATFORM(DG1)),
142 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
143 },
144 { XE_RTP_NAME("1408615072"),
145 XE_RTP_RULES(PLATFORM(DG1)),
146 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
147 },
148
149 /* DG2 */
150
151 { XE_RTP_NAME("22010523718"),
152 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
153 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
154 },
155 { XE_RTP_NAME("14011006942"),
156 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
157 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
158 },
159 { XE_RTP_NAME("14014830051"),
160 XE_RTP_RULES(PLATFORM(DG2)),
161 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
162 },
163 { XE_RTP_NAME("18018781329"),
164 XE_RTP_RULES(PLATFORM(DG2)),
165 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
166 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
167 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
168 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
169 },
170 { XE_RTP_NAME("1509235366"),
171 XE_RTP_RULES(PLATFORM(DG2)),
172 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
173 INVALIDATION_BROADCAST_MODE_DIS |
174 GLOBAL_INVALIDATION_MODE))
175 },
176
177 /* PVC */
178
179 { XE_RTP_NAME("18018781329"),
180 XE_RTP_RULES(PLATFORM(PVC)),
181 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
182 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
183 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
184 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
185 },
186 { XE_RTP_NAME("16016694945"),
187 XE_RTP_RULES(PLATFORM(PVC)),
188 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
189 },
190
191 /* Xe_LPG */
192
193 { XE_RTP_NAME("14015795083"),
194 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
195 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
196 },
197 { XE_RTP_NAME("14018575942"),
198 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
199 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
200 },
201 { XE_RTP_NAME("22016670082"),
202 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
203 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
204 },
205
206 /* Xe_LPM+ */
207
208 { XE_RTP_NAME("16021867713"),
209 XE_RTP_RULES(MEDIA_VERSION(1300),
210 ENGINE_CLASS(VIDEO_DECODE)),
211 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
212 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
213 },
214 { XE_RTP_NAME("22016670082"),
215 XE_RTP_RULES(MEDIA_VERSION(1300)),
216 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
217 },
218
219 /* Xe2_LPG */
220
221 { XE_RTP_NAME("16020975621"),
222 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
223 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS))
224 },
225 { XE_RTP_NAME("14018157293"),
226 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
227 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0),
228 SET(XEHPC_L3CLOS_MASK(1), ~0),
229 SET(XEHPC_L3CLOS_MASK(2), ~0),
230 SET(XEHPC_L3CLOS_MASK(3), ~0))
231 },
232
233 /* Xe2_LPM */
234
235 { XE_RTP_NAME("14017421178"),
236 XE_RTP_RULES(MEDIA_VERSION(2000),
237 ENGINE_CLASS(VIDEO_DECODE)),
238 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
239 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
240 },
241 { XE_RTP_NAME("16021867713"),
242 XE_RTP_RULES(MEDIA_VERSION(2000),
243 ENGINE_CLASS(VIDEO_DECODE)),
244 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
245 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
246 },
247 { XE_RTP_NAME("14019449301"),
248 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
249 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
250 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
251 },
252
253 /* Xe2_HPG */
254
255 { XE_RTP_NAME("16025250150"),
256 XE_RTP_RULES(GRAPHICS_VERSION(2001)),
257 XE_RTP_ACTIONS(SET(LSN_VC_REG2,
258 LSN_LNI_WGT(1) |
259 LSN_LNE_WGT(1) |
260 LSN_DIM_X_WGT(1) |
261 LSN_DIM_Y_WGT(1) |
262 LSN_DIM_Z_WGT(1)))
263 },
264
265 /* Xe2_HPM */
266
267 { XE_RTP_NAME("16021867713"),
268 XE_RTP_RULES(MEDIA_VERSION(1301),
269 ENGINE_CLASS(VIDEO_DECODE)),
270 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
271 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
272 },
273 { XE_RTP_NAME("14020316580"),
274 XE_RTP_RULES(MEDIA_VERSION(1301)),
275 XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE,
276 VDN_HCP_POWERGATE_ENABLE(0) |
277 VDN_MFXVDENC_POWERGATE_ENABLE(0) |
278 VDN_HCP_POWERGATE_ENABLE(2) |
279 VDN_MFXVDENC_POWERGATE_ENABLE(2))),
280 },
281 { XE_RTP_NAME("14019449301"),
282 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
283 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
284 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
285 },
286
287 /* Xe3_LPG */
288
289 { XE_RTP_NAME("14021871409"),
290 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
291 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
292 },
293
294 /* Xe3_LPM */
295
296 { XE_RTP_NAME("16021867713"),
297 XE_RTP_RULES(MEDIA_VERSION(3000),
298 ENGINE_CLASS(VIDEO_DECODE)),
299 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
300 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
301 },
302 { XE_RTP_NAME("16021865536"),
303 XE_RTP_RULES(MEDIA_VERSION(3000),
304 ENGINE_CLASS(VIDEO_DECODE)),
305 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
306 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
307 },
308 { XE_RTP_NAME("16021865536"),
309 XE_RTP_RULES(MEDIA_VERSION(3002),
310 ENGINE_CLASS(VIDEO_DECODE)),
311 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
312 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
313 },
314 { XE_RTP_NAME("16021867713"),
315 XE_RTP_RULES(MEDIA_VERSION(3002),
316 ENGINE_CLASS(VIDEO_DECODE)),
317 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
318 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
319 },
320 { XE_RTP_NAME("14021486841"),
321 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
322 ENGINE_CLASS(VIDEO_DECODE)),
323 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
324 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
325 },
326};
327
328static const struct xe_rtp_entry_sr engine_was[] = {
329 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
330 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
331 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
332 FF_TESSELATION_DOP_GATE_DISABLE))
333 },
334 { XE_RTP_NAME("1409804808"),
335 XE_RTP_RULES(GRAPHICS_VERSION(1200),
336 ENGINE_CLASS(RENDER),
337 IS_INTEGRATED),
338 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
339 },
340 { XE_RTP_NAME("14010229206, 1409085225"),
341 XE_RTP_RULES(GRAPHICS_VERSION(1200),
342 ENGINE_CLASS(RENDER),
343 IS_INTEGRATED),
344 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
345 },
346 { XE_RTP_NAME("1606931601"),
347 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
348 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
349 },
350 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
351 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
352 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
353 FF_DOP_CLOCK_GATE_DISABLE))
354 },
355 { XE_RTP_NAME("1406941453"),
356 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
357 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
358 },
359 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
360 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
361 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
362 FFSC_PERCTX_PREEMPT_CTRL))
363 },
364
365 /* TGL */
366
367 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
368 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
369 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
370 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
371 RC_SEMA_IDLE_MSG_DISABLE))
372 },
373
374 /* RKL */
375
376 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
377 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
378 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
379 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
380 RC_SEMA_IDLE_MSG_DISABLE))
381 },
382
383 /* ADL-P */
384
385 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
386 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
387 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
388 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
389 RC_SEMA_IDLE_MSG_DISABLE))
390 },
391
392 /* DG2 */
393
394 { XE_RTP_NAME("22013037850"),
395 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
396 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
397 DISABLE_128B_EVICTION_COMMAND_UDW))
398 },
399 { XE_RTP_NAME("22014226127"),
400 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
401 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
402 },
403 { XE_RTP_NAME("18017747507"),
404 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
405 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
406 POLYGON_TRIFAN_LINELOOP_DISABLE))
407 },
408 { XE_RTP_NAME("22012826095, 22013059131"),
409 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
410 FUNC(xe_rtp_match_first_render_or_compute)),
411 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
412 MAXREQS_PER_BANK,
413 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
414 },
415 { XE_RTP_NAME("22013059131"),
416 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
417 FUNC(xe_rtp_match_first_render_or_compute)),
418 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
419 },
420 { XE_RTP_NAME("14015227452"),
421 XE_RTP_RULES(PLATFORM(DG2),
422 FUNC(xe_rtp_match_first_render_or_compute)),
423 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
424 },
425 { XE_RTP_NAME("18028616096"),
426 XE_RTP_RULES(PLATFORM(DG2),
427 FUNC(xe_rtp_match_first_render_or_compute)),
428 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
429 },
430 { XE_RTP_NAME("22015475538"),
431 XE_RTP_RULES(PLATFORM(DG2),
432 FUNC(xe_rtp_match_first_render_or_compute)),
433 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
434 },
435 { XE_RTP_NAME("22012654132"),
436 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
437 FUNC(xe_rtp_match_first_render_or_compute)),
438 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
439 /*
440 * Register can't be read back for verification on
441 * DG2 due to Wa_14012342262
442 */
443 .read_mask = 0))
444 },
445 { XE_RTP_NAME("1509727124"),
446 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
447 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
448 },
449 { XE_RTP_NAME("22012856258"),
450 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
451 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
452 },
453 { XE_RTP_NAME("22010960976, 14013347512"),
454 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
455 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
456 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
457 },
458 { XE_RTP_NAME("14015150844"),
459 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
460 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
461 XE_RTP_NOCHECK))
462 },
463
464 /* PVC */
465
466 { XE_RTP_NAME("22014226127"),
467 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
468 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
469 },
470 { XE_RTP_NAME("14015227452"),
471 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
472 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
473 },
474 { XE_RTP_NAME("18020744125"),
475 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute),
476 ENGINE_CLASS(COMPUTE)),
477 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
478 },
479 { XE_RTP_NAME("14014999345"),
480 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
481 GRAPHICS_STEP(B0, C0)),
482 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
483 },
484
485 /* Xe_LPG */
486
487 { XE_RTP_NAME("14017856879"),
488 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
489 FUNC(xe_rtp_match_first_render_or_compute)),
490 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
491 },
492 { XE_RTP_NAME("14015150844"),
493 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
494 FUNC(xe_rtp_match_first_render_or_compute)),
495 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
496 XE_RTP_NOCHECK))
497 },
498 { XE_RTP_NAME("14020495402"),
499 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
500 FUNC(xe_rtp_match_first_render_or_compute)),
501 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING))
502 },
503
504 /* Xe2_LPG */
505
506 { XE_RTP_NAME("18032247524"),
507 XE_RTP_RULES(GRAPHICS_VERSION(2004),
508 FUNC(xe_rtp_match_first_render_or_compute)),
509 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
510 },
511 { XE_RTP_NAME("16018712365"),
512 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
513 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
514 },
515 { XE_RTP_NAME("14018957109"),
516 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
517 FUNC(xe_rtp_match_first_render_or_compute)),
518 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE))
519 },
520 { XE_RTP_NAME("14020338487"),
521 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
522 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
523 },
524 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */
525 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
526 FUNC(xe_rtp_match_first_render_or_compute)),
527 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
528 },
529 { XE_RTP_NAME("14019322943"),
530 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
531 FUNC(xe_rtp_match_first_render_or_compute)),
532 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))
533 },
534 { XE_RTP_NAME("14018471104"),
535 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
536 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
537 },
538 /*
539 * These two workarounds are the same, just applying to different
540 * engines. Although Wa_18032095049 (for the RCS) isn't required on
541 * all steppings, disabling these reports has no impact for our
542 * driver or the GuC, so we go ahead and treat it the same as
543 * Wa_16021639441 which does apply to all steppings.
544 */
545 { XE_RTP_NAME("18032095049, 16021639441"),
546 XE_RTP_RULES(GRAPHICS_VERSION(2004)),
547 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
548 GHWSP_CSB_REPORT_DIS |
549 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
550 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
551 },
552 { XE_RTP_NAME("16018610683"),
553 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
554 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
555 },
556 { XE_RTP_NAME("14021402888"),
557 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
558 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
559 },
560 { XE_RTP_NAME("13012615864"),
561 XE_RTP_RULES(GRAPHICS_VERSION(2004),
562 FUNC(xe_rtp_match_first_render_or_compute)),
563 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
564 },
565
566 /* Xe2_HPG */
567
568 { XE_RTP_NAME("16018712365"),
569 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
570 FUNC(xe_rtp_match_first_render_or_compute)),
571 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
572 },
573 { XE_RTP_NAME("16018737384"),
574 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
575 FUNC(xe_rtp_match_first_render_or_compute)),
576 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
577 },
578 { XE_RTP_NAME("14019988906"),
579 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
580 FUNC(xe_rtp_match_first_render_or_compute)),
581 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
582 },
583 { XE_RTP_NAME("14019877138"),
584 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
585 FUNC(xe_rtp_match_first_render_or_compute)),
586 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
587 },
588 { XE_RTP_NAME("14020338487"),
589 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
590 FUNC(xe_rtp_match_first_render_or_compute)),
591 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
592 },
593 { XE_RTP_NAME("18032247524"),
594 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
595 FUNC(xe_rtp_match_first_render_or_compute)),
596 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
597 },
598 { XE_RTP_NAME("14018471104"),
599 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
600 FUNC(xe_rtp_match_first_render_or_compute)),
601 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
602 },
603 /*
604 * Although this workaround isn't required for the RCS, disabling these
605 * reports has no impact for our driver or the GuC, so we go ahead and
606 * apply this to all engines for simplicity.
607 */
608 { XE_RTP_NAME("16021639441"),
609 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002)),
610 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
611 GHWSP_CSB_REPORT_DIS |
612 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
613 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
614 },
615 { XE_RTP_NAME("14019811474"),
616 XE_RTP_RULES(GRAPHICS_VERSION(2001),
617 FUNC(xe_rtp_match_first_render_or_compute)),
618 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
619 },
620 { XE_RTP_NAME("14021402888"),
621 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
622 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
623 },
624 { XE_RTP_NAME("14021821874, 14022954250"),
625 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
626 FUNC(xe_rtp_match_first_render_or_compute)),
627 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
628 },
629 { XE_RTP_NAME("13012615864"),
630 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
631 FUNC(xe_rtp_match_first_render_or_compute)),
632 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
633 },
634 { XE_RTP_NAME("18041344222"),
635 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
636 FUNC(xe_rtp_match_first_render_or_compute),
637 FUNC(xe_rtp_match_not_sriov_vf),
638 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
639 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
640 },
641
642 /* Xe2_LPM */
643
644 { XE_RTP_NAME("16021639441"),
645 XE_RTP_RULES(MEDIA_VERSION(2000)),
646 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
647 GHWSP_CSB_REPORT_DIS |
648 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
649 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
650 },
651
652 /* Xe2_HPM */
653
654 { XE_RTP_NAME("16021639441"),
655 XE_RTP_RULES(MEDIA_VERSION(1301)),
656 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
657 GHWSP_CSB_REPORT_DIS |
658 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
659 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
660 },
661
662 /* Xe3_LPG */
663
664 { XE_RTP_NAME("14021402888"),
665 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
666 FUNC(xe_rtp_match_first_render_or_compute)),
667 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
668 },
669 { XE_RTP_NAME("18034896535"),
670 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
671 FUNC(xe_rtp_match_first_render_or_compute)),
672 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
673 },
674 { XE_RTP_NAME("16024792527"),
675 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
676 FUNC(xe_rtp_match_first_render_or_compute)),
677 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER,
678 SMP_FORCE_128B_OVERFETCH))
679 },
680 { XE_RTP_NAME("14023061436"),
681 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
682 FUNC(xe_rtp_match_first_render_or_compute)),
683 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
684 },
685 { XE_RTP_NAME("13012615864"),
686 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR,
687 GRAPHICS_VERSION(3003),
688 FUNC(xe_rtp_match_first_render_or_compute)),
689 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
690 },
691 { XE_RTP_NAME("16023105232"),
692 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR,
693 GRAPHICS_VERSION_RANGE(2001, 3001)),
694 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
695 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
696 },
697 { XE_RTP_NAME("14021402888"),
698 XE_RTP_RULES(GRAPHICS_VERSION(3003), FUNC(xe_rtp_match_first_render_or_compute)),
699 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
700 },
701 { XE_RTP_NAME("18041344222"),
702 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
703 FUNC(xe_rtp_match_first_render_or_compute),
704 FUNC(xe_rtp_match_not_sriov_vf),
705 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
706 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
707 },
708};
709
710static const struct xe_rtp_entry_sr lrc_was[] = {
711 { XE_RTP_NAME("16011163337"),
712 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
713 /* read verification is ignored due to 1608008084. */
714 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
715 FF_MODE2_GS_TIMER_MASK,
716 FF_MODE2_GS_TIMER_224))
717 },
718 { XE_RTP_NAME("1604555607"),
719 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
720 /* read verification is ignored due to 1608008084. */
721 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
722 FF_MODE2_TDS_TIMER_MASK,
723 FF_MODE2_TDS_TIMER_128))
724 },
725 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
726 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
727 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
728 DISABLE_CPS_AWARE_COLOR_PIPE))
729 },
730 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
731 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
732 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
733 PREEMPT_GPGPU_LEVEL_MASK,
734 PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
735 },
736 { XE_RTP_NAME("1806527549"),
737 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
738 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
739 },
740 { XE_RTP_NAME("1606376872"),
741 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
742 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
743 },
744
745 /* DG1 */
746
747 { XE_RTP_NAME("1409044764"),
748 XE_RTP_RULES(PLATFORM(DG1)),
749 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
750 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
751 },
752 { XE_RTP_NAME("22010493298"),
753 XE_RTP_RULES(PLATFORM(DG1)),
754 XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
755 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
756 },
757
758 /* DG2 */
759
760 { XE_RTP_NAME("16013271637"),
761 XE_RTP_RULES(PLATFORM(DG2)),
762 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
763 MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
764 },
765 { XE_RTP_NAME("14014947963"),
766 XE_RTP_RULES(PLATFORM(DG2)),
767 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
768 PREEMPTION_VERTEX_COUNT,
769 0x4000))
770 },
771 { XE_RTP_NAME("18018764978"),
772 XE_RTP_RULES(PLATFORM(DG2)),
773 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
774 SCOREBOARD_STALL_FLUSH_CONTROL))
775 },
776 { XE_RTP_NAME("18019271663"),
777 XE_RTP_RULES(PLATFORM(DG2)),
778 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
779 },
780 { XE_RTP_NAME("14019877138"),
781 XE_RTP_RULES(PLATFORM(DG2)),
782 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
783 },
784
785 /* PVC */
786
787 { XE_RTP_NAME("16017236439"),
788 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
789 FUNC(xe_rtp_match_even_instance)),
790 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
791 BCS_SWCTRL_DISABLE_256B,
792 XE_RTP_ACTION_FLAG(ENGINE_BASE))),
793 },
794
795 /* Xe_LPG */
796
797 { XE_RTP_NAME("18019271663"),
798 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
799 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
800 },
801 { XE_RTP_NAME("14019877138"),
802 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
803 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
804 },
805
806 /* Xe2_LPG */
807
808 { XE_RTP_NAME("16020518922"),
809 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
810 ENGINE_CLASS(RENDER)),
811 XE_RTP_ACTIONS(SET(FF_MODE,
812 DIS_TE_AUTOSTRIP |
813 DIS_MESH_PARTIAL_AUTOSTRIP |
814 DIS_MESH_AUTOSTRIP),
815 SET(VFLSKPD,
816 DIS_PARTIAL_AUTOSTRIP |
817 DIS_AUTOSTRIP))
818 },
819 { XE_RTP_NAME("14019386621"),
820 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
821 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
822 },
823 { XE_RTP_NAME("14019877138"),
824 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
825 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
826 },
827 { XE_RTP_NAME("14020013138"),
828 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
829 ENGINE_CLASS(RENDER)),
830 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
831 },
832 { XE_RTP_NAME("14019988906"),
833 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
834 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
835 },
836 { XE_RTP_NAME("16020183090"),
837 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
838 ENGINE_CLASS(RENDER)),
839 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
840 },
841 { XE_RTP_NAME("18033852989"),
842 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
843 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
844 },
845 { XE_RTP_NAME("14021567978"),
846 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
847 ENGINE_CLASS(RENDER)),
848 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
849 },
850 { XE_RTP_NAME("14020756599"),
851 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR,
852 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)),
853 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
854 },
855 { XE_RTP_NAME("14021490052"),
856 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
857 XE_RTP_ACTIONS(SET(FF_MODE,
858 DIS_MESH_PARTIAL_AUTOSTRIP |
859 DIS_MESH_AUTOSTRIP),
860 SET(VFLSKPD,
861 DIS_PARTIAL_AUTOSTRIP |
862 DIS_AUTOSTRIP))
863 },
864 { XE_RTP_NAME("15016589081"),
865 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
866 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
867 },
868
869 /* Xe2_HPG */
870 { XE_RTP_NAME("15010599737"),
871 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
872 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
873 },
874 { XE_RTP_NAME("14019386621"),
875 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
876 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
877 },
878 { XE_RTP_NAME("14020756599"),
879 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
880 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
881 },
882 { XE_RTP_NAME("14021490052"),
883 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
884 XE_RTP_ACTIONS(SET(FF_MODE,
885 DIS_MESH_PARTIAL_AUTOSTRIP |
886 DIS_MESH_AUTOSTRIP),
887 SET(VFLSKPD,
888 DIS_PARTIAL_AUTOSTRIP |
889 DIS_AUTOSTRIP))
890 },
891 { XE_RTP_NAME("15016589081"),
892 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
893 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
894 },
895 { XE_RTP_NAME("22021007897"),
896 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
897 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
898 },
899 { XE_RTP_NAME("18033852989"),
900 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
901 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
902 },
903
904 /* Xe3_LPG */
905 { XE_RTP_NAME("14021490052"),
906 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
907 ENGINE_CLASS(RENDER)),
908 XE_RTP_ACTIONS(SET(FF_MODE,
909 DIS_MESH_PARTIAL_AUTOSTRIP |
910 DIS_MESH_AUTOSTRIP),
911 SET(VFLSKPD,
912 DIS_PARTIAL_AUTOSTRIP |
913 DIS_AUTOSTRIP))
914 },
915 { XE_RTP_NAME("22021007897"),
916 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3003), ENGINE_CLASS(RENDER)),
917 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
918 },
919};
920
921static __maybe_unused const struct xe_rtp_entry oob_was[] = {
922#include <generated/xe_wa_oob.c>
923 {}
924};
925
926static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
927
928static __maybe_unused const struct xe_rtp_entry device_oob_was[] = {
929#include <generated/xe_device_wa_oob.c>
930 {}
931};
932
933static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT);
934
935__diag_pop();
936
937/**
938 * xe_wa_process_device_oob - process OOB workaround table
939 * @xe: device instance to process workarounds for
940 *
941 * process OOB workaround table for this device, marking in @xe the
942 * workarounds that are active.
943 */
944
945void xe_wa_process_device_oob(struct xe_device *xe)
946{
947 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe);
948
949 xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was));
950
951 xe->wa_active.oob_initialized = true;
952 xe_rtp_process(&ctx, device_oob_was);
953}
954
955/**
956 * xe_wa_process_gt_oob - process GT OOB workaround table
957 * @gt: GT instance to process workarounds for
958 *
959 * Process OOB workaround table for this platform, marking in @gt the
960 * workarounds that are active.
961 */
962void xe_wa_process_gt_oob(struct xe_gt *gt)
963{
964 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
965
966 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
967 ARRAY_SIZE(oob_was));
968 gt->wa_active.oob_initialized = true;
969 xe_rtp_process(&ctx, oob_was);
970}
971
972/**
973 * xe_wa_process_gt - process GT workaround table
974 * @gt: GT instance to process workarounds for
975 *
976 * Process GT workaround table for this platform, saving in @gt all the
977 * workarounds that need to be applied at the GT level.
978 */
979void xe_wa_process_gt(struct xe_gt *gt)
980{
981 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
982
983 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
984 ARRAY_SIZE(gt_was));
985 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), >->reg_sr);
986}
987EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
988
989/**
990 * xe_wa_process_engine - process engine workaround table
991 * @hwe: engine instance to process workarounds for
992 *
993 * Process engine workaround table for this platform, saving in @hwe all the
994 * workarounds that need to be applied at the engine level that match this
995 * engine.
996 */
997void xe_wa_process_engine(struct xe_hw_engine *hwe)
998{
999 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
1000
1001 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
1002 ARRAY_SIZE(engine_was));
1003 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), &hwe->reg_sr);
1004}
1005
1006/**
1007 * xe_wa_process_lrc - process context workaround table
1008 * @hwe: engine instance to process workarounds for
1009 *
1010 * Process context workaround table for this platform, saving in @hwe all the
1011 * workarounds that need to be applied on context restore. These are workarounds
1012 * touching registers that are part of the HW context image.
1013 */
1014void xe_wa_process_lrc(struct xe_hw_engine *hwe)
1015{
1016 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
1017
1018 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
1019 ARRAY_SIZE(lrc_was));
1020 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), &hwe->reg_lrc);
1021}
1022
1023/**
1024 * xe_wa_device_init - initialize device with workaround oob bookkeeping
1025 * @xe: Xe device instance to initialize
1026 *
1027 * Returns 0 for success, negative with error code otherwise
1028 */
1029int xe_wa_device_init(struct xe_device *xe)
1030{
1031 unsigned long *p;
1032
1033 p = drmm_kzalloc(&xe->drm,
1034 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)),
1035 GFP_KERNEL);
1036
1037 if (!p)
1038 return -ENOMEM;
1039
1040 xe->wa_active.oob = p;
1041
1042 return 0;
1043}
1044
1045/**
1046 * xe_wa_gt_init - initialize gt with workaround bookkeeping
1047 * @gt: GT instance to initialize
1048 *
1049 * Returns 0 for success, negative error code otherwise.
1050 */
1051int xe_wa_gt_init(struct xe_gt *gt)
1052{
1053 struct xe_device *xe = gt_to_xe(gt);
1054 size_t n_oob, n_lrc, n_engine, n_gt, total;
1055 unsigned long *p;
1056
1057 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
1058 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
1059 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
1060 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
1061 total = n_gt + n_engine + n_lrc + n_oob;
1062
1063 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
1064 if (!p)
1065 return -ENOMEM;
1066
1067 gt->wa_active.gt = p;
1068 p += n_gt;
1069 gt->wa_active.engine = p;
1070 p += n_engine;
1071 gt->wa_active.lrc = p;
1072 p += n_lrc;
1073 gt->wa_active.oob = p;
1074
1075 return 0;
1076}
1077ALLOW_ERROR_INJECTION(xe_wa_gt_init, ERRNO); /* See xe_pci_probe() */
1078
1079void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p)
1080{
1081 size_t idx;
1082
1083 drm_printf(p, "Device OOB Workarounds\n");
1084 for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was))
1085 if (device_oob_was[idx].name)
1086 drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name);
1087}
1088
1089void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
1090{
1091 size_t idx;
1092
1093 drm_printf(p, "GT Workarounds\n");
1094 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
1095 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
1096
1097 drm_printf(p, "\nEngine Workarounds\n");
1098 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
1099 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
1100
1101 drm_printf(p, "\nLRC Workarounds\n");
1102 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
1103 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
1104
1105 drm_printf(p, "\nOOB Workarounds\n");
1106 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
1107 if (oob_was[idx].name)
1108 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
1109}
1110
1111/*
1112 * Apply tile (non-GT, non-display) workarounds. Think very carefully before
1113 * adding anything to this function; most workarounds should be implemented
1114 * elsewhere. The programming here is primarily for sgunit/soc workarounds,
1115 * which are relatively rare. Since the registers these workarounds target are
1116 * outside the GT, they should only need to be applied once at device
1117 * probe/resume; they will not lose their values on any kind of GT or engine
1118 * reset.
1119 *
1120 * TODO: We may want to move this over to xe_rtp in the future once we have
1121 * enough workarounds to justify the work.
1122 */
1123void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
1124{
1125 struct xe_mmio *mmio = &tile->mmio;
1126
1127 if (IS_SRIOV_VF(tile->xe))
1128 return;
1129
1130 if (XE_GT_WA(tile->primary_gt, 22010954014))
1131 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
1132}