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Linux kernel mirror (for testing)
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linux
1/*
2 * Copyright 2005-2009 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU Lesser General
5 * Public License. You may obtain a copy of the GNU Lesser General
6 * Public License Version 2.1 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/lgpl-license.html
9 * http://www.gnu.org/copyleft/lgpl.html
10 */
11
12#ifndef __DRM_IPU_H__
13#define __DRM_IPU_H__
14
15#include <linux/types.h>
16#include <linux/videodev2.h>
17#include <linux/bitmap.h>
18#include <linux/fb.h>
19#include <linux/of.h>
20#include <drm/drm_color_mgmt.h>
21#include <media/v4l2-mediabus.h>
22#include <video/videomode.h>
23
24struct ipu_soc;
25
26enum ipuv3_type {
27 IPUV3EX,
28 IPUV3M,
29 IPUV3H,
30};
31
32#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
33
34/*
35 * Bitfield of Display Interface signal polarities.
36 */
37struct ipu_di_signal_cfg {
38 unsigned data_pol:1; /* true = inverted */
39 unsigned clk_pol:1; /* true = rising edge */
40 unsigned enable_pol:1;
41
42 struct videomode mode;
43
44 u32 bus_format;
45 u32 v_to_h_sync;
46
47#define IPU_DI_CLKMODE_SYNC (1 << 0)
48#define IPU_DI_CLKMODE_EXT (1 << 1)
49 unsigned long clkflags;
50
51 u8 hsync_pin;
52 u8 vsync_pin;
53};
54
55/*
56 * Enumeration of CSI destinations
57 */
58enum ipu_csi_dest {
59 IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
60 IPU_CSI_DEST_IC, /* to Image Converter */
61 IPU_CSI_DEST_VDIC, /* to VDIC */
62};
63
64/*
65 * Enumeration of IPU rotation modes
66 */
67#define IPU_ROT_BIT_VFLIP (1 << 0)
68#define IPU_ROT_BIT_HFLIP (1 << 1)
69#define IPU_ROT_BIT_90 (1 << 2)
70
71enum ipu_rotate_mode {
72 IPU_ROTATE_NONE = 0,
73 IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
74 IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
75 IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
76 IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
77 IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP),
78 IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP),
79 IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 |
80 IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
81};
82
83/* 90-degree rotations require the IRT unit */
84#define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)
85
86enum ipu_color_space {
87 IPUV3_COLORSPACE_RGB,
88 IPUV3_COLORSPACE_YUV,
89 IPUV3_COLORSPACE_UNKNOWN,
90};
91
92/*
93 * Enumeration of VDI MOTION select
94 */
95enum ipu_motion_sel {
96 MOTION_NONE = 0,
97 LOW_MOTION,
98 MED_MOTION,
99 HIGH_MOTION,
100};
101
102struct ipuv3_channel;
103
104enum ipu_channel_irq {
105 IPU_IRQ_EOF = 0,
106 IPU_IRQ_NFACK = 64,
107 IPU_IRQ_NFB4EOF = 128,
108 IPU_IRQ_EOS = 192,
109};
110
111/*
112 * Enumeration of IDMAC channels
113 */
114#define IPUV3_CHANNEL_CSI0 0
115#define IPUV3_CHANNEL_CSI1 1
116#define IPUV3_CHANNEL_CSI2 2
117#define IPUV3_CHANNEL_CSI3 3
118#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
119/*
120 * NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
121 * but the direct CSI->VDI linking is handled the same way as IDMAC
122 * channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
123 * these channel names are used to support the direct CSI->VDI link.
124 */
125#define IPUV3_CHANNEL_CSI_DIRECT 6
126#define IPUV3_CHANNEL_CSI_VDI_PREV 7
127#define IPUV3_CHANNEL_MEM_VDI_PREV 8
128#define IPUV3_CHANNEL_MEM_VDI_CUR 9
129#define IPUV3_CHANNEL_MEM_VDI_NEXT 10
130#define IPUV3_CHANNEL_MEM_IC_PP 11
131#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
132#define IPUV3_CHANNEL_VDI_MEM_RECENT 13
133#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
134#define IPUV3_CHANNEL_G_MEM_IC_PP 15
135#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17
136#define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA 18
137#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19
138#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
139#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
140#define IPUV3_CHANNEL_IC_PP_MEM 22
141#define IPUV3_CHANNEL_MEM_BG_SYNC 23
142#define IPUV3_CHANNEL_MEM_BG_ASYNC 24
143#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB 25
144#define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB 26
145#define IPUV3_CHANNEL_MEM_FG_SYNC 27
146#define IPUV3_CHANNEL_MEM_DC_SYNC 28
147#define IPUV3_CHANNEL_MEM_FG_ASYNC 29
148#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
149#define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA 33
150#define IPUV3_CHANNEL_DC_MEM_READ 40
151#define IPUV3_CHANNEL_MEM_DC_ASYNC 41
152#define IPUV3_CHANNEL_MEM_DC_COMMAND 42
153#define IPUV3_CHANNEL_MEM_DC_COMMAND2 43
154#define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK 44
155#define IPUV3_CHANNEL_MEM_ROT_ENC 45
156#define IPUV3_CHANNEL_MEM_ROT_VF 46
157#define IPUV3_CHANNEL_MEM_ROT_PP 47
158#define IPUV3_CHANNEL_ROT_ENC_MEM 48
159#define IPUV3_CHANNEL_ROT_VF_MEM 49
160#define IPUV3_CHANNEL_ROT_PP_MEM 50
161#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
162#define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52
163#define IPUV3_NUM_CHANNELS 64
164
165static inline int ipu_channel_alpha_channel(int ch_num)
166{
167 switch (ch_num) {
168 case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
169 return IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA;
170 case IPUV3_CHANNEL_G_MEM_IC_PP:
171 return IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA;
172 case IPUV3_CHANNEL_MEM_FG_SYNC:
173 return IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA;
174 case IPUV3_CHANNEL_MEM_FG_ASYNC:
175 return IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA;
176 case IPUV3_CHANNEL_MEM_BG_SYNC:
177 return IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA;
178 case IPUV3_CHANNEL_MEM_BG_ASYNC:
179 return IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA;
180 case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB:
181 return IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA;
182 default:
183 return -EINVAL;
184 }
185}
186
187int ipu_map_irq(struct ipu_soc *ipu, int irq);
188int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
189 enum ipu_channel_irq irq);
190
191#define IPU_IRQ_DP_SF_START (448 + 2)
192#define IPU_IRQ_DP_SF_END (448 + 3)
193#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
194#define IPU_IRQ_DC_FC_0 (448 + 8)
195#define IPU_IRQ_DC_FC_1 (448 + 9)
196#define IPU_IRQ_DC_FC_2 (448 + 10)
197#define IPU_IRQ_DC_FC_3 (448 + 11)
198#define IPU_IRQ_DC_FC_4 (448 + 12)
199#define IPU_IRQ_DC_FC_6 (448 + 13)
200#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
201#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
202
203/*
204 * IPU Common functions
205 */
206int ipu_get_num(struct ipu_soc *ipu);
207void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
208void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
209void ipu_dump(struct ipu_soc *ipu);
210
211/*
212 * IPU Image DMA Controller (idmac) functions
213 */
214struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
215void ipu_idmac_put(struct ipuv3_channel *);
216
217int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
218int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
219void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
220int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
221int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
222
223void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
224 bool doublebuffer);
225int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
226bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
227void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
228void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
229int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
230int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
231int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
232int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
233
234/*
235 * IPU Channel Parameter Memory (cpmem) functions
236 */
237struct ipu_rgb {
238 struct fb_bitfield red;
239 struct fb_bitfield green;
240 struct fb_bitfield blue;
241 struct fb_bitfield transp;
242 int bits_per_pixel;
243};
244
245struct ipu_image {
246 struct v4l2_pix_format pix;
247 struct v4l2_rect rect;
248 dma_addr_t phys0;
249 dma_addr_t phys1;
250 /* chroma plane offset overrides */
251 u32 u_offset;
252 u32 v_offset;
253};
254
255void ipu_cpmem_zero(struct ipuv3_channel *ch);
256void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
257void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch);
258void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
259void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
260void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
261void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
262void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride,
263 u32 pixelformat);
264void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
265void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
266void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
267void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
268 enum ipu_rotate_mode rot);
269int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
270 const struct ipu_rgb *rgb);
271int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
272void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
273 unsigned int uv_stride,
274 unsigned int u_offset,
275 unsigned int v_offset);
276int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
277int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
278void ipu_cpmem_dump(struct ipuv3_channel *ch);
279
280/*
281 * IPU Display Controller (dc) functions
282 */
283struct ipu_dc;
284struct ipu_di;
285struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
286void ipu_dc_put(struct ipu_dc *dc);
287int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
288 u32 pixel_fmt, u32 width);
289void ipu_dc_enable(struct ipu_soc *ipu);
290void ipu_dc_enable_channel(struct ipu_dc *dc);
291void ipu_dc_disable_channel(struct ipu_dc *dc);
292void ipu_dc_disable(struct ipu_soc *ipu);
293
294/*
295 * IPU Display Interface (di) functions
296 */
297struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
298void ipu_di_put(struct ipu_di *);
299int ipu_di_disable(struct ipu_di *);
300int ipu_di_enable(struct ipu_di *);
301int ipu_di_get_num(struct ipu_di *);
302int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
303int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
304
305/*
306 * IPU Display Multi FIFO Controller (dmfc) functions
307 */
308struct dmfc_channel;
309int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
310void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
311void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
312struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
313void ipu_dmfc_put(struct dmfc_channel *dmfc);
314
315/*
316 * IPU Display Processor (dp) functions
317 */
318#define IPU_DP_FLOW_SYNC_BG 0
319#define IPU_DP_FLOW_SYNC_FG 1
320#define IPU_DP_FLOW_ASYNC0_BG 2
321#define IPU_DP_FLOW_ASYNC0_FG 3
322#define IPU_DP_FLOW_ASYNC1_BG 4
323#define IPU_DP_FLOW_ASYNC1_FG 5
324
325struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
326void ipu_dp_put(struct ipu_dp *);
327int ipu_dp_enable(struct ipu_soc *ipu);
328int ipu_dp_enable_channel(struct ipu_dp *dp);
329void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync);
330void ipu_dp_disable(struct ipu_soc *ipu);
331int ipu_dp_setup_channel(struct ipu_dp *dp,
332 enum drm_color_encoding ycbcr_enc, enum drm_color_range range,
333 enum ipu_color_space in, enum ipu_color_space out);
334int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
335int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
336 bool bg_chan);
337
338/*
339 * IPU Prefetch Resolve Gasket (prg) functions
340 */
341int ipu_prg_max_active_channels(void);
342bool ipu_prg_present(struct ipu_soc *ipu);
343bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
344 uint64_t modifier);
345int ipu_prg_enable(struct ipu_soc *ipu);
346void ipu_prg_disable(struct ipu_soc *ipu);
347void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan);
348int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
349 unsigned int axi_id, unsigned int width,
350 unsigned int height, unsigned int stride,
351 u32 format, uint64_t modifier, unsigned long *eba);
352bool ipu_prg_channel_configure_pending(struct ipuv3_channel *ipu_chan);
353
354/*
355 * IPU CMOS Sensor Interface (csi) functions
356 */
357struct ipu_csi;
358int ipu_csi_init_interface(struct ipu_csi *csi,
359 const struct v4l2_mbus_config *mbus_cfg,
360 const struct v4l2_mbus_framefmt *infmt,
361 const struct v4l2_mbus_framefmt *outfmt);
362void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
363void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert);
364int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
365 struct v4l2_mbus_framefmt *mbus_fmt);
366int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
367 u32 max_ratio, u32 id);
368int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
369int ipu_csi_enable(struct ipu_csi *csi);
370int ipu_csi_disable(struct ipu_csi *csi);
371struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
372void ipu_csi_put(struct ipu_csi *csi);
373void ipu_csi_dump(struct ipu_csi *csi);
374
375/*
376 * IPU Image Converter (ic) functions
377 */
378enum ipu_ic_task {
379 IC_TASK_ENCODER,
380 IC_TASK_VIEWFINDER,
381 IC_TASK_POST_PROCESSOR,
382 IC_NUM_TASKS,
383};
384
385/*
386 * The parameters that describe a colorspace according to the
387 * Image Converter:
388 * - Y'CbCr encoding
389 * - quantization
390 * - "colorspace" (RGB or YUV).
391 */
392struct ipu_ic_colorspace {
393 enum v4l2_ycbcr_encoding enc;
394 enum v4l2_quantization quant;
395 enum ipu_color_space cs;
396};
397
398static inline void
399ipu_ic_fill_colorspace(struct ipu_ic_colorspace *ic_cs,
400 enum v4l2_ycbcr_encoding enc,
401 enum v4l2_quantization quant,
402 enum ipu_color_space cs)
403{
404 ic_cs->enc = enc;
405 ic_cs->quant = quant;
406 ic_cs->cs = cs;
407}
408
409struct ipu_ic_csc_params {
410 s16 coeff[3][3]; /* signed 9-bit integer coefficients */
411 s16 offset[3]; /* signed 11+2-bit fixed point offset */
412 u8 scale:2; /* scale coefficients * 2^(scale-1) */
413 bool sat:1; /* saturate to (16, 235(Y) / 240(U, V)) */
414};
415
416struct ipu_ic_csc {
417 struct ipu_ic_colorspace in_cs;
418 struct ipu_ic_colorspace out_cs;
419 struct ipu_ic_csc_params params;
420};
421
422struct ipu_ic;
423
424int __ipu_ic_calc_csc(struct ipu_ic_csc *csc);
425int ipu_ic_calc_csc(struct ipu_ic_csc *csc,
426 enum v4l2_ycbcr_encoding in_enc,
427 enum v4l2_quantization in_quant,
428 enum ipu_color_space in_cs,
429 enum v4l2_ycbcr_encoding out_enc,
430 enum v4l2_quantization out_quant,
431 enum ipu_color_space out_cs);
432int ipu_ic_task_init(struct ipu_ic *ic,
433 const struct ipu_ic_csc *csc,
434 int in_width, int in_height,
435 int out_width, int out_height);
436int ipu_ic_task_init_rsc(struct ipu_ic *ic,
437 const struct ipu_ic_csc *csc,
438 int in_width, int in_height,
439 int out_width, int out_height,
440 u32 rsc);
441void ipu_ic_task_enable(struct ipu_ic *ic);
442void ipu_ic_task_disable(struct ipu_ic *ic);
443int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
444 u32 width, u32 height, int burst_size,
445 enum ipu_rotate_mode rot);
446int ipu_ic_enable(struct ipu_ic *ic);
447int ipu_ic_disable(struct ipu_ic *ic);
448struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
449void ipu_ic_put(struct ipu_ic *ic);
450void ipu_ic_dump(struct ipu_ic *ic);
451
452/*
453 * IPU Video De-Interlacer (vdi) functions
454 */
455struct ipu_vdi;
456void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
457void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
458void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
459int ipu_vdi_enable(struct ipu_vdi *vdi);
460int ipu_vdi_disable(struct ipu_vdi *vdi);
461struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu);
462void ipu_vdi_put(struct ipu_vdi *vdi);
463
464/*
465 * IPU Sensor Multiple FIFO Controller (SMFC) functions
466 */
467struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
468void ipu_smfc_put(struct ipu_smfc *smfc);
469int ipu_smfc_enable(struct ipu_smfc *smfc);
470int ipu_smfc_disable(struct ipu_smfc *smfc);
471int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
472int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
473int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
474
475enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
476enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
477int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
478 bool hflip, bool vflip);
479
480struct ipu_client_platformdata {
481 int csi;
482 int di;
483 int dc;
484 int dp;
485 int dma[2];
486 struct device_node *of_node;
487};
488
489#endif /* __DRM_IPU_H__ */