Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates
4 * Copyright (c) 2023 Intel and affiliates
5 */
6
7#ifndef __DPLL_H__
8#define __DPLL_H__
9
10#include <uapi/linux/dpll.h>
11#include <linux/device.h>
12#include <linux/netlink.h>
13#include <linux/netdevice.h>
14#include <linux/rtnetlink.h>
15
16struct dpll_device;
17struct dpll_pin;
18struct dpll_pin_esync;
19
20struct dpll_device_ops {
21 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
22 enum dpll_mode *mode, struct netlink_ext_ack *extack);
23 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
24 enum dpll_lock_status *status,
25 enum dpll_lock_status_error *status_error,
26 struct netlink_ext_ack *extack);
27 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
28 s32 *temp, struct netlink_ext_ack *extack);
29 int (*clock_quality_level_get)(const struct dpll_device *dpll,
30 void *dpll_priv,
31 unsigned long *qls,
32 struct netlink_ext_ack *extack);
33 int (*phase_offset_monitor_set)(const struct dpll_device *dpll,
34 void *dpll_priv,
35 enum dpll_feature_state state,
36 struct netlink_ext_ack *extack);
37 int (*phase_offset_monitor_get)(const struct dpll_device *dpll,
38 void *dpll_priv,
39 enum dpll_feature_state *state,
40 struct netlink_ext_ack *extack);
41};
42
43struct dpll_pin_ops {
44 int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv,
45 const struct dpll_device *dpll, void *dpll_priv,
46 const u64 frequency,
47 struct netlink_ext_ack *extack);
48 int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv,
49 const struct dpll_device *dpll, void *dpll_priv,
50 u64 *frequency, struct netlink_ext_ack *extack);
51 int (*direction_set)(const struct dpll_pin *pin, void *pin_priv,
52 const struct dpll_device *dpll, void *dpll_priv,
53 const enum dpll_pin_direction direction,
54 struct netlink_ext_ack *extack);
55 int (*direction_get)(const struct dpll_pin *pin, void *pin_priv,
56 const struct dpll_device *dpll, void *dpll_priv,
57 enum dpll_pin_direction *direction,
58 struct netlink_ext_ack *extack);
59 int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv,
60 const struct dpll_pin *parent_pin,
61 void *parent_pin_priv,
62 enum dpll_pin_state *state,
63 struct netlink_ext_ack *extack);
64 int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv,
65 const struct dpll_device *dpll,
66 void *dpll_priv, enum dpll_pin_state *state,
67 struct netlink_ext_ack *extack);
68 int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv,
69 const struct dpll_pin *parent_pin,
70 void *parent_pin_priv,
71 const enum dpll_pin_state state,
72 struct netlink_ext_ack *extack);
73 int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv,
74 const struct dpll_device *dpll,
75 void *dpll_priv,
76 const enum dpll_pin_state state,
77 struct netlink_ext_ack *extack);
78 int (*prio_get)(const struct dpll_pin *pin, void *pin_priv,
79 const struct dpll_device *dpll, void *dpll_priv,
80 u32 *prio, struct netlink_ext_ack *extack);
81 int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
82 const struct dpll_device *dpll, void *dpll_priv,
83 const u32 prio, struct netlink_ext_ack *extack);
84 int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
85 const struct dpll_device *dpll, void *dpll_priv,
86 s64 *phase_offset,
87 struct netlink_ext_ack *extack);
88 int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
89 const struct dpll_device *dpll, void *dpll_priv,
90 s32 *phase_adjust,
91 struct netlink_ext_ack *extack);
92 int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
93 const struct dpll_device *dpll, void *dpll_priv,
94 const s32 phase_adjust,
95 struct netlink_ext_ack *extack);
96 int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv,
97 const struct dpll_device *dpll, void *dpll_priv,
98 s64 *ffo, struct netlink_ext_ack *extack);
99 int (*esync_set)(const struct dpll_pin *pin, void *pin_priv,
100 const struct dpll_device *dpll, void *dpll_priv,
101 u64 freq, struct netlink_ext_ack *extack);
102 int (*esync_get)(const struct dpll_pin *pin, void *pin_priv,
103 const struct dpll_device *dpll, void *dpll_priv,
104 struct dpll_pin_esync *esync,
105 struct netlink_ext_ack *extack);
106 int (*ref_sync_set)(const struct dpll_pin *pin, void *pin_priv,
107 const struct dpll_pin *ref_sync_pin,
108 void *ref_sync_pin_priv,
109 const enum dpll_pin_state state,
110 struct netlink_ext_ack *extack);
111 int (*ref_sync_get)(const struct dpll_pin *pin, void *pin_priv,
112 const struct dpll_pin *ref_sync_pin,
113 void *ref_sync_pin_priv,
114 enum dpll_pin_state *state,
115 struct netlink_ext_ack *extack);
116};
117
118struct dpll_pin_frequency {
119 u64 min;
120 u64 max;
121};
122
123#define DPLL_PIN_FREQUENCY_RANGE(_min, _max) \
124 { \
125 .min = _min, \
126 .max = _max, \
127 }
128
129#define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val)
130#define DPLL_PIN_FREQUENCY_1PPS \
131 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ)
132#define DPLL_PIN_FREQUENCY_10MHZ \
133 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ)
134#define DPLL_PIN_FREQUENCY_IRIG_B \
135 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ)
136#define DPLL_PIN_FREQUENCY_DCF77 \
137 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
138
139struct dpll_pin_phase_adjust_range {
140 s32 min;
141 s32 max;
142};
143
144struct dpll_pin_esync {
145 u64 freq;
146 const struct dpll_pin_frequency *range;
147 u8 range_num;
148 u8 pulse;
149};
150
151struct dpll_pin_properties {
152 const char *board_label;
153 const char *panel_label;
154 const char *package_label;
155 enum dpll_pin_type type;
156 unsigned long capabilities;
157 u32 freq_supported_num;
158 struct dpll_pin_frequency *freq_supported;
159 struct dpll_pin_phase_adjust_range phase_range;
160};
161
162#if IS_ENABLED(CONFIG_DPLL)
163void dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin);
164void dpll_netdev_pin_clear(struct net_device *dev);
165
166size_t dpll_netdev_pin_handle_size(const struct net_device *dev);
167int dpll_netdev_add_pin_handle(struct sk_buff *msg,
168 const struct net_device *dev);
169#else
170static inline void
171dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin) { }
172static inline void dpll_netdev_pin_clear(struct net_device *dev) { }
173
174static inline size_t dpll_netdev_pin_handle_size(const struct net_device *dev)
175{
176 return 0;
177}
178
179static inline int
180dpll_netdev_add_pin_handle(struct sk_buff *msg, const struct net_device *dev)
181{
182 return 0;
183}
184#endif
185
186struct dpll_device *
187dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module);
188
189void dpll_device_put(struct dpll_device *dpll);
190
191int dpll_device_register(struct dpll_device *dpll, enum dpll_type type,
192 const struct dpll_device_ops *ops, void *priv);
193
194void dpll_device_unregister(struct dpll_device *dpll,
195 const struct dpll_device_ops *ops, void *priv);
196
197struct dpll_pin *
198dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module,
199 const struct dpll_pin_properties *prop);
200
201int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,
202 const struct dpll_pin_ops *ops, void *priv);
203
204void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,
205 const struct dpll_pin_ops *ops, void *priv);
206
207void dpll_pin_put(struct dpll_pin *pin);
208
209int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin,
210 const struct dpll_pin_ops *ops, void *priv);
211
212void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin,
213 const struct dpll_pin_ops *ops, void *priv);
214
215int dpll_pin_ref_sync_pair_add(struct dpll_pin *pin,
216 struct dpll_pin *ref_sync_pin);
217
218int dpll_device_change_ntf(struct dpll_device *dpll);
219
220int dpll_pin_change_ntf(struct dpll_pin *pin);
221
222#endif