tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2023-2024 Linaro Ltd. */
4
5#include <linux/array_size.h>
6#include <linux/bits.h>
7#include <linux/types.h>
8
9#include "../gsi_reg.h"
10#include "../ipa_version.h"
11#include "../reg.h"
12
13REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
14 0x0000c020 + 0x1000 * GSI_EE_AP);
15
16REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
17 0x0000c024 + 0x1000 * GSI_EE_AP);
18
19static const u32 reg_ch_c_cntxt_0_fmask[] = {
20 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
21 [CHTYPE_DIR] = BIT(3),
22 [CH_EE] = GENMASK(7, 4),
23 [CHID] = GENMASK(12, 8),
24 [CHTYPE_PROTOCOL_MSB] = BIT(13),
25 [ERINDEX] = GENMASK(18, 14),
26 /* Bit 19 reserved */
27 [CHSTATE] = GENMASK(23, 20),
28 [ELEMENT_SIZE] = GENMASK(31, 24),
29};
30
31REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
32 0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
33
34static const u32 reg_ch_c_cntxt_1_fmask[] = {
35 [CH_R_LENGTH] = GENMASK(19, 0),
36 /* Bits 20-31 reserved */
37};
38
39REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
40 0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
41
42REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
43
44REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
45
46static const u32 reg_ch_c_qos_fmask[] = {
47 [WRR_WEIGHT] = GENMASK(3, 0),
48 /* Bits 4-7 reserved */
49 [MAX_PREFETCH] = BIT(8),
50 [USE_DB_ENG] = BIT(9),
51 [PREFETCH_MODE] = GENMASK(13, 10),
52 /* Bits 14-15 reserved */
53 [EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),
54 [DB_IN_BYTES] = BIT(24),
55 /* Bits 25-31 reserved */
56};
57
58REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
59
60static const u32 reg_error_log_fmask[] = {
61 [ERR_ARG3] = GENMASK(3, 0),
62 [ERR_ARG2] = GENMASK(7, 4),
63 [ERR_ARG1] = GENMASK(11, 8),
64 [ERR_CODE] = GENMASK(15, 12),
65 /* Bits 16-18 reserved */
66 [ERR_VIRT_IDX] = GENMASK(23, 19),
67 [ERR_TYPE] = GENMASK(27, 24),
68 [ERR_EE] = GENMASK(31, 28),
69};
70
71REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
72 0x0000f060 + 0x4000 * GSI_EE_AP, 0x80);
73
74REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
75 0x0000f064 + 0x4000 * GSI_EE_AP, 0x80);
76
77REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
78 0x0000f068 + 0x4000 * GSI_EE_AP, 0x80);
79
80REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
81 0x0000f06c + 0x4000 * GSI_EE_AP, 0x80);
82
83static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
84 [EV_CHTYPE] = GENMASK(3, 0),
85 [EV_EE] = GENMASK(7, 4),
86 [EV_EVCHID] = GENMASK(15, 8),
87 [EV_INTYPE] = BIT(16),
88 /* Bits 17-19 reserved */
89 [EV_CHSTATE] = GENMASK(23, 20),
90 [EV_ELEMENT_SIZE] = GENMASK(31, 24),
91};
92
93REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
94 0x00010000 + 0x4000 * GSI_EE_AP, 0x80);
95
96static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
97 [R_LENGTH] = GENMASK(15, 0),
98};
99
100REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
101 0x00010004 + 0x4000 * GSI_EE_AP, 0x80);
102
103REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
104 0x00010008 + 0x4000 * GSI_EE_AP, 0x80);
105
106REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
107 0x0001000c + 0x4000 * GSI_EE_AP, 0x80);
108
109REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
110 0x00010010 + 0x4000 * GSI_EE_AP, 0x80);
111
112static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
113 [EV_MODT] = GENMASK(15, 0),
114 [EV_MODC] = GENMASK(23, 16),
115 [EV_MOD_CNT] = GENMASK(31, 24),
116};
117
118REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
119 0x00010020 + 0x4000 * GSI_EE_AP, 0x80);
120
121REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
122 0x00010024 + 0x4000 * GSI_EE_AP, 0x80);
123
124REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
125 0x00010028 + 0x4000 * GSI_EE_AP, 0x80);
126
127REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
128 0x0001002c + 0x4000 * GSI_EE_AP, 0x80);
129
130REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
131 0x00010030 + 0x4000 * GSI_EE_AP, 0x80);
132
133REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
134 0x00010034 + 0x4000 * GSI_EE_AP, 0x80);
135
136REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
137 0x00010048 + 0x4000 * GSI_EE_AP, 0x80);
138
139REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
140 0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
141
142REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
143 0x00011000 + 0x4000 * GSI_EE_AP, 0x08);
144
145REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
146 0x00011100 + 0x4000 * GSI_EE_AP, 0x08);
147
148static const u32 reg_gsi_status_fmask[] = {
149 [ENABLED] = BIT(0),
150 /* Bits 1-31 reserved */
151};
152
153REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP);
154
155static const u32 reg_ch_cmd_fmask[] = {
156 [CH_CHID] = GENMASK(7, 0),
157 /* Bits 8-23 reserved */
158 [CH_OPCODE] = GENMASK(31, 24),
159};
160
161REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP);
162
163static const u32 reg_ev_ch_cmd_fmask[] = {
164 [EV_CHID] = GENMASK(7, 0),
165 /* Bits 8-23 reserved */
166 [EV_OPCODE] = GENMASK(31, 24),
167};
168
169REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP);
170
171static const u32 reg_generic_cmd_fmask[] = {
172 [GENERIC_OPCODE] = GENMASK(4, 0),
173 [GENERIC_CHID] = GENMASK(9, 5),
174 [GENERIC_EE] = GENMASK(13, 10),
175 /* Bits 14-31 reserved */
176};
177
178REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP);
179
180static const u32 reg_hw_param_2_fmask[] = {
181 [IRAM_SIZE] = GENMASK(2, 0),
182 [NUM_CH_PER_EE] = GENMASK(7, 3),
183 [NUM_EV_PER_EE] = GENMASK(12, 8),
184 [GSI_CH_PEND_TRANSLATE] = BIT(13),
185 [GSI_CH_FULL_LOGIC] = BIT(14),
186 [GSI_USE_SDMA] = BIT(15),
187 [GSI_SDMA_N_INT] = GENMASK(18, 16),
188 [GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
189 [GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
190 [GSI_USE_RD_WR_ENG] = BIT(30),
191 [GSI_USE_INTER_EE] = BIT(31),
192};
193
194REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP);
195
196REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
197
198REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
199
200REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
201
202REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
203
204REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
205 0x00012098 + 0x4000 * GSI_EE_AP);
206
207REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
208 0x0001209c + 0x4000 * GSI_EE_AP);
209
210REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
211 0x000120a0 + 0x4000 * GSI_EE_AP);
212
213REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
214 0x000120a4 + 0x4000 * GSI_EE_AP);
215
216REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
217
218REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
219 0x000120b8 + 0x4000 * GSI_EE_AP);
220
221REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
222 0x000120c0 + 0x4000 * GSI_EE_AP);
223
224REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
225
226REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
227
228REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
229
230REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
231
232REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
233
234REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
235
236static const u32 reg_cntxt_intset_fmask[] = {
237 [INTYPE] = BIT(0)
238 /* Bits 1-31 reserved */
239};
240
241REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP);
242
243REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP);
244
245REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
246
247static const u32 reg_cntxt_scratch_0_fmask[] = {
248 [INTER_EE_RESULT] = GENMASK(2, 0),
249 /* Bits 3-4 reserved */
250 [GENERIC_EE_RESULT] = GENMASK(7, 5),
251 /* Bits 8-31 reserved */
252};
253
254REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP);
255
256static const struct reg *reg_array[] = {
257 [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk,
258 [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk,
259 [CH_C_CNTXT_0] = ®_ch_c_cntxt_0,
260 [CH_C_CNTXT_1] = ®_ch_c_cntxt_1,
261 [CH_C_CNTXT_2] = ®_ch_c_cntxt_2,
262 [CH_C_CNTXT_3] = ®_ch_c_cntxt_3,
263 [CH_C_QOS] = ®_ch_c_qos,
264 [CH_C_SCRATCH_0] = ®_ch_c_scratch_0,
265 [CH_C_SCRATCH_1] = ®_ch_c_scratch_1,
266 [CH_C_SCRATCH_2] = ®_ch_c_scratch_2,
267 [CH_C_SCRATCH_3] = ®_ch_c_scratch_3,
268 [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0,
269 [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1,
270 [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2,
271 [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3,
272 [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4,
273 [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8,
274 [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9,
275 [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10,
276 [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11,
277 [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12,
278 [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13,
279 [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0,
280 [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1,
281 [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0,
282 [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0,
283 [GSI_STATUS] = ®_gsi_status,
284 [CH_CMD] = ®_ch_cmd,
285 [EV_CH_CMD] = ®_ev_ch_cmd,
286 [GENERIC_CMD] = ®_generic_cmd,
287 [HW_PARAM_2] = ®_hw_param_2,
288 [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq,
289 [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk,
290 [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq,
291 [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq,
292 [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk,
293 [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk,
294 [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr,
295 [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr,
296 [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq,
297 [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk,
298 [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr,
299 [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts,
300 [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en,
301 [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr,
302 [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts,
303 [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en,
304 [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr,
305 [CNTXT_INTSET] = ®_cntxt_intset,
306 [ERROR_LOG] = ®_error_log,
307 [ERROR_LOG_CLR] = ®_error_log_clr,
308 [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0,
309};
310
311const struct regs gsi_regs_v4_9 = {
312 .reg_count = ARRAY_SIZE(reg_array),
313 .reg = reg_array,
314};