tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2023-2024 Linaro Ltd. */
4
5#include <linux/array_size.h>
6#include <linux/bits.h>
7#include <linux/types.h>
8
9#include "../gsi_reg.h"
10#include "../ipa_version.h"
11#include "../reg.h"
12
13REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
14 0x0000c020 + 0x1000 * GSI_EE_AP);
15
16REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
17 0x0000c024 + 0x1000 * GSI_EE_AP);
18
19static const u32 reg_ch_c_cntxt_0_fmask[] = {
20 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
21 [CHTYPE_DIR] = BIT(3),
22 [CH_EE] = GENMASK(7, 4),
23 [CHID] = GENMASK(12, 8),
24 /* Bit 13 reserved */
25 [ERINDEX] = GENMASK(18, 14),
26 /* Bit 19 reserved */
27 [CHSTATE] = GENMASK(23, 20),
28 [ELEMENT_SIZE] = GENMASK(31, 24),
29};
30
31REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
32 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
33
34static const u32 reg_ch_c_cntxt_1_fmask[] = {
35 [CH_R_LENGTH] = GENMASK(15, 0),
36 /* Bits 16-31 reserved */
37};
38
39REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
40 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
41
42REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
43
44REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
45
46static const u32 reg_ch_c_qos_fmask[] = {
47 [WRR_WEIGHT] = GENMASK(3, 0),
48 /* Bits 4-7 reserved */
49 [MAX_PREFETCH] = BIT(8),
50 [USE_DB_ENG] = BIT(9),
51 /* Bits 10-31 reserved */
52};
53
54REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
55
56static const u32 reg_error_log_fmask[] = {
57 [ERR_ARG3] = GENMASK(3, 0),
58 [ERR_ARG2] = GENMASK(7, 4),
59 [ERR_ARG1] = GENMASK(11, 8),
60 [ERR_CODE] = GENMASK(15, 12),
61 /* Bits 16-18 reserved */
62 [ERR_VIRT_IDX] = GENMASK(23, 19),
63 [ERR_TYPE] = GENMASK(27, 24),
64 [ERR_EE] = GENMASK(31, 28),
65};
66
67REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
68 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
69
70REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
71 0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
72
73REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
74 0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
75
76REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
77 0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
78
79static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
80 [EV_CHTYPE] = GENMASK(3, 0),
81 [EV_EE] = GENMASK(7, 4),
82 [EV_EVCHID] = GENMASK(15, 8),
83 [EV_INTYPE] = BIT(16),
84 /* Bits 17-19 reserved */
85 [EV_CHSTATE] = GENMASK(23, 20),
86 [EV_ELEMENT_SIZE] = GENMASK(31, 24),
87};
88
89REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
90 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
91
92static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
93 [R_LENGTH] = GENMASK(15, 0),
94};
95
96REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
97 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
98
99REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
100 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
101
102REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
103 0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
104
105REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
106 0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
107
108static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
109 [EV_MODT] = GENMASK(15, 0),
110 [EV_MODC] = GENMASK(23, 16),
111 [EV_MOD_CNT] = GENMASK(31, 24),
112};
113
114REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
115 0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
116
117REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
118 0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
119
120REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
121 0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
122
123REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
124 0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
125
126REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
127 0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
128
129REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
130 0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
131
132REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
133 0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
134
135REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
136 0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
137
138REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
139 0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
140
141REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
142 0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
143
144static const u32 reg_gsi_status_fmask[] = {
145 [ENABLED] = BIT(0),
146 /* Bits 1-31 reserved */
147};
148
149REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
150
151static const u32 reg_ch_cmd_fmask[] = {
152 [CH_CHID] = GENMASK(7, 0),
153 /* Bits 8-23 reserved */
154 [CH_OPCODE] = GENMASK(31, 24),
155};
156
157REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
158
159static const u32 reg_ev_ch_cmd_fmask[] = {
160 [EV_CHID] = GENMASK(7, 0),
161 /* Bits 8-23 reserved */
162 [EV_OPCODE] = GENMASK(31, 24),
163};
164
165REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
166
167static const u32 reg_generic_cmd_fmask[] = {
168 [GENERIC_OPCODE] = GENMASK(4, 0),
169 [GENERIC_CHID] = GENMASK(9, 5),
170 [GENERIC_EE] = GENMASK(13, 10),
171 /* Bits 14-31 reserved */
172};
173
174REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
175
176REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
177
178REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
179
180REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
181
182REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
183
184REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
185 0x0001f098 + 0x4000 * GSI_EE_AP);
186
187REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
188 0x0001f09c + 0x4000 * GSI_EE_AP);
189
190REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
191 0x0001f0a0 + 0x4000 * GSI_EE_AP);
192
193REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
194 0x0001f0a4 + 0x4000 * GSI_EE_AP);
195
196REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
197
198REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
199 0x0001f0b8 + 0x4000 * GSI_EE_AP);
200
201REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
202 0x0001f0c0 + 0x4000 * GSI_EE_AP);
203
204REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
205
206REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
207
208REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
209
210REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
211
212REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
213
214REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
215
216static const u32 reg_cntxt_intset_fmask[] = {
217 [INTYPE] = BIT(0)
218 /* Bits 1-31 reserved */
219};
220
221REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
222
223REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
224
225REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
226
227static const u32 reg_cntxt_scratch_0_fmask[] = {
228 [INTER_EE_RESULT] = GENMASK(2, 0),
229 /* Bits 3-4 reserved */
230 [GENERIC_EE_RESULT] = GENMASK(7, 5),
231 /* Bits 8-31 reserved */
232};
233
234REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
235
236static const struct reg *reg_array[] = {
237 [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk,
238 [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk,
239 [CH_C_CNTXT_0] = ®_ch_c_cntxt_0,
240 [CH_C_CNTXT_1] = ®_ch_c_cntxt_1,
241 [CH_C_CNTXT_2] = ®_ch_c_cntxt_2,
242 [CH_C_CNTXT_3] = ®_ch_c_cntxt_3,
243 [CH_C_QOS] = ®_ch_c_qos,
244 [CH_C_SCRATCH_0] = ®_ch_c_scratch_0,
245 [CH_C_SCRATCH_1] = ®_ch_c_scratch_1,
246 [CH_C_SCRATCH_2] = ®_ch_c_scratch_2,
247 [CH_C_SCRATCH_3] = ®_ch_c_scratch_3,
248 [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0,
249 [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1,
250 [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2,
251 [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3,
252 [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4,
253 [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8,
254 [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9,
255 [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10,
256 [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11,
257 [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12,
258 [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13,
259 [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0,
260 [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1,
261 [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0,
262 [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0,
263 [GSI_STATUS] = ®_gsi_status,
264 [CH_CMD] = ®_ch_cmd,
265 [EV_CH_CMD] = ®_ev_ch_cmd,
266 [GENERIC_CMD] = ®_generic_cmd,
267 [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq,
268 [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk,
269 [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq,
270 [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq,
271 [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk,
272 [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk,
273 [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr,
274 [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr,
275 [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq,
276 [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk,
277 [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr,
278 [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts,
279 [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en,
280 [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr,
281 [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts,
282 [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en,
283 [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr,
284 [CNTXT_INTSET] = ®_cntxt_intset,
285 [ERROR_LOG] = ®_error_log,
286 [ERROR_LOG_CLR] = ®_error_log_clr,
287 [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0,
288};
289
290const struct regs gsi_regs_v3_1 = {
291 .reg_count = ARRAY_SIZE(reg_array),
292 .reg = reg_array,
293};