tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8
9/ {
10 compatible = "brcm,bcm6855", "brcm,bcmbca";
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 interrupt-parent = <&gic>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 CA7_0: cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a7";
23 reg = <0x0>;
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
26 };
27
28 CA7_1: cpu@1 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a7";
31 reg = <0x1>;
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
34 };
35
36 CA7_2: cpu@2 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a7";
39 reg = <0x2>;
40 next-level-cache = <&L2_0>;
41 enable-method = "psci";
42 };
43
44 L2_0: l2-cache0 {
45 compatible = "cache";
46 cache-level = <2>;
47 cache-unified;
48 };
49 };
50
51 timer {
52 compatible = "arm,armv7-timer";
53 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
54 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
55 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
56 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
57 arm,cpu-registers-not-fw-configured;
58 };
59
60 pmu: pmu {
61 compatible = "arm,cortex-a7-pmu";
62 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
65 interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
66 };
67
68 clocks: clocks {
69 periph_clk: periph-clk {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <200000000>;
73 };
74
75 uart_clk: uart-clk {
76 compatible = "fixed-factor-clock";
77 #clock-cells = <0>;
78 clocks = <&periph_clk>;
79 clock-div = <4>;
80 clock-mult = <1>;
81 };
82
83 hsspi_pll: hsspi-pll {
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <200000000>;
87 };
88 };
89
90 psci {
91 compatible = "arm,psci-0.2";
92 method = "smc";
93 };
94
95 axi@81000000 {
96 compatible = "simple-bus";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges = <0 0x81000000 0x8000>;
100
101 gic: interrupt-controller@1000 {
102 compatible = "arm,cortex-a7-gic";
103 #interrupt-cells = <3>;
104 interrupt-controller;
105 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
106 reg = <0x1000 0x1000>,
107 <0x2000 0x2000>,
108 <0x4000 0x2000>,
109 <0x6000 0x2000>;
110 };
111 };
112
113 bus@ff800000 {
114 compatible = "simple-bus";
115 #address-cells = <1>;
116 #size-cells = <1>;
117 ranges = <0 0xff800000 0x800000>;
118
119 watchdog@480 {
120 compatible = "brcm,bcm6345-wdt";
121 reg = <0x480 0x10>;
122 };
123
124 watchdog@4c0 {
125 compatible = "brcm,bcm6345-wdt";
126 reg = <0x4c0 0x10>;
127 status = "disabled";
128 };
129
130 /* GPIOs 0 .. 31 */
131 gpio0: gpio@500 {
132 compatible = "brcm,bcm6345-gpio";
133 reg = <0x500 0x04>, <0x520 0x04>;
134 reg-names = "dirout", "dat";
135 gpio-controller;
136 #gpio-cells = <2>;
137 status = "disabled";
138 };
139
140 /* GPIOs 32 .. 63 */
141 gpio1: gpio@504 {
142 compatible = "brcm,bcm6345-gpio";
143 reg = <0x504 0x04>, <0x524 0x04>;
144 reg-names = "dirout", "dat";
145 gpio-controller;
146 #gpio-cells = <2>;
147 status = "disabled";
148 };
149
150 /* GPIOs 64 .. 95 */
151 gpio2: gpio@508 {
152 compatible = "brcm,bcm6345-gpio";
153 reg = <0x508 0x04>, <0x528 0x04>;
154 reg-names = "dirout", "dat";
155 gpio-controller;
156 #gpio-cells = <2>;
157 status = "disabled";
158 };
159
160 /* GPIOs 96 .. 127 */
161 gpio3: gpio@50c {
162 compatible = "brcm,bcm6345-gpio";
163 reg = <0x50c 0x04>, <0x52c 0x04>;
164 reg-names = "dirout", "dat";
165 gpio-controller;
166 #gpio-cells = <2>;
167 status = "disabled";
168 };
169
170 /* GPIOs 128 .. 159 */
171 gpio4: gpio@510 {
172 compatible = "brcm,bcm6345-gpio";
173 reg = <0x510 0x04>, <0x530 0x04>;
174 reg-names = "dirout", "dat";
175 gpio-controller;
176 #gpio-cells = <2>;
177 status = "disabled";
178 };
179
180 /* GPIOs 160 .. 191 */
181 gpio5: gpio@514 {
182 compatible = "brcm,bcm6345-gpio";
183 reg = <0x514 0x04>, <0x534 0x04>;
184 reg-names = "dirout", "dat";
185 gpio-controller;
186 #gpio-cells = <2>;
187 status = "disabled";
188 };
189
190 /* GPIOs 192 .. 223 */
191 gpio6: gpio@518 {
192 compatible = "brcm,bcm6345-gpio";
193 reg = <0x518 0x04>, <0x538 0x04>;
194 reg-names = "dirout", "dat";
195 gpio-controller;
196 #gpio-cells = <2>;
197 status = "disabled";
198 };
199
200 /* GPIOs 224 .. 255 */
201 gpio7: gpio@51c {
202 compatible = "brcm,bcm6345-gpio";
203 reg = <0x51c 0x04>, <0x53c 0x04>;
204 reg-names = "dirout", "dat";
205 gpio-controller;
206 #gpio-cells = <2>;
207 status = "disabled";
208 };
209
210 rng@b80 {
211 compatible = "brcm,iproc-rng200";
212 reg = <0xb80 0x28>;
213 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
214 };
215
216 hsspi: spi@1000 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "brcm,bcm6855-hsspi", "brcm,bcmbca-hsspi-v1.1";
220 reg = <0x1000 0x600>, <0x2610 0x4>;
221 reg-names = "hsspi", "spim-ctrl";
222 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&hsspi_pll &hsspi_pll>;
224 clock-names = "hsspi", "pll";
225 num-cs = <8>;
226 status = "disabled";
227 };
228
229 nand_controller: nand-controller@1800 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
233 reg = <0x1800 0x600>, <0x2000 0x10>;
234 reg-names = "nand", "nand-int-base";
235 status = "disabled";
236
237 nandcs: nand@0 {
238 compatible = "brcm,nandcs";
239 reg = <0>;
240 };
241 };
242
243 leds: led-controller@3000 {
244 #address-cells = <1>;
245 #size-cells = <0>;
246 compatible = "brcm,bcm63138-leds";
247 reg = <0x3000 0xdc>;
248 status = "disabled";
249 };
250
251 pl081_dma: dma-controller@11000 {
252 compatible = "arm,pl081", "arm,primecell";
253 // The magic B105F00D info is missing
254 arm,primecell-periphid = <0x00041081>;
255 reg = <0x11000 0x1000>;
256 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
257 memcpy-burst-size = <256>;
258 memcpy-bus-width = <32>;
259 clocks = <&periph_clk>;
260 clock-names = "apb_pclk";
261 #dma-cells = <2>;
262 };
263
264 uart0: serial@12000 {
265 compatible = "arm,pl011", "arm,primecell";
266 reg = <0x12000 0x1000>;
267 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&uart_clk>, <&uart_clk>;
269 clock-names = "uartclk", "apb_pclk";
270 status = "disabled";
271 };
272
273 uart1: serial@13000 {
274 compatible = "arm,pl011", "arm,primecell";
275 reg = <0x13000 0x1000>;
276 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&uart_clk>, <&uart_clk>;
278 clock-names = "uartclk", "apb_pclk";
279 status = "disabled";
280 };
281 };
282};