tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive Core Local Interruptor
8
9maintainers:
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
12
13description:
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18 interrupt controller is the parent interrupt controller for CLINT device.
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
20 property of "/cpus" DT node. The "timebase-frequency" DT property is
21 described in Documentation/devicetree/bindings/riscv/cpus.yaml
22
23 T-Head C906/C910 CPU cores include an implementation of CLINT too, however
24 their implementation lacks a memory-mapped MTIME register, thus not
25 compatible with SiFive ones.
26
27properties:
28 compatible:
29 oneOf:
30 - items:
31 - enum:
32 - canaan,k210-clint # Canaan Kendryte K210
33 - eswin,eic7700-clint # ESWIN EIC7700
34 - sifive,fu540-c000-clint # SiFive FU540
35 - spacemit,k1-clint # SpacemiT K1
36 - starfive,jh7100-clint # StarFive JH7100
37 - starfive,jh7110-clint # StarFive JH7110
38 - starfive,jh8100-clint # StarFive JH8100
39 - const: sifive,clint0 # SiFive CLINT v0 IP block
40 - items:
41 - {}
42 - const: sifive,clint2 # SiFive CLINT v2 IP block
43 description:
44 SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
45 differs from that of sifive,clint0, making them incompatible.
46 - items:
47 - enum:
48 - allwinner,sun20i-d1-clint
49 - sophgo,cv1800b-clint
50 - sophgo,cv1812h-clint
51 - sophgo,sg2002-clint
52 - thead,th1520-clint
53 - const: thead,c900-clint
54 - items:
55 - const: sifive,clint0
56 - const: riscv,clint0
57 deprecated: true
58 description: For the QEMU virt machine only
59
60 description:
61 Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
62 when compatible with a SiFive CLINT. Please refer to
63 sifive-blocks-ip-versioning.txt for details regarding the latter.
64
65 reg:
66 maxItems: 1
67
68 interrupts-extended:
69 minItems: 1
70 maxItems: 4095
71
72 sifive,fine-ctr-bits:
73 maximum: 15
74 description: The width in bits of the fine counter.
75
76if:
77 properties:
78 compatible:
79 contains:
80 const: sifive,clint2
81then:
82 required:
83 - sifive,fine-ctr-bits
84else:
85 properties:
86 sifive,fine-ctr-bits: false
87
88additionalProperties: false
89
90required:
91 - compatible
92 - reg
93 - interrupts-extended
94
95examples:
96 - |
97 timer@2000000 {
98 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
99 interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
100 <&cpu2intc 3>, <&cpu2intc 7>,
101 <&cpu3intc 3>, <&cpu3intc 7>,
102 <&cpu4intc 3>, <&cpu4intc 7>;
103 reg = <0x2000000 0x10000>;
104 };
105...