tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
8
9maintainers:
10 - Biju Das <biju.das.jz@bp.renesas.com>
11
12description: |
13 The 5P35023 is a VersaClock programmable clock generator and
14 is designed for low-power, consumer, and high-performance PCI
15 express applications. The 5P35023 device is a three PLL
16 architecture design, and each PLL is individually programmable
17 and allowing for up to 6 unique frequency outputs.
18
19 An internal OTP memory allows the user to store the configuration
20 in the device. After power up, the user can change the device register
21 settings through the I2C interface when I2C mode is selected.
22
23 The driver can read a full register map from the DT, and will use that
24 register map to initialize the attached part (via I2C) when the system
25 boots. Any configuration not supported by the common clock framework
26 must be done via the full register map, including optimized settings.
27
28 Link to datasheet:
29 https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator
30
31properties:
32 compatible:
33 enum:
34 - renesas,5l35023
35 - renesas,5p35023
36
37 reg:
38 maxItems: 1
39
40 '#clock-cells':
41 description:
42 The index in the assigned-clocks is mapped to the output clock as below
43 0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2.
44 const: 1
45
46 clocks:
47 maxItems: 1
48
49 renesas,settings:
50 description: Optional, complete register map of the device.
51 Optimized settings for the device must be provided in full
52 and are written during initialization.
53 $ref: /schemas/types.yaml#/definitions/uint8-array
54 maxItems: 37
55
56required:
57 - compatible
58 - reg
59 - '#clock-cells'
60 - clocks
61
62additionalProperties: false
63
64examples:
65 - |
66 i2c {
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 versa3: clock-generator@68 {
71 compatible = "renesas,5p35023";
72 reg = <0x68>;
73 #clock-cells = <1>;
74
75 clocks = <&x1>;
76
77 renesas,settings = [
78 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
79 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
80 80 b0 45 c4 95
81 ];
82
83 assigned-clocks = <&versa3 0>, <&versa3 1>,
84 <&versa3 2>, <&versa3 3>,
85 <&versa3 4>, <&versa3 5>;
86 assigned-clock-rates = <24000000>, <11289600>,
87 <11289600>, <12000000>,
88 <25000000>, <12288000>;
89 };
90 };