tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: GPL-2.0-or-later
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2500-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ASPEED AST2500 Pin Controller
8
9maintainers:
10 - Andrew Jeffery <andrew@aj.id.au>
11
12description: |+
13 The pin controller node should be the child of a syscon node with the
14 required property:
15
16 - compatible: Should be one of the following:
17 "aspeed,ast2500-scu", "syscon", "simple-mfd"
18 "aspeed,g5-scu", "syscon", "simple-mfd"
19
20 Refer to the bindings described in
21 Documentation/devicetree/bindings/mfd/syscon.yaml
22
23properties:
24 compatible:
25 const: aspeed,ast2500-pinctrl
26 reg:
27 maxItems: 2
28
29 aspeed,external-nodes:
30 minItems: 2
31 maxItems: 2
32 items:
33 maxItems: 1
34 $ref: /schemas/types.yaml#/definitions/phandle-array
35 description: |
36 A cell of phandles to external controller nodes:
37 0: compatible with "aspeed,ast2500-gfx", "syscon"
38 1: compatible with "aspeed,ast2500-lpc", "syscon"
39
40additionalProperties:
41 $ref: pinmux-node.yaml#
42 additionalProperties: false
43
44 properties:
45 pins: true
46 bias-disable: true
47
48 patternProperties:
49 "^function|groups$":
50 enum:
51 - ACPI
52 - ADC0
53 - ADC1
54 - ADC10
55 - ADC11
56 - ADC12
57 - ADC13
58 - ADC14
59 - ADC15
60 - ADC2
61 - ADC3
62 - ADC4
63 - ADC5
64 - ADC6
65 - ADC7
66 - ADC8
67 - ADC9
68 - BMCINT
69 - DDCCLK
70 - DDCDAT
71 - ESPI
72 - FWSPICS1
73 - FWSPICS2
74 - GPID0
75 - GPID2
76 - GPID4
77 - GPID6
78 - GPIE0
79 - GPIE2
80 - GPIE4
81 - GPIE6
82 - I2C10
83 - I2C11
84 - I2C12
85 - I2C13
86 - I2C14
87 - I2C3
88 - I2C4
89 - I2C5
90 - I2C6
91 - I2C7
92 - I2C8
93 - I2C9
94 - LAD0
95 - LAD1
96 - LAD2
97 - LAD3
98 - LCLK
99 - LFRAME
100 - LPCHC
101 - LPCPD
102 - LPCPLUS
103 - LPCPME
104 - LPCRST
105 - LPCSMI
106 - LSIRQ
107 - MAC1LINK
108 - MAC2LINK
109 - MDIO1
110 - MDIO2
111 - NCTS1
112 - NCTS2
113 - NCTS3
114 - NCTS4
115 - NDCD1
116 - NDCD2
117 - NDCD3
118 - NDCD4
119 - NDSR1
120 - NDSR2
121 - NDSR3
122 - NDSR4
123 - NDTR1
124 - NDTR2
125 - NDTR3
126 - NDTR4
127 - NRI1
128 - NRI2
129 - NRI3
130 - NRI4
131 - NRTS1
132 - NRTS2
133 - NRTS3
134 - NRTS4
135 - OSCCLK
136 - PEWAKE
137 - PNOR
138 - PWM0
139 - PWM1
140 - PWM2
141 - PWM3
142 - PWM4
143 - PWM5
144 - PWM6
145 - PWM7
146 - RGMII1
147 - RGMII2
148 - RMII1
149 - RMII2
150 - RXD1
151 - RXD2
152 - RXD3
153 - RXD4
154 - SALT1
155 - SALT10
156 - SALT11
157 - SALT12
158 - SALT13
159 - SALT14
160 - SALT2
161 - SALT3
162 - SALT4
163 - SALT5
164 - SALT6
165 - SALT7
166 - SALT8
167 - SALT9
168 - SCL1
169 - SCL2
170 - SD1
171 - SD2
172 - SDA1
173 - SDA2
174 - SGPM
175 - SGPS1
176 - SGPS2
177 - SIOONCTRL
178 - SIOPBI
179 - SIOPBO
180 - SIOPWREQ
181 - SIOPWRGD
182 - SIOS3
183 - SIOS5
184 - SIOSCI
185 - SPI1
186 - SPI1CS1
187 - SPI1DEBUG
188 - SPI1PASSTHRU
189 - SPI2CK
190 - SPI2CS0
191 - SPI2CS1
192 - SPI2MISO
193 - SPI2MOSI
194 - TIMER3
195 - TIMER4
196 - TIMER5
197 - TIMER6
198 - TIMER7
199 - TIMER8
200 - TXD1
201 - TXD2
202 - TXD3
203 - TXD4
204 - UART6
205 - USB11BHID
206 - USB2AD
207 - USB2AH
208 - USB2BD
209 - USB2BH
210 - USBCKI
211 - VGABIOSROM
212 - VGAHS
213 - VGAVS
214 - VPI24
215 - VPO
216 - WDTRST1
217 - WDTRST2
218
219allOf:
220 - $ref: pinctrl.yaml#
221
222required:
223 - compatible
224 - aspeed,external-nodes
225
226examples:
227 - |
228 #include <dt-bindings/clock/aspeed-clock.h>
229 scu@1e6e2000 {
230 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
231 reg = <0x1e6e2000 0x1a8>;
232 #clock-cells = <1>;
233 #reset-cells = <1>;
234
235 #address-cells = <1>;
236 #size-cells = <1>;
237 ranges = <0x0 0x1e6e2000 0x1000>;
238
239 pinctrl: pinctrl {
240 compatible = "aspeed,ast2500-pinctrl";
241 aspeed,external-nodes = <&gfx>, <&lhc>;
242
243 pinctrl_i2c3_default: i2c3_default {
244 function = "I2C3";
245 groups = "I2C3";
246 };
247
248 pinctrl_gpioh0_unbiased_default: gpioh0 {
249 pins = "A18";
250 bias-disable;
251 };
252 };
253 };