tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Frame Engine Ethernet controller
8
9maintainers:
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
12
13description:
14 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
15 have dual GMAC ports.
16
17properties:
18 compatible:
19 enum:
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
25 - mediatek,mt7981-eth
26 - mediatek,mt7986-eth
27 - mediatek,mt7988-eth
28 - ralink,rt5350-eth
29
30 reg:
31 maxItems: 1
32
33 clocks:
34 minItems: 2
35 maxItems: 24
36
37 clock-names:
38 minItems: 2
39 maxItems: 24
40
41 interrupts:
42 minItems: 1
43 maxItems: 8
44
45 interrupt-names:
46 minItems: 1
47 items:
48 - const: fe0
49 - const: fe1
50 - const: fe2
51 - const: fe3
52 - const: pdma0
53 - const: pdma1
54 - const: pdma2
55 - const: pdma3
56
57 power-domains:
58 maxItems: 1
59
60 resets:
61 maxItems: 3
62
63 reset-names:
64 items:
65 - const: fe
66 - const: gmac
67 - const: ppe
68
69 sram:
70 $ref: /schemas/types.yaml#/definitions/phandle
71 description: phandle to mmio SRAM
72
73 mediatek,ethsys:
74 $ref: /schemas/types.yaml#/definitions/phandle
75 description:
76 Phandle to the syscon node that handles the port setup.
77
78 cci-control-port: true
79
80 mediatek,hifsys:
81 $ref: /schemas/types.yaml#/definitions/phandle
82 description:
83 Phandle to the mediatek hifsys controller used to provide various clocks
84 and reset to the system.
85
86 mediatek,infracfg:
87 $ref: /schemas/types.yaml#/definitions/phandle
88 description:
89 Phandle to the syscon node that handles the path from GMAC to
90 PHY variants.
91
92 mediatek,pcie-mirror:
93 $ref: /schemas/types.yaml#/definitions/phandle
94 description:
95 Phandle to the mediatek pcie-mirror controller.
96
97 mediatek,pctl:
98 $ref: /schemas/types.yaml#/definitions/phandle
99 description:
100 Phandle to the syscon node that handles the ports slew rate and
101 driver current.
102
103 mediatek,sgmiisys:
104 $ref: /schemas/types.yaml#/definitions/phandle-array
105 minItems: 1
106 maxItems: 2
107 items:
108 maxItems: 1
109 description:
110 A list of phandle to the syscon node that handles the SGMII setup which is required for
111 those SoCs equipped with SGMII.
112
113 mediatek,wed:
114 $ref: /schemas/types.yaml#/definitions/phandle-array
115 minItems: 2
116 maxItems: 2
117 items:
118 maxItems: 1
119 description:
120 List of phandles to wireless ethernet dispatch nodes.
121
122 mediatek,wed-pcie:
123 $ref: /schemas/types.yaml#/definitions/phandle
124 description:
125 Phandle to the mediatek wed-pcie controller.
126
127 dma-coherent: true
128
129 mdio-bus:
130 $ref: mdio.yaml#
131 unevaluatedProperties: false
132
133 "#address-cells":
134 const: 1
135
136 "#size-cells":
137 const: 0
138
139allOf:
140 - $ref: ethernet-controller.yaml#
141 - if:
142 properties:
143 compatible:
144 contains:
145 enum:
146 - mediatek,mt2701-eth
147 - mediatek,mt7623-eth
148 then:
149 properties:
150 interrupts:
151 minItems: 3
152 maxItems: 3
153
154 interrupt-names:
155 minItems: 3
156 maxItems: 3
157
158 clocks:
159 minItems: 4
160 maxItems: 4
161
162 clock-names:
163 items:
164 - const: ethif
165 - const: esw
166 - const: gp1
167 - const: gp2
168
169 sram: false
170
171 mediatek,infracfg: false
172
173 mediatek,wed: false
174
175 mediatek,wed-pcie: false
176 else:
177 properties:
178 mediatek,pctl: false
179
180 - if:
181 properties:
182 compatible:
183 contains:
184 enum:
185 - mediatek,mt7621-eth
186 then:
187 properties:
188 interrupts:
189 maxItems: 1
190
191 interrupt-names:
192 maxItems: 1
193
194 clocks:
195 minItems: 2
196 maxItems: 2
197
198 clock-names:
199 items:
200 - const: ethif
201 - const: fe
202
203 sram: false
204
205 mediatek,infracfg: false
206
207 mediatek,wed: false
208
209 mediatek,wed-pcie: false
210
211 - if:
212 properties:
213 compatible:
214 contains:
215 const: mediatek,mt7622-eth
216 then:
217 properties:
218 interrupts:
219 minItems: 3
220 maxItems: 3
221
222 interrupt-names:
223 minItems: 3
224 maxItems: 3
225
226 clocks:
227 minItems: 11
228 maxItems: 11
229
230 clock-names:
231 items:
232 - const: ethif
233 - const: esw
234 - const: gp0
235 - const: gp1
236 - const: gp2
237 - const: sgmii_tx250m
238 - const: sgmii_rx250m
239 - const: sgmii_cdr_ref
240 - const: sgmii_cdr_fb
241 - const: sgmii_ck
242 - const: eth2pll
243
244 sram: false
245
246 mediatek,infracfg: false
247
248 mediatek,sgmiisys:
249 minItems: 1
250 maxItems: 1
251
252 mediatek,wed-pcie: false
253 else:
254 properties:
255 mediatek,pcie-mirror: false
256
257 - if:
258 properties:
259 compatible:
260 contains:
261 const: mediatek,mt7629-eth
262 then:
263 properties:
264 interrupts:
265 minItems: 3
266 maxItems: 3
267
268 interrupt-names:
269 minItems: 3
270 maxItems: 3
271
272 clocks:
273 minItems: 17
274 maxItems: 17
275
276 clock-names:
277 items:
278 - const: ethif
279 - const: sgmiitop
280 - const: esw
281 - const: gp0
282 - const: gp1
283 - const: gp2
284 - const: fe
285 - const: sgmii_tx250m
286 - const: sgmii_rx250m
287 - const: sgmii_cdr_ref
288 - const: sgmii_cdr_fb
289 - const: sgmii2_tx250m
290 - const: sgmii2_rx250m
291 - const: sgmii2_cdr_ref
292 - const: sgmii2_cdr_fb
293 - const: sgmii_ck
294 - const: eth2pll
295
296 sram: false
297
298 mediatek,sgmiisys:
299 minItems: 2
300 maxItems: 2
301
302 mediatek,wed: false
303
304 mediatek,wed-pcie: false
305
306 - if:
307 properties:
308 compatible:
309 contains:
310 const: mediatek,mt7981-eth
311 then:
312 properties:
313 interrupts:
314 minItems: 8
315
316 interrupt-names:
317 minItems: 8
318
319 clocks:
320 minItems: 15
321 maxItems: 15
322
323 clock-names:
324 items:
325 - const: fe
326 - const: gp2
327 - const: gp1
328 - const: wocpu0
329 - const: sgmii_ck
330 - const: sgmii_tx250m
331 - const: sgmii_rx250m
332 - const: sgmii_cdr_ref
333 - const: sgmii_cdr_fb
334 - const: sgmii2_tx250m
335 - const: sgmii2_rx250m
336 - const: sgmii2_cdr_ref
337 - const: sgmii2_cdr_fb
338 - const: netsys0
339 - const: netsys1
340
341 mediatek,infracfg: false
342
343 mediatek,sgmiisys:
344 minItems: 2
345 maxItems: 2
346
347 - if:
348 properties:
349 compatible:
350 contains:
351 const: mediatek,mt7986-eth
352 then:
353 properties:
354 interrupts:
355 minItems: 8
356
357 interrupt-names:
358 minItems: 8
359
360 clocks:
361 minItems: 15
362 maxItems: 15
363
364 clock-names:
365 items:
366 - const: fe
367 - const: gp2
368 - const: gp1
369 - const: wocpu1
370 - const: wocpu0
371 - const: sgmii_tx250m
372 - const: sgmii_rx250m
373 - const: sgmii_cdr_ref
374 - const: sgmii_cdr_fb
375 - const: sgmii2_tx250m
376 - const: sgmii2_rx250m
377 - const: sgmii2_cdr_ref
378 - const: sgmii2_cdr_fb
379 - const: netsys0
380 - const: netsys1
381
382 mediatek,infracfg: false
383
384 mediatek,sgmiisys:
385 minItems: 2
386 maxItems: 2
387
388 - if:
389 properties:
390 compatible:
391 contains:
392 const: mediatek,mt7988-eth
393 then:
394 properties:
395 interrupts:
396 minItems: 8
397
398 interrupt-names:
399 minItems: 8
400
401 clocks:
402 minItems: 24
403 maxItems: 24
404
405 clock-names:
406 items:
407 - const: crypto
408 - const: fe
409 - const: gp2
410 - const: gp1
411 - const: gp3
412 - const: ethwarp_wocpu2
413 - const: ethwarp_wocpu1
414 - const: ethwarp_wocpu0
415 - const: esw
416 - const: top_eth_gmii_sel
417 - const: top_eth_refck_50m_sel
418 - const: top_eth_sys_200m_sel
419 - const: top_eth_sys_sel
420 - const: top_eth_xgmii_sel
421 - const: top_eth_mii_sel
422 - const: top_netsys_sel
423 - const: top_netsys_500m_sel
424 - const: top_netsys_pao_2x_sel
425 - const: top_netsys_sync_250m_sel
426 - const: top_netsys_ppefb_250m_sel
427 - const: top_netsys_warp_sel
428 - const: xgp1
429 - const: xgp2
430 - const: xgp3
431
432patternProperties:
433 "^mac@[0-2]$":
434 type: object
435 unevaluatedProperties: false
436 allOf:
437 - $ref: ethernet-controller.yaml#
438 description:
439 Ethernet MAC node
440 properties:
441 compatible:
442 const: mediatek,eth-mac
443
444 reg:
445 maxItems: 1
446
447 required:
448 - reg
449 - compatible
450
451required:
452 - compatible
453 - reg
454 - interrupts
455 - clocks
456 - clock-names
457 - mediatek,ethsys
458
459unevaluatedProperties: false
460
461examples:
462 - |
463 #include <dt-bindings/interrupt-controller/arm-gic.h>
464 #include <dt-bindings/interrupt-controller/irq.h>
465 #include <dt-bindings/clock/mt7622-clk.h>
466 #include <dt-bindings/power/mt7622-power.h>
467
468 soc {
469 #address-cells = <2>;
470 #size-cells = <2>;
471
472 ethernet: ethernet@1b100000 {
473 compatible = "mediatek,mt7622-eth";
474 reg = <0 0x1b100000 0 0x20000>;
475 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
476 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
477 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
478 clocks = <&topckgen CLK_TOP_ETH_SEL>,
479 <ðsys CLK_ETH_ESW_EN>,
480 <ðsys CLK_ETH_GP0_EN>,
481 <ðsys CLK_ETH_GP1_EN>,
482 <ðsys CLK_ETH_GP2_EN>,
483 <&sgmiisys CLK_SGMII_TX250M_EN>,
484 <&sgmiisys CLK_SGMII_RX250M_EN>,
485 <&sgmiisys CLK_SGMII_CDR_REF>,
486 <&sgmiisys CLK_SGMII_CDR_FB>,
487 <&topckgen CLK_TOP_SGMIIPLL>,
488 <&apmixedsys CLK_APMIXED_ETH2PLL>;
489 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
490 "sgmii_tx250m", "sgmii_rx250m",
491 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
492 "eth2pll";
493 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
494 mediatek,ethsys = <ðsys>;
495 mediatek,sgmiisys = <&sgmiisys>;
496 cci-control-port = <&cci_control2>;
497 mediatek,pcie-mirror = <&pcie_mirror>;
498 mediatek,hifsys = <&hifsys>;
499 dma-coherent;
500
501 #address-cells = <1>;
502 #size-cells = <0>;
503
504 mdio0: mdio-bus {
505 #address-cells = <1>;
506 #size-cells = <0>;
507
508 phy0: ethernet-phy@0 {
509 reg = <0>;
510 };
511
512 phy1: ethernet-phy@1 {
513 reg = <1>;
514 };
515 };
516
517 gmac0: mac@0 {
518 compatible = "mediatek,eth-mac";
519 phy-mode = "rgmii";
520 phy-handle = <&phy0>;
521 reg = <0>;
522 };
523
524 gmac1: mac@1 {
525 compatible = "mediatek,eth-mac";
526 phy-mode = "rgmii";
527 phy-handle = <&phy1>;
528 reg = <1>;
529 };
530 };
531 };
532
533 - |
534 #include <dt-bindings/interrupt-controller/arm-gic.h>
535 #include <dt-bindings/interrupt-controller/irq.h>
536 #include <dt-bindings/clock/mt7622-clk.h>
537
538 soc {
539 #address-cells = <2>;
540 #size-cells = <2>;
541
542 eth: ethernet@15100000 {
543 #define CLK_ETH_FE_EN 0
544 #define CLK_ETH_WOCPU1_EN 3
545 #define CLK_ETH_WOCPU0_EN 4
546 #define CLK_TOP_NETSYS_SEL 43
547 #define CLK_TOP_NETSYS_500M_SEL 44
548 #define CLK_TOP_NETSYS_2X_SEL 46
549 #define CLK_TOP_SGM_325M_SEL 47
550 #define CLK_APMIXED_NET2PLL 1
551 #define CLK_APMIXED_SGMPLL 3
552
553 compatible = "mediatek,mt7986-eth";
554 reg = <0 0x15100000 0 0x80000>;
555 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <ðsys CLK_ETH_FE_EN>,
564 <ðsys CLK_ETH_GP2_EN>,
565 <ðsys CLK_ETH_GP1_EN>,
566 <ðsys CLK_ETH_WOCPU1_EN>,
567 <ðsys CLK_ETH_WOCPU0_EN>,
568 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
569 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
570 <&sgmiisys0 CLK_SGMII_CDR_REF>,
571 <&sgmiisys0 CLK_SGMII_CDR_FB>,
572 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
573 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
574 <&sgmiisys1 CLK_SGMII_CDR_REF>,
575 <&sgmiisys1 CLK_SGMII_CDR_FB>,
576 <&topckgen CLK_TOP_NETSYS_SEL>,
577 <&topckgen CLK_TOP_NETSYS_SEL>;
578 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
579 "sgmii_tx250m", "sgmii_rx250m",
580 "sgmii_cdr_ref", "sgmii_cdr_fb",
581 "sgmii2_tx250m", "sgmii2_rx250m",
582 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
583 "netsys0", "netsys1";
584 mediatek,ethsys = <ðsys>;
585 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
586 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
587 <&topckgen CLK_TOP_SGM_325M_SEL>;
588 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
589 <&apmixedsys CLK_APMIXED_SGMPLL>;
590
591 #address-cells = <1>;
592 #size-cells = <0>;
593
594 mdio: mdio-bus {
595 #address-cells = <1>;
596 #size-cells = <0>;
597
598 phy5: ethernet-phy@0 {
599 compatible = "ethernet-phy-id67c9.de0a";
600 phy-mode = "2500base-x";
601 reset-gpios = <&pio 6 1>;
602 reset-deassert-us = <20000>;
603 reg = <5>;
604 };
605
606 phy6: ethernet-phy@1 {
607 compatible = "ethernet-phy-id67c9.de0a";
608 phy-mode = "2500base-x";
609 reg = <6>;
610 };
611 };
612
613 mac0: mac@0 {
614 compatible = "mediatek,eth-mac";
615 phy-mode = "2500base-x";
616 phy-handle = <&phy5>;
617 reg = <0>;
618 };
619
620 mac1: mac@1 {
621 compatible = "mediatek,eth-mac";
622 phy-mode = "2500base-x";
623 phy-handle = <&phy6>;
624 reg = <1>;
625 };
626 };
627 };