tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/cdns,macb.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence MACB/GEM Ethernet controller
8
9maintainers:
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
12
13properties:
14 compatible:
15 oneOf:
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
20
21 - items:
22 - enum:
23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC
24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
25 - const: cdns,gem # Generic
26 deprecated: true
27
28 - items:
29 - enum:
30 - xlnx,versal-gem # Xilinx Versal
31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
33 - const: cdns,gem # Generic
34
35 - items:
36 - enum:
37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs
38 - cdns,sam9x60-macb # Microchip sam9x60 SoC
39 - microchip,mpfs-macb # Microchip PolarFire SoC
40 - const: cdns,macb # Generic
41
42 - items:
43 - enum:
44 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs
45 - enum:
46 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
47 - const: cdns,macb # Generic
48
49 - enum:
50 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs
51 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs
52 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs
53 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs
54 - cdns,np4-macb # NP4 SoC devices
55 - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface
56 - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
57 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC
58 - cdns,emac # Generic
59 - cdns,gem # Generic
60 - cdns,macb # Generic
61
62 - items:
63 - enum:
64 - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface
65 - microchip,sama7d65-gem # Microchip SAMA7D65 gigabit ethernet interface
66 - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
67
68 reg:
69 minItems: 1
70 items:
71 - description: Basic register set
72 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
73
74 interrupts:
75 minItems: 1
76 maxItems: 8
77 description: One interrupt per available hardware queue
78
79 clocks:
80 minItems: 1
81 maxItems: 5
82
83 clock-names:
84 minItems: 1
85 items:
86 - enum: [ ether_clk, hclk, pclk ]
87 - enum: [ hclk, pclk ]
88 - const: tx_clk
89 - enum: [ rx_clk, tsu_clk ]
90 - const: tsu_clk
91
92 local-mac-address: true
93
94 phy-mode: true
95
96 phy-handle: true
97
98 phys:
99 maxItems: 1
100
101 resets:
102 maxItems: 1
103 description:
104 Recommended with ZynqMP, specify reset control for this
105 controller instance with zynqmp-reset driver.
106
107 reset-names:
108 maxItems: 1
109
110 fixed-link: true
111
112 iommus:
113 maxItems: 1
114
115 power-domains:
116 maxItems: 1
117
118 cdns,refclk-ext:
119 type: boolean
120 description:
121 This selects if the REFCLK for RMII is provided by an external source.
122 For RGMII mode this selects if the 125MHz REF clock is provided by an external
123 source.
124
125 cdns,rx-watermark:
126 $ref: /schemas/types.yaml#/definitions/uint32
127 description:
128 When the receive partial store and forward mode is activated,
129 the receiver will only begin to forward the packet to the external
130 AHB or AXI slave when enough packet data is stored in the SRAM packet buffer.
131 rx-watermark corresponds to the number of SRAM buffer locations,
132 that need to be filled, before the forwarding process is activated.
133 Width of the SRAM is platform dependent, and can be 4, 8 or 16 bytes.
134
135 '#address-cells':
136 const: 1
137
138 '#size-cells':
139 const: 0
140
141 mdio:
142 type: object
143 description:
144 Node containing PHY children. If this node is not present, then PHYs will
145 be direct children.
146
147patternProperties:
148 "^ethernet-phy@[0-9a-f]$":
149 type: object
150 $ref: ethernet-phy.yaml#
151
152 properties:
153 reset-gpios: true
154
155 magic-packet:
156 type: boolean
157 deprecated: true
158 description:
159 Indicates that the hardware supports waking up via magic packet.
160
161 unevaluatedProperties: false
162
163required:
164 - compatible
165 - reg
166 - interrupts
167 - clocks
168 - clock-names
169 - phy-mode
170
171allOf:
172 - $ref: ethernet-controller.yaml#
173
174 - if:
175 not:
176 properties:
177 compatible:
178 contains:
179 const: sifive,fu540-c000-gem
180 then:
181 properties:
182 reg:
183 maxItems: 1
184
185unevaluatedProperties: false
186
187examples:
188 - |
189 macb0: ethernet@fffc4000 {
190 compatible = "cdns,macb";
191 reg = <0xfffc4000 0x4000>;
192 interrupts = <21>;
193 cdns,rx-watermark = <0x44>;
194 phy-mode = "rmii";
195 local-mac-address = [3a 0e 03 04 05 06];
196 clock-names = "pclk", "hclk", "tx_clk";
197 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
198 #address-cells = <1>;
199 #size-cells = <0>;
200
201 ethernet-phy@1 {
202 reg = <0x1>;
203 reset-gpios = <&pioE 6 1>;
204 };
205 };
206
207 - |
208 #include <dt-bindings/power/xlnx-zynqmp-power.h>
209 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
210 #include <dt-bindings/phy/phy.h>
211
212 bus {
213 #address-cells = <2>;
214 #size-cells = <2>;
215 gem1: ethernet@ff0c0000 {
216 compatible = "xlnx,zynqmp-gem", "cdns,gem";
217 interrupt-parent = <&gic>;
218 interrupts = <0 59 4>, <0 59 4>;
219 reg = <0x0 0xff0c0000 0x0 0x1000>;
220 clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>,
221 <&zynqmp_clk 51>, <&zynqmp_clk 50>,
222 <&zynqmp_clk 44>;
223 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 iommus = <&smmu 0x875>;
227 power-domains = <&zynqmp_firmware PD_ETH_1>;
228 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
229 reset-names = "gem1_rst";
230 phy-mode = "sgmii";
231 phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>;
232 fixed-link {
233 speed = <1000>;
234 full-duplex;
235 pause;
236 };
237 };
238 };