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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
8
9maintainers:
10 - Jia-Wei Chang <jia-wei.chang@mediatek.com>
11 - Johnson Wang <johnson.wang@mediatek.com>
12
13description: |
14 MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
15 MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
16 hardware. It can also optimize the voltage to reduce the power consumption.
17
18properties:
19 compatible:
20 oneOf:
21 - enum:
22 - mediatek,mt8183-cci
23 - mediatek,mt8186-cci
24 - items:
25 - enum:
26 - mediatek,mt7988-cci
27 - const: mediatek,mt8183-cci
28
29 clocks:
30 items:
31 - description:
32 The multiplexer for clock input of the bus.
33 - description:
34 A parent of "bus" clock which is used as an intermediate clock source
35 when the original clock source (PLL) is under transition and not
36 stable yet.
37
38 clock-names:
39 items:
40 - const: cci
41 - const: intermediate
42
43 operating-points-v2: true
44 opp-table:
45 type: object
46
47 proc-supply:
48 description:
49 Phandle of the regulator for CCI that provides the supply voltage.
50
51 sram-supply:
52 description:
53 Phandle of the regulator for sram of CCI that provides the supply
54 voltage. When it is present, the implementation needs to do
55 "voltage tracking" to step by step scale up/down Vproc and Vsram to fit
56 SoC specific needs. When absent, the voltage scaling flow is handled by
57 hardware, hence no software "voltage tracking" is needed.
58
59required:
60 - compatible
61 - clocks
62 - clock-names
63 - operating-points-v2
64 - proc-supply
65
66additionalProperties: false
67
68examples:
69 - |
70 #include <dt-bindings/clock/mt8183-clk.h>
71 cci: cci {
72 compatible = "mediatek,mt8183-cci";
73 clocks = <&mcucfg CLK_MCU_BUS_SEL>,
74 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
75 clock-names = "cci", "intermediate";
76 operating-points-v2 = <&cci_opp>;
77 proc-supply = <&mt6358_vproc12_reg>;
78 };
79
80 cci_opp: opp-table-cci {
81 compatible = "operating-points-v2";
82 opp-shared;
83 opp2_00: opp-273000000 {
84 opp-hz = /bits/ 64 <273000000>;
85 opp-microvolt = <650000>;
86 };
87 opp2_01: opp-338000000 {
88 opp-hz = /bits/ 64 <338000000>;
89 opp-microvolt = <687500>;
90 };
91 opp2_02: opp-403000000 {
92 opp-hz = /bits/ 64 <403000000>;
93 opp-microvolt = <718750>;
94 };
95 opp2_03: opp-463000000 {
96 opp-hz = /bits/ 64 <463000000>;
97 opp-microvolt = <756250>;
98 };
99 opp2_04: opp-546000000 {
100 opp-hz = /bits/ 64 <546000000>;
101 opp-microvolt = <800000>;
102 };
103 opp2_05: opp-624000000 {
104 opp-hz = /bits/ 64 <624000000>;
105 opp-microvolt = <818750>;
106 };
107 opp2_06: opp-689000000 {
108 opp-hz = /bits/ 64 <689000000>;
109 opp-microvolt = <850000>;
110 };
111 opp2_07: opp-767000000 {
112 opp-hz = /bits/ 64 <767000000>;
113 opp-microvolt = <868750>;
114 };
115 opp2_08: opp-845000000 {
116 opp-hz = /bits/ 64 <845000000>;
117 opp-microvolt = <893750>;
118 };
119 opp2_09: opp-871000000 {
120 opp-hz = /bits/ 64 <871000000>;
121 opp-microvolt = <906250>;
122 };
123 opp2_10: opp-923000000 {
124 opp-hz = /bits/ 64 <923000000>;
125 opp-microvolt = <931250>;
126 };
127 opp2_11: opp-962000000 {
128 opp-hz = /bits/ 64 <962000000>;
129 opp-microvolt = <943750>;
130 };
131 opp2_12: opp-1027000000 {
132 opp-hz = /bits/ 64 <1027000000>;
133 opp-microvolt = <975000>;
134 };
135 opp2_13: opp-1092000000 {
136 opp-hz = /bits/ 64 <1092000000>;
137 opp-microvolt = <1000000>;
138 };
139 opp2_14: opp-1144000000 {
140 opp-hz = /bits/ 64 <1144000000>;
141 opp-microvolt = <1025000>;
142 };
143 opp2_15: opp-1196000000 {
144 opp-hz = /bits/ 64 <1196000000>;
145 opp-microvolt = <1050000>;
146 };
147 };