tjh.dev
Linux kernel mirror (for testing)
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on X1E80100
8
9maintainers:
10 - Rajendra Nayak <quic_rjendra@quicinc.com>
11
12description: |
13 Qualcomm global clock control module provides the clocks, resets and power
14 domains on X1E80100
15
16 See also: include/dt-bindings/clock/qcom,x1e80100-gcc.h
17
18properties:
19 compatible:
20 oneOf:
21 - items:
22 - const: qcom,x1p42100-gcc
23 - const: qcom,x1e80100-gcc
24 - const: qcom,x1e80100-gcc
25
26 clocks:
27 items:
28 - description: Board XO source
29 - description: Sleep clock source
30 - description: PCIe 3 pipe clock
31 - description: PCIe 4 pipe clock
32 - description: PCIe 5 pipe clock
33 - description: PCIe 6a pipe clock
34 - description: PCIe 6b pipe clock
35 - description: USB QMP Phy 0 clock source
36 - description: USB QMP Phy 1 clock source
37 - description: USB QMP Phy 2 clock source
38
39 power-domains:
40 description:
41 A phandle and PM domain specifier for the CX power domain.
42 maxItems: 1
43
44required:
45 - compatible
46 - clocks
47 - power-domains
48 - '#power-domain-cells'
49
50allOf:
51 - $ref: qcom,gcc.yaml#
52
53unevaluatedProperties: false
54
55examples:
56 - |
57 #include <dt-bindings/power/qcom,rpmhpd.h>
58 clock-controller@100000 {
59 compatible = "qcom,x1e80100-gcc";
60 reg = <0x00100000 0x200000>;
61 clocks = <&bi_tcxo_div2>,
62 <&sleep_clk>,
63 <&pcie3_phy>,
64 <&pcie4_phy>,
65 <&pcie5_phy>,
66 <&pcie6a_phy>,
67 <&pcie6b_phy>,
68 <&usb_1_ss0_qmpphy 0>,
69 <&usb_1_ss1_qmpphy 1>,
70 <&usb_1_ss2_qmpphy 2>;
71 power-domains = <&rpmhpd RPMHPD_CX>;
72 #clock-cells = <1>;
73 #reset-cells = <1>;
74 #power-domain-cells = <1>;
75 };
76
77...