tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/pmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Performance Monitor Units
8
9maintainers:
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
12
13description: |+
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
16 representation in the device tree should be done as under:-
17
18properties:
19 compatible:
20 items:
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
25 - apple,firestorm-pmu
26 - apple,icestorm-pmu
27 - arm,armv8-pmuv3 # Only for s/w models
28 - arm,arm1136-pmu
29 - arm,arm1176-pmu
30 - arm,arm11mpcore-pmu
31 - arm,cortex-a5-pmu
32 - arm,cortex-a7-pmu
33 - arm,cortex-a8-pmu
34 - arm,cortex-a9-pmu
35 - arm,cortex-a12-pmu
36 - arm,cortex-a15-pmu
37 - arm,cortex-a17-pmu
38 - arm,cortex-a32-pmu
39 - arm,cortex-a34-pmu
40 - arm,cortex-a35-pmu
41 - arm,cortex-a53-pmu
42 - arm,cortex-a55-pmu
43 - arm,cortex-a57-pmu
44 - arm,cortex-a65-pmu
45 - arm,cortex-a72-pmu
46 - arm,cortex-a73-pmu
47 - arm,cortex-a75-pmu
48 - arm,cortex-a76-pmu
49 - arm,cortex-a77-pmu
50 - arm,cortex-a78-pmu
51 - arm,cortex-a510-pmu
52 - arm,cortex-a520-pmu
53 - arm,cortex-a710-pmu
54 - arm,cortex-a715-pmu
55 - arm,cortex-a720-pmu
56 - arm,cortex-a725-pmu
57 - arm,cortex-x1-pmu
58 - arm,cortex-x2-pmu
59 - arm,cortex-x3-pmu
60 - arm,cortex-x4-pmu
61 - arm,cortex-x925-pmu
62 - arm,neoverse-e1-pmu
63 - arm,neoverse-n1-pmu
64 - arm,neoverse-n2-pmu
65 - arm,neoverse-n3-pmu
66 - arm,neoverse-v1-pmu
67 - arm,neoverse-v2-pmu
68 - arm,neoverse-v3-pmu
69 - arm,neoverse-v3ae-pmu
70 - arm,rainier-pmu
71 - brcm,vulcan-pmu
72 - cavium,thunder-pmu
73 - nvidia,denver-pmu
74 - nvidia,carmel-pmu
75 - qcom,krait-pmu
76 - qcom,scorpion-pmu
77 - qcom,scorpion-mp-pmu
78 - samsung,mongoose-pmu
79
80 interrupts:
81 # Don't know how many CPUs, so no constraints to specify
82 description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
83
84 interrupt-affinity:
85 $ref: /schemas/types.yaml#/definitions/phandle-array
86 items:
87 maxItems: 1
88 description:
89 When using SPIs, specifies a list of phandles to CPU
90 nodes corresponding directly to the affinity of
91 the SPIs listed in the interrupts property.
92
93 When using a PPI, specifies a list of phandles to CPU
94 nodes corresponding to the set of CPUs which have
95 a PMU of this type signalling the PPI listed in the
96 interrupts property, unless this is already specified
97 by the PPI interrupt specifier itself (in which case
98 the interrupt-affinity property shouldn't be present).
99
100 This property should be present when there is more than
101 a single SPI.
102
103 qcom,no-pc-write:
104 type: boolean
105 description:
106 Indicates that this PMU doesn't support the 0xc and 0xd events.
107
108 secure-reg-access:
109 type: boolean
110 description:
111 Indicates that the ARMv7 Secure Debug Enable Register
112 (SDER) is accessible. This will cause the driver to do
113 any setup required that is only possible in ARMv7 secure
114 state. If not present the ARMv7 SDER will not be touched,
115 which means the PMU may fail to operate unless external
116 code (bootloader or security monitor) has performed the
117 appropriate initialisation. Note that this property is
118 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
119 in Non-secure state.
120
121required:
122 - compatible
123
124additionalProperties: false
125
126...