tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "nbio_v7_9.h"
25#include "amdgpu_ras.h"
26
27#include "nbio/nbio_7_9_0_offset.h"
28#include "nbio/nbio_7_9_0_sh_mask.h"
29#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
30#include <uapi/linux/kfd_ioctl.h>
31
32#define NPS_MODE_MASK 0x000000FFL
33
34static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
35{
36 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
37 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
38 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
39 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
40}
41
42static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev)
43{
44 u32 tmp;
45
46 tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0));
47 /* If it is VF or subrevision holds a non-zero value, that should be used */
48 if (tmp || amdgpu_sriov_vf(adev))
49 return tmp;
50
51 /* If discovery subrev is not updated, use register version */
52 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
53 tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0,
54 STRAP_ATI_REV_ID_DEV0_F0);
55
56 return tmp;
57}
58
59static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable)
60{
61 if (enable)
62 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
63 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
64 else
65 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
66}
67
68static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev)
69{
70 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
71}
72
73static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
74 bool use_doorbell, int doorbell_index, int doorbell_size)
75{
76 u32 doorbell_range = 0, doorbell_ctrl = 0;
77 int aid_id, dev_inst;
78
79 dev_inst = GET_INST(SDMA0, instance);
80 aid_id = adev->sdma.instance[instance].aid_id;
81
82 if (use_doorbell == false)
83 return;
84
85 doorbell_range =
86 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
87 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, doorbell_index);
88 doorbell_range =
89 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
90 BIF_DOORBELL0_RANGE_SIZE_ENTRY, doorbell_size);
91 doorbell_ctrl =
92 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
93 S2A_DOORBELL_PORT1_ENABLE, 1);
94 doorbell_ctrl =
95 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
96 S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size);
97
98 switch (dev_inst % adev->sdma.num_inst_per_aid) {
99 case 0:
100 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1,
101 4 * aid_id, doorbell_range);
102
103 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
104 S2A_DOORBELL_ENTRY_1_CTRL,
105 S2A_DOORBELL_PORT1_AWID, 0xe);
106 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
107 S2A_DOORBELL_ENTRY_1_CTRL,
108 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe);
109 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
110 S2A_DOORBELL_ENTRY_1_CTRL,
111 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
112 0x1);
113 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_1_CTRL,
114 aid_id, doorbell_ctrl);
115 break;
116 case 1:
117 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2,
118 4 * aid_id, doorbell_range);
119
120 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
121 S2A_DOORBELL_ENTRY_1_CTRL,
122 S2A_DOORBELL_PORT1_AWID, 0x8);
123 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
124 S2A_DOORBELL_ENTRY_1_CTRL,
125 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8);
126 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
127 S2A_DOORBELL_ENTRY_1_CTRL,
128 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
129 0x2);
130 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_2_CTRL,
131 aid_id, doorbell_ctrl);
132 break;
133 case 2:
134 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3,
135 4 * aid_id, doorbell_range);
136
137 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
138 S2A_DOORBELL_ENTRY_1_CTRL,
139 S2A_DOORBELL_PORT1_AWID, 0x9);
140 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
141 S2A_DOORBELL_ENTRY_1_CTRL,
142 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9);
143 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
144 S2A_DOORBELL_ENTRY_1_CTRL,
145 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
146 0x8);
147 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_5_CTRL,
148 aid_id, doorbell_ctrl);
149 break;
150 case 3:
151 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4,
152 4 * aid_id, doorbell_range);
153
154 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
155 S2A_DOORBELL_ENTRY_1_CTRL,
156 S2A_DOORBELL_PORT1_AWID, 0xa);
157 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
158 S2A_DOORBELL_ENTRY_1_CTRL,
159 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa);
160 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
161 S2A_DOORBELL_ENTRY_1_CTRL,
162 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
163 0x9);
164 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_6_CTRL,
165 aid_id, doorbell_ctrl);
166 break;
167 default:
168 break;
169 }
170}
171
172static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
173 int doorbell_index, int instance)
174{
175 u32 doorbell_range = 0, doorbell_ctrl = 0;
176 u32 aid_id = instance;
177 u32 range_size;
178
179 if (use_doorbell) {
180 range_size = (amdgpu_ip_version(adev, GC_HWIP, 0) ==
181 IP_VERSION(9, 5, 0)) ?
182 0xb : 0x9;
183 doorbell_range = REG_SET_FIELD(doorbell_range,
184 DOORBELL0_CTRL_ENTRY_0,
185 BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
186 doorbell_index);
187 doorbell_range = REG_SET_FIELD(doorbell_range,
188 DOORBELL0_CTRL_ENTRY_0,
189 BIF_DOORBELL0_RANGE_SIZE_ENTRY,
190 range_size);
191 if (aid_id)
192 doorbell_range = REG_SET_FIELD(doorbell_range,
193 DOORBELL0_CTRL_ENTRY_0,
194 DOORBELL0_FENCE_ENABLE_ENTRY,
195 0x4);
196
197 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
198 S2A_DOORBELL_ENTRY_1_CTRL,
199 S2A_DOORBELL_PORT1_ENABLE, 1);
200 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
201 S2A_DOORBELL_ENTRY_1_CTRL,
202 S2A_DOORBELL_PORT1_AWID, 0x4);
203 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
204 S2A_DOORBELL_ENTRY_1_CTRL,
205 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4);
206 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
207 S2A_DOORBELL_ENTRY_1_CTRL,
208 S2A_DOORBELL_PORT1_RANGE_SIZE, range_size);
209 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
210 S2A_DOORBELL_ENTRY_1_CTRL,
211 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4);
212
213 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
214 aid_id, doorbell_range);
215 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
216 aid_id, doorbell_ctrl);
217 } else {
218 doorbell_range = REG_SET_FIELD(doorbell_range,
219 DOORBELL0_CTRL_ENTRY_0,
220 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
221 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
222 S2A_DOORBELL_ENTRY_1_CTRL,
223 S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
224
225 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
226 aid_id, doorbell_range);
227 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
228 aid_id, doorbell_ctrl);
229 }
230}
231
232static void nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device *adev,
233 bool enable)
234{
235 /* Enable to allow doorbell pass thru on pre-silicon bare-metal */
236 WREG32_SOC15(NBIO, 0, regBIFC_DOORBELL_ACCESS_EN_PF, 0xfffff);
237 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,
238 BIF_DOORBELL_APER_EN, enable ? 1 : 0);
239}
240
241static void nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
242 bool enable)
243{
244 u32 tmp = 0;
245
246 if (enable) {
247 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
248 DOORBELL_SELFRING_GPA_APER_EN, 1) |
249 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
250 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
251 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
252 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
253
254 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
255 lower_32_bits(adev->doorbell.base));
256 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
257 upper_32_bits(adev->doorbell.base));
258 }
259
260 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
261}
262
263static void nbio_v7_9_ih_doorbell_range(struct amdgpu_device *adev,
264 bool use_doorbell, int doorbell_index)
265{
266 u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0;
267
268 if (use_doorbell) {
269 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
270 DOORBELL0_CTRL_ENTRY_0,
271 BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
272 doorbell_index);
273 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
274 DOORBELL0_CTRL_ENTRY_0,
275 BIF_DOORBELL0_RANGE_SIZE_ENTRY,
276 0x8);
277
278 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
279 S2A_DOORBELL_ENTRY_1_CTRL,
280 S2A_DOORBELL_PORT1_ENABLE, 1);
281 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
282 S2A_DOORBELL_ENTRY_1_CTRL,
283 S2A_DOORBELL_PORT1_AWID, 0);
284 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
285 S2A_DOORBELL_ENTRY_1_CTRL,
286 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0);
287 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
288 S2A_DOORBELL_ENTRY_1_CTRL,
289 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8);
290 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
291 S2A_DOORBELL_ENTRY_1_CTRL,
292 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0);
293 } else {
294 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
295 DOORBELL0_CTRL_ENTRY_0,
296 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
297 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
298 S2A_DOORBELL_ENTRY_1_CTRL,
299 S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
300 }
301
302 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range);
303 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl);
304}
305
306
307static void nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device *adev,
308 bool enable)
309{
310}
311
312static void nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device *adev,
313 bool enable)
314{
315}
316
317static void nbio_v7_9_get_clockgating_state(struct amdgpu_device *adev,
318 u64 *flags)
319{
320}
321
322static void nbio_v7_9_ih_control(struct amdgpu_device *adev)
323{
324 u32 interrupt_cntl;
325
326 /* setup interrupt control */
327 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
328 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
329 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
330 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
331 */
332 interrupt_cntl =
333 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
334 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
335 interrupt_cntl =
336 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
337 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
338}
339
340static u32 nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device *adev)
341{
342 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
343}
344
345static u32 nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device *adev)
346{
347 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
348}
349
350static u32 nbio_v7_9_get_pcie_index_offset(struct amdgpu_device *adev)
351{
352 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
353}
354
355static u32 nbio_v7_9_get_pcie_data_offset(struct amdgpu_device *adev)
356{
357 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
358}
359
360static u32 nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device *adev)
361{
362 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI);
363}
364
365const struct nbio_hdp_flush_reg nbio_v7_9_hdp_flush_reg = {
366 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
367 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
368 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
369 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
370 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
371 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
372 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
373 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
374 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
375 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
376 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
377 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
378 .ref_and_mask_sdma2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
379 .ref_and_mask_sdma3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
380 .ref_and_mask_sdma4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
381 .ref_and_mask_sdma5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
382 .ref_and_mask_sdma6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
383 .ref_and_mask_sdma7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
384};
385
386static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev,
387 bool enable)
388{
389 WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL,
390 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
391}
392
393static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev)
394{
395 u32 tmp, px;
396
397 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
398 px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
399 PARTITION_MODE);
400
401 return px;
402}
403
404static bool nbio_v7_9_is_nps_switch_requested(struct amdgpu_device *adev)
405{
406 u32 tmp;
407
408 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
409 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS,
410 CHANGE_STATUE);
411
412 /* 0x8 - NPS switch requested */
413 return (tmp == 0x8);
414}
415static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev,
416 u32 *supp_modes)
417{
418 u32 tmp;
419
420 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
421 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE);
422
423 if (supp_modes) {
424 *supp_modes =
425 RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP);
426 }
427
428 return ffs(tmp);
429}
430
431static void nbio_v7_9_init_registers(struct amdgpu_device *adev)
432{
433 u32 inst_mask;
434 int i;
435
436 WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE,
437 0xff & ~(adev->gfx.xcc_mask));
438
439 WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff);
440
441 inst_mask = adev->aid_mask & ~1U;
442 for_each_inst(i, inst_mask) {
443 WREG32_SOC15_EXT(NBIO, i, regXCC_DOORBELL_FENCE, i,
444 XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK);
445
446 }
447
448 if (!amdgpu_sriov_vf(adev)) {
449 u32 baco_cntl;
450 for_each_inst(i, adev->aid_mask) {
451 baco_cntl = RREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL);
452 if (baco_cntl & (BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK |
453 BIF_BX0_BACO_CNTL__BACO_EN_MASK)) {
454 baco_cntl &= ~(
455 BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK |
456 BIF_BX0_BACO_CNTL__BACO_EN_MASK);
457 dev_dbg(adev->dev,
458 "Unsetting baco dummy mode %x",
459 baco_cntl);
460 WREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL,
461 baco_cntl);
462 }
463 }
464 }
465}
466
467#define MMIO_REG_HOLE_OFFSET 0x1A000
468
469static void nbio_v7_9_set_reg_remap(struct amdgpu_device *adev)
470{
471 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
472 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
473 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
474 } else {
475 adev->rmmio_remap.reg_offset =
476 SOC15_REG_OFFSET(
477 NBIO, 0,
478 regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
479 << 2;
480 adev->rmmio_remap.bus_addr = 0;
481 }
482}
483
484const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
485 .get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
486 .get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
487 .get_pcie_index_offset = nbio_v7_9_get_pcie_index_offset,
488 .get_pcie_data_offset = nbio_v7_9_get_pcie_data_offset,
489 .get_pcie_index_hi_offset = nbio_v7_9_get_pcie_index_hi_offset,
490 .get_rev_id = nbio_v7_9_get_rev_id,
491 .mc_access_enable = nbio_v7_9_mc_access_enable,
492 .get_memsize = nbio_v7_9_get_memsize,
493 .sdma_doorbell_range = nbio_v7_9_sdma_doorbell_range,
494 .vcn_doorbell_range = nbio_v7_9_vcn_doorbell_range,
495 .enable_doorbell_aperture = nbio_v7_9_enable_doorbell_aperture,
496 .enable_doorbell_selfring_aperture = nbio_v7_9_enable_doorbell_selfring_aperture,
497 .ih_doorbell_range = nbio_v7_9_ih_doorbell_range,
498 .enable_doorbell_interrupt = nbio_v7_9_enable_doorbell_interrupt,
499 .update_medium_grain_clock_gating = nbio_v7_9_update_medium_grain_clock_gating,
500 .update_medium_grain_light_sleep = nbio_v7_9_update_medium_grain_light_sleep,
501 .get_clockgating_state = nbio_v7_9_get_clockgating_state,
502 .ih_control = nbio_v7_9_ih_control,
503 .remap_hdp_registers = nbio_v7_9_remap_hdp_registers,
504 .get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
505 .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
506 .is_nps_switch_requested = nbio_v7_9_is_nps_switch_requested,
507 .init_registers = nbio_v7_9_init_registers,
508 .set_reg_remap = nbio_v7_9_set_reg_remap,
509};
510
511static void nbio_v7_9_query_ras_error_count(struct amdgpu_device *adev,
512 void *ras_error_status)
513{
514}
515
516static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
517{
518 uint32_t bif_doorbell_intr_cntl;
519 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
520 struct ras_err_data err_data;
521 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
522
523 if (amdgpu_ras_error_data_init(&err_data))
524 return;
525
526 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
527
528 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
529 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
530 /* driver has to clear the interrupt status when bif ring is disabled */
531 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
532 BIF_BX0_BIF_DOORBELL_INT_CNTL,
533 RAS_CNTLR_INTERRUPT_CLEAR, 1);
534 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
535
536 if (!ras->disable_ras_err_cnt_harvest) {
537 /*
538 * clear error status after ras_controller_intr
539 * according to hw team and count ue number
540 * for query
541 */
542 nbio_v7_9_query_ras_error_count(adev, &err_data);
543
544 /* logging on error cnt and printing for awareness */
545 obj->err_data.ue_count += err_data.ue_count;
546 obj->err_data.ce_count += err_data.ce_count;
547
548 if (err_data.ce_count)
549 dev_info(adev->dev, "%ld correctable hardware "
550 "errors detected in %s block\n",
551 obj->err_data.ce_count,
552 get_ras_block_str(adev->nbio.ras_if));
553
554 if (err_data.ue_count)
555 dev_info(adev->dev, "%ld uncorrectable hardware "
556 "errors detected in %s block\n",
557 obj->err_data.ue_count,
558 get_ras_block_str(adev->nbio.ras_if));
559 }
560
561 dev_info(adev->dev, "RAS controller interrupt triggered "
562 "by NBIF error\n");
563 }
564
565 amdgpu_ras_error_data_fini(&err_data);
566}
567
568static void nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
569{
570 uint32_t bif_doorbell_intr_cntl;
571
572 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
573
574 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
575 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
576 /* driver has to clear the interrupt status when bif ring is disabled */
577 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
578 BIF_BX0_BIF_DOORBELL_INT_CNTL,
579 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
580
581 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
582
583 amdgpu_ras_global_ras_isr(adev);
584 }
585}
586
587static int nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device *adev,
588 struct amdgpu_irq_src *src,
589 unsigned type,
590 enum amdgpu_interrupt_state state)
591{
592 /* Dummy function, there is no initialization operation in driver */
593
594 return 0;
595}
596
597static int nbio_v7_9_process_ras_controller_irq(struct amdgpu_device *adev,
598 struct amdgpu_irq_src *source,
599 struct amdgpu_iv_entry *entry)
600{
601 /* By design, the ih cookie for ras_controller_irq should be written
602 * to BIFring instead of general iv ring. However, due to known bif ring
603 * hw bug, it has to be disabled. There is no chance the process function
604 * will be involked. Just left it as a dummy one.
605 */
606 return 0;
607}
608
609static int nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
610 struct amdgpu_irq_src *src,
611 unsigned type,
612 enum amdgpu_interrupt_state state)
613{
614 /* Dummy function, there is no initialization operation in driver */
615
616 return 0;
617}
618
619static int nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device *adev,
620 struct amdgpu_irq_src *source,
621 struct amdgpu_iv_entry *entry)
622{
623 /* By design, the ih cookie for err_event_athub_irq should be written
624 * to BIFring instead of general iv ring. However, due to known bif ring
625 * hw bug, it has to be disabled. There is no chance the process function
626 * will be involked. Just left it as a dummy one.
627 */
628 return 0;
629}
630
631static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_controller_irq_funcs = {
632 .set = nbio_v7_9_set_ras_controller_irq_state,
633 .process = nbio_v7_9_process_ras_controller_irq,
634};
635
636static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_err_event_athub_irq_funcs = {
637 .set = nbio_v7_9_set_ras_err_event_athub_irq_state,
638 .process = nbio_v7_9_process_err_event_athub_irq,
639};
640
641static int nbio_v7_9_init_ras_controller_interrupt (struct amdgpu_device *adev)
642{
643 int r;
644
645 /* init the irq funcs */
646 adev->nbio.ras_controller_irq.funcs =
647 &nbio_v7_9_ras_controller_irq_funcs;
648 adev->nbio.ras_controller_irq.num_types = 1;
649
650 /* register ras controller interrupt */
651 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
652 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
653 &adev->nbio.ras_controller_irq);
654
655 return r;
656}
657
658static int nbio_v7_9_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
659{
660
661 int r;
662
663 /* init the irq funcs */
664 adev->nbio.ras_err_event_athub_irq.funcs =
665 &nbio_v7_9_ras_err_event_athub_irq_funcs;
666 adev->nbio.ras_err_event_athub_irq.num_types = 1;
667
668 /* register ras err event athub interrupt */
669 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
670 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
671 &adev->nbio.ras_err_event_athub_irq);
672
673 return r;
674}
675
676const struct amdgpu_ras_block_hw_ops nbio_v7_9_ras_hw_ops = {
677 .query_ras_error_count = nbio_v7_9_query_ras_error_count,
678};
679
680struct amdgpu_nbio_ras nbio_v7_9_ras = {
681 .ras_block = {
682 .ras_comm = {
683 .name = "pcie_bif",
684 .block = AMDGPU_RAS_BLOCK__PCIE_BIF,
685 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
686 },
687 .hw_ops = &nbio_v7_9_ras_hw_ops,
688 .ras_late_init = amdgpu_nbio_ras_late_init,
689 },
690 .handle_ras_controller_intr_no_bifring = nbio_v7_9_handle_ras_controller_intr_no_bifring,
691 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring,
692 .init_ras_controller_interrupt = nbio_v7_9_init_ras_controller_interrupt,
693 .init_ras_err_event_athub_interrupt = nbio_v7_9_init_ras_err_event_athub_interrupt,
694};