tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_TTM_H__
25#define __AMDGPU_TTM_H__
26
27#include <linux/dma-direction.h>
28#include <drm/gpu_scheduler.h>
29#include <drm/ttm/ttm_placement.h>
30#include "amdgpu_vram_mgr.h"
31
32#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
33#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
34#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
35#define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3)
36#define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4)
37#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 5)
38
39#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
40#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
41
42extern const struct attribute_group amdgpu_vram_mgr_attr_group;
43extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
44
45struct hmm_range;
46
47struct amdgpu_gtt_mgr {
48 struct ttm_resource_manager manager;
49 struct drm_mm mm;
50 spinlock_t lock;
51};
52
53struct amdgpu_mman {
54 struct ttm_device bdev;
55 struct ttm_pool *ttm_pools;
56 bool initialized;
57 void __iomem *aper_base_kaddr;
58
59 /* buffer handling */
60 const struct amdgpu_buffer_funcs *buffer_funcs;
61 struct amdgpu_ring *buffer_funcs_ring;
62 bool buffer_funcs_enabled;
63
64 struct mutex gtt_window_lock;
65 /* High priority scheduler entity for buffer moves */
66 struct drm_sched_entity high_pr;
67 /* Low priority scheduler entity for VRAM clearing */
68 struct drm_sched_entity low_pr;
69
70 struct amdgpu_vram_mgr vram_mgr;
71 struct amdgpu_gtt_mgr gtt_mgr;
72 struct ttm_resource_manager preempt_mgr;
73
74 uint64_t stolen_vga_size;
75 struct amdgpu_bo *stolen_vga_memory;
76 uint64_t stolen_extended_size;
77 struct amdgpu_bo *stolen_extended_memory;
78 bool keep_stolen_vga_memory;
79
80 struct amdgpu_bo *stolen_reserved_memory;
81 uint64_t stolen_reserved_offset;
82 uint64_t stolen_reserved_size;
83
84 /* discovery */
85 uint8_t *discovery_bin;
86 uint32_t discovery_tmr_size;
87 /* fw reserved memory */
88 struct amdgpu_bo *fw_reserved_memory;
89 struct amdgpu_bo *fw_reserved_memory_extend;
90
91 /* firmware VRAM reservation */
92 u64 fw_vram_usage_start_offset;
93 u64 fw_vram_usage_size;
94 struct amdgpu_bo *fw_vram_usage_reserved_bo;
95 void *fw_vram_usage_va;
96
97 /* driver VRAM reservation */
98 u64 drv_vram_usage_start_offset;
99 u64 drv_vram_usage_size;
100 struct amdgpu_bo *drv_vram_usage_reserved_bo;
101 void *drv_vram_usage_va;
102
103 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */
104 struct amdgpu_bo *sdma_access_bo;
105 void *sdma_access_ptr;
106};
107
108struct amdgpu_copy_mem {
109 struct ttm_buffer_object *bo;
110 struct ttm_resource *mem;
111 unsigned long offset;
112};
113
114#define AMDGPU_COPY_FLAGS_TMZ (1 << 0)
115#define AMDGPU_COPY_FLAGS_READ_DECOMPRESSED (1 << 1)
116#define AMDGPU_COPY_FLAGS_WRITE_COMPRESSED (1 << 2)
117#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_SHIFT 3
118#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_MASK 0x03
119#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_SHIFT 5
120#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07
121#define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT 8
122#define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f
123#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT 14
124#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK 0x1
125
126#define AMDGPU_COPY_FLAGS_SET(field, value) \
127 (((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT)
128#define AMDGPU_COPY_FLAGS_GET(value, field) \
129 (((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) & AMDGPU_COPY_FLAGS_##field##_MASK)
130
131int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
132void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
133int amdgpu_preempt_mgr_init(struct amdgpu_device *adev);
134void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev);
135int amdgpu_vram_mgr_init(struct amdgpu_device *adev);
136void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
137
138bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
139void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr);
140
141uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man);
142
143u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
144int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
145 struct ttm_resource *mem,
146 u64 offset, u64 size,
147 struct device *dev,
148 enum dma_data_direction dir,
149 struct sg_table **sgt);
150void amdgpu_vram_mgr_free_sgt(struct device *dev,
151 enum dma_data_direction dir,
152 struct sg_table *sgt);
153uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr);
154int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr,
155 uint64_t start, uint64_t size);
156int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr,
157 uint64_t start);
158void amdgpu_vram_mgr_clear_reset_blocks(struct amdgpu_device *adev);
159
160bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
161 struct ttm_resource *res);
162
163int amdgpu_ttm_init(struct amdgpu_device *adev);
164void amdgpu_ttm_fini(struct amdgpu_device *adev);
165void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
166 bool enable);
167int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
168 uint64_t dst_offset, uint32_t byte_count,
169 struct dma_resv *resv,
170 struct dma_fence **fence, bool direct_submit,
171 bool vm_needs_flush, uint32_t copy_flags);
172int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
173 const struct amdgpu_copy_mem *src,
174 const struct amdgpu_copy_mem *dst,
175 uint64_t size, bool tmz,
176 struct dma_resv *resv,
177 struct dma_fence **f);
178int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
179 struct dma_resv *resv,
180 struct dma_fence **fence);
181int amdgpu_fill_buffer(struct amdgpu_bo *bo,
182 uint32_t src_data,
183 struct dma_resv *resv,
184 struct dma_fence **fence,
185 bool delayed);
186
187int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
188void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
189uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
190
191#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
192int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,
193 struct hmm_range **range);
194void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
195 struct hmm_range *range);
196bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
197 struct hmm_range *range);
198#else
199static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
200 struct page **pages,
201 struct hmm_range **range)
202{
203 return -EPERM;
204}
205static inline void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
206 struct hmm_range *range)
207{
208}
209static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
210 struct hmm_range *range)
211{
212 return false;
213}
214#endif
215
216void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
217int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
218 uint64_t *user_addr);
219int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
220 uint64_t addr, uint32_t flags);
221bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
222struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
223bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
224 unsigned long end, unsigned long *userptr);
225bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
226 int *last_invalidated);
227bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
228bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
229uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem);
230uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
231 struct ttm_resource *mem);
232int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type);
233
234void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
235
236#endif