tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Qualcomm QUSB2 phy controller
9
10maintainers:
11 - Wesley Cheng <quic_wcheng@quicinc.com>
12
13description:
14 QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
15
16properties:
17 compatible:
18 oneOf:
19 - items:
20 - enum:
21 - qcom,ipq5424-qusb2-phy
22 - qcom,ipq6018-qusb2-phy
23 - qcom,ipq8074-qusb2-phy
24 - qcom,ipq9574-qusb2-phy
25 - qcom,msm8953-qusb2-phy
26 - qcom,msm8996-qusb2-phy
27 - qcom,msm8998-qusb2-phy
28 - qcom,qcm2290-qusb2-phy
29 - qcom,qcs615-qusb2-phy
30 - qcom,sdm660-qusb2-phy
31 - qcom,sm4250-qusb2-phy
32 - qcom,sm6115-qusb2-phy
33 - items:
34 - enum:
35 - qcom,sc7180-qusb2-phy
36 - qcom,sdm670-qusb2-phy
37 - qcom,sdm845-qusb2-phy
38 - qcom,sm6350-qusb2-phy
39 - const: qcom,qusb2-v2-phy
40 reg:
41 maxItems: 1
42
43 "#phy-cells":
44 const: 0
45
46 clocks:
47 minItems: 2
48 items:
49 - description: phy config clock
50 - description: 19.2 MHz ref clk
51 - description: phy interface clock (Optional)
52
53 clock-names:
54 minItems: 2
55 items:
56 - const: cfg_ahb
57 - const: ref
58 - const: iface
59
60 vdd-supply:
61 description:
62 Phandle to 0.9V regulator supply to PHY digital circuit.
63
64 vdda-pll-supply:
65 description:
66 Phandle to 1.8V regulator supply to PHY refclk pll block.
67
68 vdda-phy-dpdm-supply:
69 description:
70 Phandle to 3.1V regulator supply to Dp/Dm port signals.
71
72 resets:
73 maxItems: 1
74 description:
75 Phandle to reset to phy block.
76
77 nvmem-cells:
78 maxItems: 1
79 description:
80 Phandle to nvmem cell that contains 'HS Tx trim'
81 tuning parameter value for qusb2 phy.
82
83 qcom,tcsr-syscon:
84 description:
85 Phandle to TCSR syscon register region.
86 $ref: /schemas/types.yaml#/definitions/phandle
87
88 qcom,imp-res-offset-value:
89 description:
90 It is a 6 bit value that specifies offset to be
91 added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
92 tuning parameter that may vary for different boards of same SOC.
93 $ref: /schemas/types.yaml#/definitions/uint32
94 minimum: 0
95 maximum: 63
96 default: 0
97
98 qcom,bias-ctrl-value:
99 description:
100 It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
101 tuning parameter that may vary for different boards of same SOC.
102 $ref: /schemas/types.yaml#/definitions/uint32
103 minimum: 0
104 maximum: 63
105 default: 32
106
107 qcom,charge-ctrl-value:
108 description:
109 It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
110 tuning parameter that may vary for different boards of same SOC.
111 $ref: /schemas/types.yaml#/definitions/uint32
112 minimum: 0
113 maximum: 3
114 default: 0
115
116 qcom,hstx-trim-value:
117 description:
118 It is a 4 bit value that specifies tuning for HSTX
119 output current.
120 Possible range is - 15mA to 24mA (stepsize of 600 uA).
121 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
122 $ref: /schemas/types.yaml#/definitions/uint32
123 minimum: 0
124 maximum: 15
125 default: 3
126
127 qcom,preemphasis-level:
128 description:
129 It is a 2 bit value that specifies pre-emphasis level.
130 Possible range is 0 to 15% (stepsize of 5%).
131 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
132 $ref: /schemas/types.yaml#/definitions/uint32
133 minimum: 0
134 maximum: 3
135 default: 2
136
137 qcom,preemphasis-width:
138 description:
139 It is a 1 bit value that specifies how long the HSTX
140 pre-emphasis (specified using qcom,preemphasis-level) must be in
141 effect. Duration could be half-bit of full-bit.
142 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
143 $ref: /schemas/types.yaml#/definitions/uint32
144 minimum: 0
145 maximum: 1
146 default: 0
147
148 qcom,hsdisc-trim-value:
149 description:
150 It is a 2 bit value tuning parameter that control disconnect
151 threshold and may vary for different boards of same SOC.
152 $ref: /schemas/types.yaml#/definitions/uint32
153 minimum: 0
154 maximum: 3
155 default: 0
156
157required:
158 - compatible
159 - reg
160 - "#phy-cells"
161 - clocks
162 - clock-names
163 - vdd-supply
164 - vdda-pll-supply
165 - vdda-phy-dpdm-supply
166 - resets
167
168allOf:
169 - if:
170 not:
171 properties:
172 compatible:
173 contains:
174 const: qcom,qusb2-v2-phy
175 then:
176 properties:
177 qcom,imp-res-offset-value: false
178 qcom,bias-ctrl-value: false
179 qcom,charge-ctrl-value: false
180 qcom,hstx-trim-value: false
181 qcom,preemphasis-level: false
182 qcom,preemphasis-width: false
183 qcom,hsdisc-trim-value: false
184
185additionalProperties: false
186
187examples:
188 - |
189 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
190 hsusb_phy: phy@7411000 {
191 compatible = "qcom,msm8996-qusb2-phy";
192 reg = <0x7411000 0x180>;
193 #phy-cells = <0>;
194
195 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
196 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
197 clock-names = "cfg_ahb", "ref";
198
199 vdd-supply = <&pm8994_l28>;
200 vdda-pll-supply = <&pm8994_l12>;
201 vdda-phy-dpdm-supply = <&pm8994_l24>;
202
203 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
204 nvmem-cells = <&qusb2p_hstx_trim>;
205 };