tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * RZ/G3E System controller (SYS) driver
4 *
5 * Copyright (C) 2025 Renesas Electronics Corp.
6 */
7
8#include <linux/bitfield.h>
9#include <linux/bits.h>
10#include <linux/device.h>
11#include <linux/init.h>
12#include <linux/io.h>
13
14#include "rz-sysc.h"
15
16/* Register Offsets */
17#define SYS_LSI_MODE 0x300
18/*
19 * BOOTPLLCA[1:0]
20 * [0,0] => 1.1GHZ
21 * [0,1] => 1.5GHZ
22 * [1,0] => 1.6GHZ
23 * [1,1] => 1.7GHZ
24 */
25#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)
26#define SYS_LSI_MODE_CA55_1_7GHZ 0x3
27
28#define SYS_LSI_PRR 0x308
29#define SYS_LSI_PRR_CA55_DIS BIT(8)
30#define SYS_LSI_PRR_NPU_DIS BIT(1)
31
32static void rzg3e_sys_print_id(struct device *dev,
33 void __iomem *sysc_base,
34 struct soc_device_attribute *soc_dev_attr)
35{
36 bool is_quad_core, npu_enabled;
37 u32 prr_val, mode_val;
38
39 prr_val = readl(sysc_base + SYS_LSI_PRR);
40 mode_val = readl(sysc_base + SYS_LSI_MODE);
41
42 /* Check CPU and NPU configuration */
43 is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS);
44 npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS);
45
46 dev_info(dev, "Detected Renesas %s Core %s %s Rev %s%s\n",
47 is_quad_core ? "Quad" : "Dual", soc_dev_attr->family,
48 soc_dev_attr->soc_id, soc_dev_attr->revision,
49 npu_enabled ? " with Ethos-U55" : "");
50
51 /* Check CA55 PLL configuration */
52 if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
53 dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
54}
55
56static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initconst = {
57 .family = "RZ/G3E",
58 .id = 0x8679447,
59 .devid_offset = 0x304,
60 .revision_mask = GENMASK(31, 28),
61 .specific_id_mask = GENMASK(27, 0),
62 .print_id = rzg3e_sys_print_id,
63};
64
65const struct rz_sysc_init_data rzg3e_sys_init_data = {
66 .soc_id_init_data = &rzg3e_sys_soc_id_init_data,
67};