tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

kernel / drivers / pinctrl / qcom / pinctrl-sar2130p.c
at v6.17-rc1 1504 lines 43 kB view raw
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Limited 5 */ 6 7#include <linux/module.h> 8#include <linux/of.h> 9#include <linux/platform_device.h> 10 11#include "pinctrl-msm.h" 12 13#define REG_SIZE 0x1000 14 15#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 16 { \ 17 .grp = PINCTRL_PINGROUP("gpio" #id, \ 18 gpio##id##_pins, \ 19 ARRAY_SIZE(gpio##id##_pins)), \ 20 .funcs = (int[]){ \ 21 msm_mux_gpio, /* gpio mode */ \ 22 msm_mux_##f1, \ 23 msm_mux_##f2, \ 24 msm_mux_##f3, \ 25 msm_mux_##f4, \ 26 msm_mux_##f5, \ 27 msm_mux_##f6, \ 28 msm_mux_##f7, \ 29 msm_mux_##f8, \ 30 msm_mux_##f9 \ 31 }, \ 32 .nfuncs = 10, \ 33 .ctl_reg = REG_SIZE * id, \ 34 .io_reg = 0x4 + REG_SIZE * id, \ 35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 36 .intr_status_reg = 0xc + REG_SIZE * id, \ 37 .intr_target_reg = 0x8 + REG_SIZE * id, \ 38 .mux_bit = 2, \ 39 .pull_bit = 0, \ 40 .drv_bit = 6, \ 41 .egpio_enable = 12, \ 42 .egpio_present = 11, \ 43 .oe_bit = 9, \ 44 .in_bit = 0, \ 45 .out_bit = 1, \ 46 .intr_enable_bit = 0, \ 47 .intr_status_bit = 0, \ 48 .intr_target_bit = 5, \ 49 .intr_target_kpss_val = 4, \ 50 .intr_raw_status_bit = 4, \ 51 .intr_polarity_bit = 1, \ 52 .intr_detection_bit = 2, \ 53 .intr_detection_width = 2, \ 54 } 55 56#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 57 { \ 58 .grp = PINCTRL_PINGROUP(#pg_name, \ 59 pg_name##_pins, \ 60 ARRAY_SIZE(pg_name##_pins)), \ 61 .ctl_reg = ctl, \ 62 .io_reg = 0, \ 63 .intr_cfg_reg = 0, \ 64 .intr_status_reg = 0, \ 65 .intr_target_reg = 0, \ 66 .mux_bit = -1, \ 67 .pull_bit = pull, \ 68 .drv_bit = drv, \ 69 .oe_bit = -1, \ 70 .in_bit = -1, \ 71 .out_bit = -1, \ 72 .intr_enable_bit = -1, \ 73 .intr_status_bit = -1, \ 74 .intr_target_bit = -1, \ 75 .intr_raw_status_bit = -1, \ 76 .intr_polarity_bit = -1, \ 77 .intr_detection_bit = -1, \ 78 .intr_detection_width = -1, \ 79 } 80 81static const struct pinctrl_pin_desc sar2130p_pins[] = { 82 PINCTRL_PIN(0, "GPIO_0"), 83 PINCTRL_PIN(1, "GPIO_1"), 84 PINCTRL_PIN(2, "GPIO_2"), 85 PINCTRL_PIN(3, "GPIO_3"), 86 PINCTRL_PIN(4, "GPIO_4"), 87 PINCTRL_PIN(5, "GPIO_5"), 88 PINCTRL_PIN(6, "GPIO_6"), 89 PINCTRL_PIN(7, "GPIO_7"), 90 PINCTRL_PIN(8, "GPIO_8"), 91 PINCTRL_PIN(9, "GPIO_9"), 92 PINCTRL_PIN(10, "GPIO_10"), 93 PINCTRL_PIN(11, "GPIO_11"), 94 PINCTRL_PIN(12, "GPIO_12"), 95 PINCTRL_PIN(13, "GPIO_13"), 96 PINCTRL_PIN(14, "GPIO_14"), 97 PINCTRL_PIN(15, "GPIO_15"), 98 PINCTRL_PIN(16, "GPIO_16"), 99 PINCTRL_PIN(17, "GPIO_17"), 100 PINCTRL_PIN(18, "GPIO_18"), 101 PINCTRL_PIN(19, "GPIO_19"), 102 PINCTRL_PIN(20, "GPIO_20"), 103 PINCTRL_PIN(21, "GPIO_21"), 104 PINCTRL_PIN(22, "GPIO_22"), 105 PINCTRL_PIN(23, "GPIO_23"), 106 PINCTRL_PIN(24, "GPIO_24"), 107 PINCTRL_PIN(25, "GPIO_25"), 108 PINCTRL_PIN(26, "GPIO_26"), 109 PINCTRL_PIN(27, "GPIO_27"), 110 PINCTRL_PIN(28, "GPIO_28"), 111 PINCTRL_PIN(29, "GPIO_29"), 112 PINCTRL_PIN(30, "GPIO_30"), 113 PINCTRL_PIN(31, "GPIO_31"), 114 PINCTRL_PIN(32, "GPIO_32"), 115 PINCTRL_PIN(33, "GPIO_33"), 116 PINCTRL_PIN(34, "GPIO_34"), 117 PINCTRL_PIN(35, "GPIO_35"), 118 PINCTRL_PIN(36, "GPIO_36"), 119 PINCTRL_PIN(37, "GPIO_37"), 120 PINCTRL_PIN(38, "GPIO_38"), 121 PINCTRL_PIN(39, "GPIO_39"), 122 PINCTRL_PIN(40, "GPIO_40"), 123 PINCTRL_PIN(41, "GPIO_41"), 124 PINCTRL_PIN(42, "GPIO_42"), 125 PINCTRL_PIN(43, "GPIO_43"), 126 PINCTRL_PIN(44, "GPIO_44"), 127 PINCTRL_PIN(45, "GPIO_45"), 128 PINCTRL_PIN(46, "GPIO_46"), 129 PINCTRL_PIN(47, "GPIO_47"), 130 PINCTRL_PIN(48, "GPIO_48"), 131 PINCTRL_PIN(49, "GPIO_49"), 132 PINCTRL_PIN(50, "GPIO_50"), 133 PINCTRL_PIN(51, "GPIO_51"), 134 PINCTRL_PIN(52, "GPIO_52"), 135 PINCTRL_PIN(53, "GPIO_53"), 136 PINCTRL_PIN(54, "GPIO_54"), 137 PINCTRL_PIN(55, "GPIO_55"), 138 PINCTRL_PIN(56, "GPIO_56"), 139 PINCTRL_PIN(57, "GPIO_57"), 140 PINCTRL_PIN(58, "GPIO_58"), 141 PINCTRL_PIN(59, "GPIO_59"), 142 PINCTRL_PIN(60, "GPIO_60"), 143 PINCTRL_PIN(61, "GPIO_61"), 144 PINCTRL_PIN(62, "GPIO_62"), 145 PINCTRL_PIN(63, "GPIO_63"), 146 PINCTRL_PIN(64, "GPIO_64"), 147 PINCTRL_PIN(65, "GPIO_65"), 148 PINCTRL_PIN(66, "GPIO_66"), 149 PINCTRL_PIN(67, "GPIO_67"), 150 PINCTRL_PIN(68, "GPIO_68"), 151 PINCTRL_PIN(69, "GPIO_69"), 152 PINCTRL_PIN(70, "GPIO_70"), 153 PINCTRL_PIN(71, "GPIO_71"), 154 PINCTRL_PIN(72, "GPIO_72"), 155 PINCTRL_PIN(73, "GPIO_73"), 156 PINCTRL_PIN(74, "GPIO_74"), 157 PINCTRL_PIN(75, "GPIO_75"), 158 PINCTRL_PIN(76, "GPIO_76"), 159 PINCTRL_PIN(77, "GPIO_77"), 160 PINCTRL_PIN(78, "GPIO_78"), 161 PINCTRL_PIN(79, "GPIO_79"), 162 PINCTRL_PIN(80, "GPIO_80"), 163 PINCTRL_PIN(81, "GPIO_81"), 164 PINCTRL_PIN(82, "GPIO_82"), 165 PINCTRL_PIN(83, "GPIO_83"), 166 PINCTRL_PIN(84, "GPIO_84"), 167 PINCTRL_PIN(85, "GPIO_85"), 168 PINCTRL_PIN(86, "GPIO_86"), 169 PINCTRL_PIN(87, "GPIO_87"), 170 PINCTRL_PIN(88, "GPIO_88"), 171 PINCTRL_PIN(89, "GPIO_89"), 172 PINCTRL_PIN(90, "GPIO_90"), 173 PINCTRL_PIN(91, "GPIO_91"), 174 PINCTRL_PIN(92, "GPIO_92"), 175 PINCTRL_PIN(93, "GPIO_93"), 176 PINCTRL_PIN(94, "GPIO_94"), 177 PINCTRL_PIN(95, "GPIO_95"), 178 PINCTRL_PIN(96, "GPIO_96"), 179 PINCTRL_PIN(97, "GPIO_97"), 180 PINCTRL_PIN(98, "GPIO_98"), 181 PINCTRL_PIN(99, "GPIO_99"), 182 PINCTRL_PIN(100, "GPIO_100"), 183 PINCTRL_PIN(101, "GPIO_101"), 184 PINCTRL_PIN(102, "GPIO_102"), 185 PINCTRL_PIN(103, "GPIO_103"), 186 PINCTRL_PIN(104, "GPIO_104"), 187 PINCTRL_PIN(105, "GPIO_105"), 188 PINCTRL_PIN(106, "GPIO_106"), 189 PINCTRL_PIN(107, "GPIO_107"), 190 PINCTRL_PIN(108, "GPIO_108"), 191 PINCTRL_PIN(109, "GPIO_109"), 192 PINCTRL_PIN(110, "GPIO_110"), 193 PINCTRL_PIN(111, "GPIO_111"), 194 PINCTRL_PIN(112, "GPIO_112"), 195 PINCTRL_PIN(113, "GPIO_113"), 196 PINCTRL_PIN(114, "GPIO_114"), 197 PINCTRL_PIN(115, "GPIO_115"), 198 PINCTRL_PIN(116, "GPIO_116"), 199 PINCTRL_PIN(117, "GPIO_117"), 200 PINCTRL_PIN(118, "GPIO_118"), 201 PINCTRL_PIN(119, "GPIO_119"), 202 PINCTRL_PIN(120, "GPIO_120"), 203 PINCTRL_PIN(121, "GPIO_121"), 204 PINCTRL_PIN(122, "GPIO_122"), 205 PINCTRL_PIN(123, "GPIO_123"), 206 PINCTRL_PIN(124, "GPIO_124"), 207 PINCTRL_PIN(125, "GPIO_125"), 208 PINCTRL_PIN(126, "GPIO_126"), 209 PINCTRL_PIN(127, "GPIO_127"), 210 PINCTRL_PIN(128, "GPIO_128"), 211 PINCTRL_PIN(129, "GPIO_129"), 212 PINCTRL_PIN(130, "GPIO_130"), 213 PINCTRL_PIN(131, "GPIO_131"), 214 PINCTRL_PIN(132, "GPIO_132"), 215 PINCTRL_PIN(133, "GPIO_133"), 216 PINCTRL_PIN(134, "GPIO_134"), 217 PINCTRL_PIN(135, "GPIO_135"), 218 PINCTRL_PIN(136, "GPIO_136"), 219 PINCTRL_PIN(137, "GPIO_137"), 220 PINCTRL_PIN(138, "GPIO_138"), 221 PINCTRL_PIN(139, "GPIO_139"), 222 PINCTRL_PIN(140, "GPIO_140"), 223 PINCTRL_PIN(141, "GPIO_141"), 224 PINCTRL_PIN(142, "GPIO_142"), 225 PINCTRL_PIN(143, "GPIO_143"), 226 PINCTRL_PIN(144, "GPIO_144"), 227 PINCTRL_PIN(145, "GPIO_145"), 228 PINCTRL_PIN(146, "GPIO_146"), 229 PINCTRL_PIN(147, "GPIO_147"), 230 PINCTRL_PIN(148, "GPIO_148"), 231 PINCTRL_PIN(149, "GPIO_149"), 232 PINCTRL_PIN(150, "GPIO_150"), 233 PINCTRL_PIN(151, "GPIO_151"), 234 PINCTRL_PIN(152, "GPIO_152"), 235 PINCTRL_PIN(153, "GPIO_153"), 236 PINCTRL_PIN(154, "GPIO_154"), 237 PINCTRL_PIN(155, "GPIO_155"), 238 PINCTRL_PIN(156, "SDC1_RCLK"), 239 PINCTRL_PIN(157, "SDC1_CLK"), 240 PINCTRL_PIN(158, "SDC1_CMD"), 241 PINCTRL_PIN(159, "SDC1_DATA"), 242}; 243 244#define DECLARE_MSM_GPIO_PINS(pin) \ 245 static const unsigned int gpio##pin##_pins[] = { pin } 246DECLARE_MSM_GPIO_PINS(0); 247DECLARE_MSM_GPIO_PINS(1); 248DECLARE_MSM_GPIO_PINS(2); 249DECLARE_MSM_GPIO_PINS(3); 250DECLARE_MSM_GPIO_PINS(4); 251DECLARE_MSM_GPIO_PINS(5); 252DECLARE_MSM_GPIO_PINS(6); 253DECLARE_MSM_GPIO_PINS(7); 254DECLARE_MSM_GPIO_PINS(8); 255DECLARE_MSM_GPIO_PINS(9); 256DECLARE_MSM_GPIO_PINS(10); 257DECLARE_MSM_GPIO_PINS(11); 258DECLARE_MSM_GPIO_PINS(12); 259DECLARE_MSM_GPIO_PINS(13); 260DECLARE_MSM_GPIO_PINS(14); 261DECLARE_MSM_GPIO_PINS(15); 262DECLARE_MSM_GPIO_PINS(16); 263DECLARE_MSM_GPIO_PINS(17); 264DECLARE_MSM_GPIO_PINS(18); 265DECLARE_MSM_GPIO_PINS(19); 266DECLARE_MSM_GPIO_PINS(20); 267DECLARE_MSM_GPIO_PINS(21); 268DECLARE_MSM_GPIO_PINS(22); 269DECLARE_MSM_GPIO_PINS(23); 270DECLARE_MSM_GPIO_PINS(24); 271DECLARE_MSM_GPIO_PINS(25); 272DECLARE_MSM_GPIO_PINS(26); 273DECLARE_MSM_GPIO_PINS(27); 274DECLARE_MSM_GPIO_PINS(28); 275DECLARE_MSM_GPIO_PINS(29); 276DECLARE_MSM_GPIO_PINS(30); 277DECLARE_MSM_GPIO_PINS(31); 278DECLARE_MSM_GPIO_PINS(32); 279DECLARE_MSM_GPIO_PINS(33); 280DECLARE_MSM_GPIO_PINS(34); 281DECLARE_MSM_GPIO_PINS(35); 282DECLARE_MSM_GPIO_PINS(36); 283DECLARE_MSM_GPIO_PINS(37); 284DECLARE_MSM_GPIO_PINS(38); 285DECLARE_MSM_GPIO_PINS(39); 286DECLARE_MSM_GPIO_PINS(40); 287DECLARE_MSM_GPIO_PINS(41); 288DECLARE_MSM_GPIO_PINS(42); 289DECLARE_MSM_GPIO_PINS(43); 290DECLARE_MSM_GPIO_PINS(44); 291DECLARE_MSM_GPIO_PINS(45); 292DECLARE_MSM_GPIO_PINS(46); 293DECLARE_MSM_GPIO_PINS(47); 294DECLARE_MSM_GPIO_PINS(48); 295DECLARE_MSM_GPIO_PINS(49); 296DECLARE_MSM_GPIO_PINS(50); 297DECLARE_MSM_GPIO_PINS(51); 298DECLARE_MSM_GPIO_PINS(52); 299DECLARE_MSM_GPIO_PINS(53); 300DECLARE_MSM_GPIO_PINS(54); 301DECLARE_MSM_GPIO_PINS(55); 302DECLARE_MSM_GPIO_PINS(56); 303DECLARE_MSM_GPIO_PINS(57); 304DECLARE_MSM_GPIO_PINS(58); 305DECLARE_MSM_GPIO_PINS(59); 306DECLARE_MSM_GPIO_PINS(60); 307DECLARE_MSM_GPIO_PINS(61); 308DECLARE_MSM_GPIO_PINS(62); 309DECLARE_MSM_GPIO_PINS(63); 310DECLARE_MSM_GPIO_PINS(64); 311DECLARE_MSM_GPIO_PINS(65); 312DECLARE_MSM_GPIO_PINS(66); 313DECLARE_MSM_GPIO_PINS(67); 314DECLARE_MSM_GPIO_PINS(68); 315DECLARE_MSM_GPIO_PINS(69); 316DECLARE_MSM_GPIO_PINS(70); 317DECLARE_MSM_GPIO_PINS(71); 318DECLARE_MSM_GPIO_PINS(72); 319DECLARE_MSM_GPIO_PINS(73); 320DECLARE_MSM_GPIO_PINS(74); 321DECLARE_MSM_GPIO_PINS(75); 322DECLARE_MSM_GPIO_PINS(76); 323DECLARE_MSM_GPIO_PINS(77); 324DECLARE_MSM_GPIO_PINS(78); 325DECLARE_MSM_GPIO_PINS(79); 326DECLARE_MSM_GPIO_PINS(80); 327DECLARE_MSM_GPIO_PINS(81); 328DECLARE_MSM_GPIO_PINS(82); 329DECLARE_MSM_GPIO_PINS(83); 330DECLARE_MSM_GPIO_PINS(84); 331DECLARE_MSM_GPIO_PINS(85); 332DECLARE_MSM_GPIO_PINS(86); 333DECLARE_MSM_GPIO_PINS(87); 334DECLARE_MSM_GPIO_PINS(88); 335DECLARE_MSM_GPIO_PINS(89); 336DECLARE_MSM_GPIO_PINS(90); 337DECLARE_MSM_GPIO_PINS(91); 338DECLARE_MSM_GPIO_PINS(92); 339DECLARE_MSM_GPIO_PINS(93); 340DECLARE_MSM_GPIO_PINS(94); 341DECLARE_MSM_GPIO_PINS(95); 342DECLARE_MSM_GPIO_PINS(96); 343DECLARE_MSM_GPIO_PINS(97); 344DECLARE_MSM_GPIO_PINS(98); 345DECLARE_MSM_GPIO_PINS(99); 346DECLARE_MSM_GPIO_PINS(100); 347DECLARE_MSM_GPIO_PINS(101); 348DECLARE_MSM_GPIO_PINS(102); 349DECLARE_MSM_GPIO_PINS(103); 350DECLARE_MSM_GPIO_PINS(104); 351DECLARE_MSM_GPIO_PINS(105); 352DECLARE_MSM_GPIO_PINS(106); 353DECLARE_MSM_GPIO_PINS(107); 354DECLARE_MSM_GPIO_PINS(108); 355DECLARE_MSM_GPIO_PINS(109); 356DECLARE_MSM_GPIO_PINS(110); 357DECLARE_MSM_GPIO_PINS(111); 358DECLARE_MSM_GPIO_PINS(112); 359DECLARE_MSM_GPIO_PINS(113); 360DECLARE_MSM_GPIO_PINS(114); 361DECLARE_MSM_GPIO_PINS(115); 362DECLARE_MSM_GPIO_PINS(116); 363DECLARE_MSM_GPIO_PINS(117); 364DECLARE_MSM_GPIO_PINS(118); 365DECLARE_MSM_GPIO_PINS(119); 366DECLARE_MSM_GPIO_PINS(120); 367DECLARE_MSM_GPIO_PINS(121); 368DECLARE_MSM_GPIO_PINS(122); 369DECLARE_MSM_GPIO_PINS(123); 370DECLARE_MSM_GPIO_PINS(124); 371DECLARE_MSM_GPIO_PINS(125); 372DECLARE_MSM_GPIO_PINS(126); 373DECLARE_MSM_GPIO_PINS(127); 374DECLARE_MSM_GPIO_PINS(128); 375DECLARE_MSM_GPIO_PINS(129); 376DECLARE_MSM_GPIO_PINS(130); 377DECLARE_MSM_GPIO_PINS(131); 378DECLARE_MSM_GPIO_PINS(132); 379DECLARE_MSM_GPIO_PINS(133); 380DECLARE_MSM_GPIO_PINS(134); 381DECLARE_MSM_GPIO_PINS(135); 382DECLARE_MSM_GPIO_PINS(136); 383DECLARE_MSM_GPIO_PINS(137); 384DECLARE_MSM_GPIO_PINS(138); 385DECLARE_MSM_GPIO_PINS(139); 386DECLARE_MSM_GPIO_PINS(140); 387DECLARE_MSM_GPIO_PINS(141); 388DECLARE_MSM_GPIO_PINS(142); 389DECLARE_MSM_GPIO_PINS(143); 390DECLARE_MSM_GPIO_PINS(144); 391DECLARE_MSM_GPIO_PINS(145); 392DECLARE_MSM_GPIO_PINS(146); 393DECLARE_MSM_GPIO_PINS(147); 394DECLARE_MSM_GPIO_PINS(148); 395DECLARE_MSM_GPIO_PINS(149); 396DECLARE_MSM_GPIO_PINS(150); 397DECLARE_MSM_GPIO_PINS(151); 398DECLARE_MSM_GPIO_PINS(152); 399DECLARE_MSM_GPIO_PINS(153); 400DECLARE_MSM_GPIO_PINS(154); 401DECLARE_MSM_GPIO_PINS(155); 402 403static const unsigned int sdc1_rclk_pins[] = { 156 }; 404static const unsigned int sdc1_clk_pins[] = { 157 }; 405static const unsigned int sdc1_cmd_pins[] = { 158 }; 406static const unsigned int sdc1_data_pins[] = { 159 }; 407 408enum sar2130p_functions { 409 msm_mux_gpio, 410 msm_mux_aoss_cti, 411 msm_mux_atest_char, 412 msm_mux_atest_char0, 413 msm_mux_atest_char1, 414 msm_mux_atest_char2, 415 msm_mux_atest_char3, 416 msm_mux_atest_usb0, 417 msm_mux_atest_usb00, 418 msm_mux_atest_usb01, 419 msm_mux_atest_usb02, 420 msm_mux_atest_usb03, 421 msm_mux_audio_ref, 422 msm_mux_cam_mclk, 423 msm_mux_cci_async, 424 msm_mux_cci_i2c, 425 msm_mux_cci_timer0, 426 msm_mux_cci_timer1, 427 msm_mux_cci_timer2, 428 msm_mux_cci_timer3, 429 msm_mux_cci_timer4, 430 msm_mux_cri_trng, 431 msm_mux_cri_trng0, 432 msm_mux_cri_trng1, 433 msm_mux_dbg_out, 434 msm_mux_ddr_bist, 435 msm_mux_ddr_pxi0, 436 msm_mux_ddr_pxi1, 437 msm_mux_ddr_pxi2, 438 msm_mux_ddr_pxi3, 439 msm_mux_dp0_hot, 440 msm_mux_ext_mclk0, 441 msm_mux_ext_mclk1, 442 msm_mux_gcc_gp1, 443 msm_mux_gcc_gp2, 444 msm_mux_gcc_gp3, 445 msm_mux_host2wlan_sol, 446 msm_mux_i2s0_data0, 447 msm_mux_i2s0_data1, 448 msm_mux_i2s0_sck, 449 msm_mux_i2s0_ws, 450 msm_mux_ibi_i3c, 451 msm_mux_jitter_bist, 452 msm_mux_mdp_vsync, 453 msm_mux_mdp_vsync0, 454 msm_mux_mdp_vsync1, 455 msm_mux_mdp_vsync2, 456 msm_mux_mdp_vsync3, 457 msm_mux_pcie0_clkreqn, 458 msm_mux_pcie1_clkreqn, 459 msm_mux_phase_flag0, 460 msm_mux_phase_flag1, 461 msm_mux_phase_flag10, 462 msm_mux_phase_flag11, 463 msm_mux_phase_flag12, 464 msm_mux_phase_flag13, 465 msm_mux_phase_flag14, 466 msm_mux_phase_flag15, 467 msm_mux_phase_flag16, 468 msm_mux_phase_flag17, 469 msm_mux_phase_flag18, 470 msm_mux_phase_flag19, 471 msm_mux_phase_flag2, 472 msm_mux_phase_flag20, 473 msm_mux_phase_flag21, 474 msm_mux_phase_flag22, 475 msm_mux_phase_flag23, 476 msm_mux_phase_flag24, 477 msm_mux_phase_flag25, 478 msm_mux_phase_flag26, 479 msm_mux_phase_flag27, 480 msm_mux_phase_flag28, 481 msm_mux_phase_flag29, 482 msm_mux_phase_flag3, 483 msm_mux_phase_flag30, 484 msm_mux_phase_flag31, 485 msm_mux_phase_flag4, 486 msm_mux_phase_flag5, 487 msm_mux_phase_flag6, 488 msm_mux_phase_flag7, 489 msm_mux_phase_flag8, 490 msm_mux_phase_flag9, 491 msm_mux_pll_bist, 492 msm_mux_pll_clk, 493 msm_mux_prng_rosc0, 494 msm_mux_prng_rosc1, 495 msm_mux_prng_rosc2, 496 msm_mux_prng_rosc3, 497 msm_mux_qdss_cti, 498 msm_mux_qdss_gpio, 499 msm_mux_qdss_gpio0, 500 msm_mux_qdss_gpio1, 501 msm_mux_qdss_gpio10, 502 msm_mux_qdss_gpio11, 503 msm_mux_qdss_gpio12, 504 msm_mux_qdss_gpio13, 505 msm_mux_qdss_gpio14, 506 msm_mux_qdss_gpio15, 507 msm_mux_qdss_gpio2, 508 msm_mux_qdss_gpio3, 509 msm_mux_qdss_gpio4, 510 msm_mux_qdss_gpio5, 511 msm_mux_qdss_gpio6, 512 msm_mux_qdss_gpio7, 513 msm_mux_qdss_gpio8, 514 msm_mux_qdss_gpio9, 515 msm_mux_qspi0, 516 msm_mux_qspi1, 517 msm_mux_qspi2, 518 msm_mux_qspi3, 519 msm_mux_qspi_clk, 520 msm_mux_qspi_cs0, 521 msm_mux_qspi_cs1, 522 msm_mux_qup0, 523 msm_mux_qup1, 524 msm_mux_qup2, 525 msm_mux_qup3, 526 msm_mux_qup4, 527 msm_mux_qup5, 528 msm_mux_qup6, 529 msm_mux_qup7, 530 msm_mux_qup8, 531 msm_mux_qup9, 532 msm_mux_qup10, 533 msm_mux_qup11, 534 msm_mux_tb_trig, 535 msm_mux_tgu_ch0, 536 msm_mux_tgu_ch1, 537 msm_mux_tgu_ch2, 538 msm_mux_tgu_ch3, 539 msm_mux_tmess_prng0, 540 msm_mux_tmess_prng1, 541 msm_mux_tmess_prng2, 542 msm_mux_tmess_prng3, 543 msm_mux_tsense_pwm1, 544 msm_mux_tsense_pwm2, 545 msm_mux_usb0_phy, 546 msm_mux_vsense_trigger, 547 msm_mux__, 548}; 549 550static const char * const gpio_groups[] = { 551 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 552 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 553 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 554 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 555 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 556 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 557 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 558 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 559 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 560 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 561 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 562 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 563 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 564 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 565 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 566 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 567 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 568 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 569 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", 570 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", 571 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", 572 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", 573 "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", 574 "gpio153", "gpio154", "gpio155", 575}; 576 577static const char * const aoss_cti_groups[] = { 578 "gpio20", "gpio21", "gpio22", "gpio23", 579}; 580 581static const char * const atest_char_groups[] = { 582 "gpio45", 583}; 584 585static const char * const atest_char0_groups[] = { 586 "gpio90", 587}; 588 589static const char * const atest_char1_groups[] = { 590 "gpio89", 591}; 592 593static const char * const atest_char2_groups[] = { 594 "gpio88", 595}; 596 597static const char * const atest_char3_groups[] = { 598 "gpio87", 599}; 600 601static const char * const atest_usb0_groups[] = { 602 "gpio26", 603}; 604 605static const char * const atest_usb00_groups[] = { 606 "gpio110", 607}; 608 609static const char * const atest_usb01_groups[] = { 610 "gpio109", 611}; 612 613static const char * const atest_usb02_groups[] = { 614 "gpio27", 615}; 616 617static const char * const atest_usb03_groups[] = { 618 "gpio60", 619}; 620 621static const char * const audio_ref_groups[] = { 622 "gpio103", 623}; 624 625static const char * const cam_mclk_groups[] = { 626 "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", 627 "gpio76", 628}; 629 630static const char * const cci_async_groups[] = { 631 "gpio80", "gpio81", "gpio82", 632}; 633 634static const char * const cci_i2c_groups[] = { 635 "gpio67", "gpio68", "gpio78", "gpio79", "gpio80", "gpio81", "gpio83", 636 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", 637 "gpio91", "gpio92", 638}; 639 640static const char * const cci_timer0_groups[] = { 641 "gpio77", 642}; 643 644static const char * const cci_timer1_groups[] = { 645 "gpio78", 646}; 647 648static const char * const cci_timer2_groups[] = { 649 "gpio79", 650}; 651 652static const char * const cci_timer3_groups[] = { 653 "gpio80", 654}; 655 656static const char * const cci_timer4_groups[] = { 657 "gpio81", 658}; 659 660static const char * const cri_trng_groups[] = { 661 "gpio60", 662}; 663 664static const char * const cri_trng0_groups[] = { 665 "gpio70", 666}; 667 668static const char * const cri_trng1_groups[] = { 669 "gpio71", 670}; 671 672static const char * const dbg_out_groups[] = { 673 "gpio59", 674}; 675 676static const char * const ddr_bist_groups[] = { 677 "gpio4", "gpio5", "gpio100", "gpio103", 678}; 679 680static const char * const ddr_pxi0_groups[] = { 681 "gpio56", "gpio57", 682}; 683 684static const char * const ddr_pxi1_groups[] = { 685 "gpio41", "gpio45", 686}; 687 688static const char * const ddr_pxi2_groups[] = { 689 "gpio48", "gpio55", 690}; 691 692static const char * const ddr_pxi3_groups[] = { 693 "gpio46", "gpio47", 694}; 695 696static const char * const dp0_hot_groups[] = { 697 "gpio35", "gpio103", 698}; 699 700static const char * const ext_mclk0_groups[] = { 701 "gpio104", 702}; 703 704static const char * const ext_mclk1_groups[] = { 705 "gpio103", 706}; 707 708static const char * const gcc_gp1_groups[] = { 709 "gpio129", "gpio132", 710}; 711 712static const char * const gcc_gp2_groups[] = { 713 "gpio130", "gpio135", 714}; 715 716static const char * const gcc_gp3_groups[] = { 717 "gpio131", "gpio136", 718}; 719 720static const char * const host2wlan_sol_groups[] = { 721 "gpio111", 722}; 723 724static const char * const i2s0_data0_groups[] = { 725 "gpio106", 726}; 727 728static const char * const i2s0_data1_groups[] = { 729 "gpio107", 730}; 731 732static const char * const i2s0_sck_groups[] = { 733 "gpio105", 734}; 735 736static const char * const i2s0_ws_groups[] = { 737 "gpio108", 738}; 739 740static const char * const ibi_i3c_groups[] = { 741 "gpio0", "gpio1", "gpio91", "gpio92", 742}; 743 744static const char * const jitter_bist_groups[] = { 745 "gpio0", 746}; 747 748static const char * const mdp_vsync_groups[] = { 749 "gpio12", "gpio13", "gpio41", "gpio49", "gpio50", 750}; 751 752static const char * const mdp_vsync0_groups[] = { 753 "gpio49", 754}; 755 756static const char * const mdp_vsync1_groups[] = { 757 "gpio49", 758}; 759 760static const char * const mdp_vsync2_groups[] = { 761 "gpio50", 762}; 763 764static const char * const mdp_vsync3_groups[] = { 765 "gpio50", 766}; 767 768static const char * const pcie0_clkreqn_groups[] = { 769 "gpio56", 770}; 771 772static const char * const pcie1_clkreqn_groups[] = { 773 "gpio59", 774}; 775 776static const char * const phase_flag0_groups[] = { 777 "gpio133", 778}; 779 780static const char * const phase_flag1_groups[] = { 781 "gpio128", 782}; 783 784static const char * const phase_flag10_groups[] = { 785 "gpio94", 786}; 787 788static const char * const phase_flag11_groups[] = { 789 "gpio93", 790}; 791 792static const char * const phase_flag12_groups[] = { 793 "gpio134", 794}; 795 796static const char * const phase_flag13_groups[] = { 797 "gpio139", 798}; 799 800static const char * const phase_flag14_groups[] = { 801 "gpio138", 802}; 803 804static const char * const phase_flag15_groups[] = { 805 "gpio137", 806}; 807 808static const char * const phase_flag16_groups[] = { 809 "gpio62", 810}; 811 812static const char * const phase_flag17_groups[] = { 813 "gpio61", 814}; 815 816static const char * const phase_flag18_groups[] = { 817 "gpio41", 818}; 819 820static const char * const phase_flag19_groups[] = { 821 "gpio23", 822}; 823 824static const char * const phase_flag2_groups[] = { 825 "gpio127", 826}; 827 828static const char * const phase_flag20_groups[] = { 829 "gpio22", 830}; 831 832static const char * const phase_flag21_groups[] = { 833 "gpio21", 834}; 835 836static const char * const phase_flag22_groups[] = { 837 "gpio19", 838}; 839 840static const char * const phase_flag23_groups[] = { 841 "gpio18", 842}; 843 844static const char * const phase_flag24_groups[] = { 845 "gpio17", 846}; 847 848static const char * const phase_flag25_groups[] = { 849 "gpio16", 850}; 851 852static const char * const phase_flag26_groups[] = { 853 "gpio13", 854}; 855 856static const char * const phase_flag27_groups[] = { 857 "gpio12", 858}; 859 860static const char * const phase_flag28_groups[] = { 861 "gpio3", 862}; 863 864static const char * const phase_flag29_groups[] = { 865 "gpio2", 866}; 867 868static const char * const phase_flag3_groups[] = { 869 "gpio126", 870}; 871 872static const char * const phase_flag30_groups[] = { 873 "gpio149", 874}; 875 876static const char * const phase_flag31_groups[] = { 877 "gpio148", 878}; 879 880static const char * const phase_flag4_groups[] = { 881 "gpio151", 882}; 883 884static const char * const phase_flag5_groups[] = { 885 "gpio150", 886}; 887 888static const char * const phase_flag6_groups[] = { 889 "gpio98", 890}; 891 892static const char * const phase_flag7_groups[] = { 893 "gpio97", 894}; 895 896static const char * const phase_flag8_groups[] = { 897 "gpio96", 898}; 899 900static const char * const phase_flag9_groups[] = { 901 "gpio95", 902}; 903 904static const char * const pll_bist_groups[] = { 905 "gpio8", 906}; 907 908static const char * const pll_clk_groups[] = { 909 "gpio54", 910}; 911 912static const char * const prng_rosc0_groups[] = { 913 "gpio72", 914}; 915 916static const char * const prng_rosc1_groups[] = { 917 "gpio73", 918}; 919 920static const char * const prng_rosc2_groups[] = { 921 "gpio74", 922}; 923 924static const char * const prng_rosc3_groups[] = { 925 "gpio75", 926}; 927 928static const char * const qdss_cti_groups[] = { 929 "gpio28", "gpio29", "gpio36", "gpio37", "gpio38", "gpio38", "gpio47", 930 "gpio48", "gpio53", "gpio53", "gpio105", "gpio106", "gpio154", 931 "gpio155", 932}; 933 934static const char * const qdss_gpio_groups[] = { 935 "gpio89", "gpio90", "gpio109", "gpio110", 936}; 937 938static const char * const qdss_gpio0_groups[] = { 939 "gpio24", "gpio65", 940}; 941 942static const char * const qdss_gpio1_groups[] = { 943 "gpio25", "gpio66", 944}; 945 946static const char * const qdss_gpio10_groups[] = { 947 "gpio63", "gpio83", 948}; 949 950static const char * const qdss_gpio11_groups[] = { 951 "gpio64", "gpio84", 952}; 953 954static const char * const qdss_gpio12_groups[] = { 955 "gpio39", "gpio85", 956}; 957 958static const char * const qdss_gpio13_groups[] = { 959 "gpio10", "gpio86", 960}; 961 962static const char * const qdss_gpio14_groups[] = { 963 "gpio45", "gpio87", 964}; 965 966static const char * const qdss_gpio15_groups[] = { 967 "gpio11", "gpio88", 968}; 969 970static const char * const qdss_gpio2_groups[] = { 971 "gpio26", "gpio67", 972}; 973 974static const char * const qdss_gpio3_groups[] = { 975 "gpio27", "gpio68", 976}; 977 978static const char * const qdss_gpio4_groups[] = { 979 "gpio30", "gpio77", 980}; 981 982static const char * const qdss_gpio5_groups[] = { 983 "gpio31", "gpio78", 984}; 985 986static const char * const qdss_gpio6_groups[] = { 987 "gpio4", "gpio79", 988}; 989 990static const char * const qdss_gpio7_groups[] = { 991 "gpio5", "gpio80", 992}; 993 994static const char * const qdss_gpio8_groups[] = { 995 "gpio6", "gpio81", 996}; 997 998static const char * const qdss_gpio9_groups[] = { 999 "gpio7", "gpio82", 1000}; 1001 1002static const char * const qspi0_groups[] = { 1003 "gpio32", 1004}; 1005 1006static const char * const qspi1_groups[] = { 1007 "gpio33", 1008}; 1009 1010static const char * const qspi2_groups[] = { 1011 "gpio36", 1012}; 1013 1014static const char * const qspi3_groups[] = { 1015 "gpio37", 1016}; 1017 1018static const char * const qspi_clk_groups[] = { 1019 "gpio34", 1020}; 1021 1022static const char * const qspi_cs0_groups[] = { 1023 "gpio35", 1024}; 1025 1026static const char * const qspi_cs1_groups[] = { 1027 "gpio38", 1028}; 1029 1030static const char * const qup0_groups[] = { 1031 "gpio0", "gpio1", "gpio2", "gpio3", "gpio93", 1032}; 1033 1034static const char * const qup1_groups[] = { 1035 "gpio2", "gpio3", "gpio61", "gpio62", 1036}; 1037 1038static const char * const qup2_groups[] = { 1039 "gpio12", "gpio13", "gpio22", "gpio23", 1040}; 1041 1042static const char * const qup3_groups[] = { 1043 "gpio16", "gpio17", "gpio18", "gpio19", "gpio41", 1044}; 1045 1046static const char * const qup4_groups[] = { 1047 "gpio20", "gpio21", "gpio22", "gpio23", "gpio94", 1048}; 1049 1050static const char * const qup5_groups[] = { 1051 "gpio95", "gpio96", "gpio97", "gpio98", 1052}; 1053 1054static const char * const qup6_groups[] = { 1055 "gpio63", "gpio64", "gpio91", "gpio92", 1056}; 1057 1058static const char * const qup7_groups[] = { 1059 "gpio24", "gpio25", "gpio26", "gpio27", 1060}; 1061 1062static const char * const qup8_groups[] = { 1063 "gpio8", "gpio9", "gpio10", "gpio11", 1064}; 1065 1066static const char * const qup9_groups[] = { 1067 "gpio34", "gpio35", "gpio109", "gpio110", 1068}; 1069 1070static const char * const qup10_groups[] = { 1071 "gpio4", "gpio5", "gpio6", "gpio7", 1072}; 1073 1074static const char * const qup11_groups[] = { 1075 "gpio14", "gpio15", "gpio28", "gpio30", 1076}; 1077 1078static const char * const tb_trig_groups[] = { 1079 "gpio69", 1080}; 1081 1082static const char * const tgu_ch0_groups[] = { 1083 "gpio20", 1084}; 1085 1086static const char * const tgu_ch1_groups[] = { 1087 "gpio21", 1088}; 1089 1090static const char * const tgu_ch2_groups[] = { 1091 "gpio22", 1092}; 1093 1094static const char * const tgu_ch3_groups[] = { 1095 "gpio23", 1096}; 1097 1098static const char * const tmess_prng0_groups[] = { 1099 "gpio80", 1100}; 1101 1102static const char * const tmess_prng1_groups[] = { 1103 "gpio79", 1104}; 1105 1106static const char * const tmess_prng2_groups[] = { 1107 "gpio83", 1108}; 1109 1110static const char * const tmess_prng3_groups[] = { 1111 "gpio81", 1112}; 1113 1114static const char * const tsense_pwm1_groups[] = { 1115 "gpio86", 1116}; 1117 1118static const char * const tsense_pwm2_groups[] = { 1119 "gpio86", 1120}; 1121 1122static const char * const usb0_phy_groups[] = { 1123 "gpio100", 1124}; 1125 1126static const char * const vsense_trigger_groups[] = { 1127 "gpio36", 1128}; 1129 1130static const struct pinfunction sar2130p_functions[] = { 1131 MSM_PIN_FUNCTION(gpio), 1132 MSM_PIN_FUNCTION(qup0), 1133 MSM_PIN_FUNCTION(ibi_i3c), 1134 MSM_PIN_FUNCTION(jitter_bist), 1135 MSM_PIN_FUNCTION(qup1), 1136 MSM_PIN_FUNCTION(phase_flag29), 1137 MSM_PIN_FUNCTION(phase_flag28), 1138 MSM_PIN_FUNCTION(qup10), 1139 MSM_PIN_FUNCTION(ddr_bist), 1140 MSM_PIN_FUNCTION(qdss_gpio6), 1141 MSM_PIN_FUNCTION(qdss_gpio7), 1142 MSM_PIN_FUNCTION(qdss_gpio8), 1143 MSM_PIN_FUNCTION(qdss_gpio9), 1144 MSM_PIN_FUNCTION(qup8), 1145 MSM_PIN_FUNCTION(pll_bist), 1146 MSM_PIN_FUNCTION(qdss_gpio13), 1147 MSM_PIN_FUNCTION(qdss_gpio15), 1148 MSM_PIN_FUNCTION(qup2), 1149 MSM_PIN_FUNCTION(mdp_vsync), 1150 MSM_PIN_FUNCTION(phase_flag27), 1151 MSM_PIN_FUNCTION(phase_flag26), 1152 MSM_PIN_FUNCTION(qup11), 1153 MSM_PIN_FUNCTION(qup3), 1154 MSM_PIN_FUNCTION(phase_flag25), 1155 MSM_PIN_FUNCTION(phase_flag24), 1156 MSM_PIN_FUNCTION(phase_flag23), 1157 MSM_PIN_FUNCTION(phase_flag22), 1158 MSM_PIN_FUNCTION(qup4), 1159 MSM_PIN_FUNCTION(aoss_cti), 1160 MSM_PIN_FUNCTION(tgu_ch0), 1161 MSM_PIN_FUNCTION(phase_flag21), 1162 MSM_PIN_FUNCTION(tgu_ch1), 1163 MSM_PIN_FUNCTION(phase_flag20), 1164 MSM_PIN_FUNCTION(tgu_ch2), 1165 MSM_PIN_FUNCTION(phase_flag19), 1166 MSM_PIN_FUNCTION(tgu_ch3), 1167 MSM_PIN_FUNCTION(qup7), 1168 MSM_PIN_FUNCTION(qdss_gpio0), 1169 MSM_PIN_FUNCTION(qdss_gpio1), 1170 MSM_PIN_FUNCTION(qdss_gpio2), 1171 MSM_PIN_FUNCTION(atest_usb0), 1172 MSM_PIN_FUNCTION(qdss_gpio3), 1173 MSM_PIN_FUNCTION(atest_usb02), 1174 MSM_PIN_FUNCTION(qdss_cti), 1175 MSM_PIN_FUNCTION(qdss_gpio4), 1176 MSM_PIN_FUNCTION(qdss_gpio5), 1177 MSM_PIN_FUNCTION(qspi0), 1178 MSM_PIN_FUNCTION(qspi1), 1179 MSM_PIN_FUNCTION(qspi_clk), 1180 MSM_PIN_FUNCTION(qup9), 1181 MSM_PIN_FUNCTION(qspi_cs0), 1182 MSM_PIN_FUNCTION(dp0_hot), 1183 MSM_PIN_FUNCTION(qspi2), 1184 MSM_PIN_FUNCTION(vsense_trigger), 1185 MSM_PIN_FUNCTION(qspi3), 1186 MSM_PIN_FUNCTION(qspi_cs1), 1187 MSM_PIN_FUNCTION(qdss_gpio12), 1188 MSM_PIN_FUNCTION(phase_flag18), 1189 MSM_PIN_FUNCTION(ddr_pxi1), 1190 MSM_PIN_FUNCTION(qdss_gpio14), 1191 MSM_PIN_FUNCTION(atest_char), 1192 MSM_PIN_FUNCTION(ddr_pxi3), 1193 MSM_PIN_FUNCTION(ddr_pxi2), 1194 MSM_PIN_FUNCTION(mdp_vsync0), 1195 MSM_PIN_FUNCTION(mdp_vsync1), 1196 MSM_PIN_FUNCTION(mdp_vsync2), 1197 MSM_PIN_FUNCTION(mdp_vsync3), 1198 MSM_PIN_FUNCTION(pll_clk), 1199 MSM_PIN_FUNCTION(pcie0_clkreqn), 1200 MSM_PIN_FUNCTION(ddr_pxi0), 1201 MSM_PIN_FUNCTION(pcie1_clkreqn), 1202 MSM_PIN_FUNCTION(dbg_out), 1203 MSM_PIN_FUNCTION(cri_trng), 1204 MSM_PIN_FUNCTION(atest_usb03), 1205 MSM_PIN_FUNCTION(phase_flag17), 1206 MSM_PIN_FUNCTION(phase_flag16), 1207 MSM_PIN_FUNCTION(qup6), 1208 MSM_PIN_FUNCTION(qdss_gpio10), 1209 MSM_PIN_FUNCTION(qdss_gpio11), 1210 MSM_PIN_FUNCTION(cci_i2c), 1211 MSM_PIN_FUNCTION(cam_mclk), 1212 MSM_PIN_FUNCTION(tb_trig), 1213 MSM_PIN_FUNCTION(cri_trng0), 1214 MSM_PIN_FUNCTION(cri_trng1), 1215 MSM_PIN_FUNCTION(prng_rosc0), 1216 MSM_PIN_FUNCTION(prng_rosc1), 1217 MSM_PIN_FUNCTION(prng_rosc2), 1218 MSM_PIN_FUNCTION(prng_rosc3), 1219 MSM_PIN_FUNCTION(cci_timer0), 1220 MSM_PIN_FUNCTION(cci_timer1), 1221 MSM_PIN_FUNCTION(cci_timer2), 1222 MSM_PIN_FUNCTION(tmess_prng1), 1223 MSM_PIN_FUNCTION(cci_timer3), 1224 MSM_PIN_FUNCTION(cci_async), 1225 MSM_PIN_FUNCTION(tmess_prng0), 1226 MSM_PIN_FUNCTION(cci_timer4), 1227 MSM_PIN_FUNCTION(tmess_prng3), 1228 MSM_PIN_FUNCTION(tmess_prng2), 1229 MSM_PIN_FUNCTION(tsense_pwm1), 1230 MSM_PIN_FUNCTION(tsense_pwm2), 1231 MSM_PIN_FUNCTION(atest_char3), 1232 MSM_PIN_FUNCTION(atest_char2), 1233 MSM_PIN_FUNCTION(qdss_gpio), 1234 MSM_PIN_FUNCTION(atest_char1), 1235 MSM_PIN_FUNCTION(atest_char0), 1236 MSM_PIN_FUNCTION(phase_flag11), 1237 MSM_PIN_FUNCTION(phase_flag10), 1238 MSM_PIN_FUNCTION(qup5), 1239 MSM_PIN_FUNCTION(phase_flag9), 1240 MSM_PIN_FUNCTION(phase_flag8), 1241 MSM_PIN_FUNCTION(phase_flag7), 1242 MSM_PIN_FUNCTION(phase_flag6), 1243 MSM_PIN_FUNCTION(usb0_phy), 1244 MSM_PIN_FUNCTION(ext_mclk1), 1245 MSM_PIN_FUNCTION(audio_ref), 1246 MSM_PIN_FUNCTION(ext_mclk0), 1247 MSM_PIN_FUNCTION(i2s0_sck), 1248 MSM_PIN_FUNCTION(i2s0_data0), 1249 MSM_PIN_FUNCTION(i2s0_data1), 1250 MSM_PIN_FUNCTION(i2s0_ws), 1251 MSM_PIN_FUNCTION(atest_usb01), 1252 MSM_PIN_FUNCTION(atest_usb00), 1253 MSM_PIN_FUNCTION(host2wlan_sol), 1254 MSM_PIN_FUNCTION(phase_flag3), 1255 MSM_PIN_FUNCTION(phase_flag2), 1256 MSM_PIN_FUNCTION(phase_flag1), 1257 MSM_PIN_FUNCTION(gcc_gp1), 1258 MSM_PIN_FUNCTION(gcc_gp2), 1259 MSM_PIN_FUNCTION(gcc_gp3), 1260 MSM_PIN_FUNCTION(phase_flag0), 1261 MSM_PIN_FUNCTION(phase_flag12), 1262 MSM_PIN_FUNCTION(phase_flag15), 1263 MSM_PIN_FUNCTION(phase_flag14), 1264 MSM_PIN_FUNCTION(phase_flag13), 1265 MSM_PIN_FUNCTION(phase_flag31), 1266 MSM_PIN_FUNCTION(phase_flag30), 1267 MSM_PIN_FUNCTION(phase_flag5), 1268 MSM_PIN_FUNCTION(phase_flag4), 1269}; 1270 1271/* Every pin is maintained as a single group, and missing or non-existing pin 1272 * would be maintained as dummy group to synchronize pin group index with 1273 * pin descriptor registered with pinctrl core. 1274 * Clients would not be able to request these dummy pin groups. 1275 */ 1276static const struct msm_pingroup sar2130p_groups[] = { 1277 [0] = PINGROUP(0, qup0, ibi_i3c, jitter_bist, _, _, _, _, _, _), 1278 [1] = PINGROUP(1, qup0, ibi_i3c, _, _, _, _, _, _, _), 1279 [2] = PINGROUP(2, qup0, qup1, phase_flag29, _, _, _, _, _, _), 1280 [3] = PINGROUP(3, qup0, qup1, phase_flag28, _, _, _, _, _, _), 1281 [4] = PINGROUP(4, qup10, ddr_bist, qdss_gpio6, _, _, _, _, _, _), 1282 [5] = PINGROUP(5, qup10, ddr_bist, qdss_gpio7, _, _, _, _, _, _), 1283 [6] = PINGROUP(6, qup10, qdss_gpio8, _, _, _, _, _, _, _), 1284 [7] = PINGROUP(7, qup10, qdss_gpio9, _, _, _, _, _, _, _), 1285 [8] = PINGROUP(8, qup8, pll_bist, _, _, _, _, _, _, _), 1286 [9] = PINGROUP(9, qup8, _, _, _, _, _, _, _, _), 1287 [10] = PINGROUP(10, qup8, qdss_gpio13, _, _, _, _, _, _, _), 1288 [11] = PINGROUP(11, qup8, qdss_gpio15, _, _, _, _, _, _, _), 1289 [12] = PINGROUP(12, qup2, mdp_vsync, phase_flag27, _, _, _, _, _, _), 1290 [13] = PINGROUP(13, qup2, mdp_vsync, phase_flag26, _, _, _, _, _, _), 1291 [14] = PINGROUP(14, qup11, _, _, _, _, _, _, _, _), 1292 [15] = PINGROUP(15, qup11, _, _, _, _, _, _, _, _), 1293 [16] = PINGROUP(16, qup3, phase_flag25, _, _, _, _, _, _, _), 1294 [17] = PINGROUP(17, qup3, phase_flag24, _, _, _, _, _, _, _), 1295 [18] = PINGROUP(18, qup3, phase_flag23, _, _, _, _, _, _, _), 1296 [19] = PINGROUP(19, qup3, phase_flag22, _, _, _, _, _, _, _), 1297 [20] = PINGROUP(20, qup4, aoss_cti, tgu_ch0, _, _, _, _, _, _), 1298 [21] = PINGROUP(21, qup4, aoss_cti, phase_flag21, tgu_ch1, _, _, _, _, _), 1299 [22] = PINGROUP(22, qup4, qup2, aoss_cti, phase_flag20, tgu_ch2, _, _, _, _), 1300 [23] = PINGROUP(23, qup4, qup2, aoss_cti, phase_flag19, tgu_ch3, _, _, _, _), 1301 [24] = PINGROUP(24, qup7, qdss_gpio0, _, _, _, _, _, _, _), 1302 [25] = PINGROUP(25, qup7, qdss_gpio1, _, _, _, _, _, _, _), 1303 [26] = PINGROUP(26, qup7, qdss_gpio2, atest_usb0, _, _, _, _, _, _), 1304 [27] = PINGROUP(27, qup7, qdss_gpio3, atest_usb02, _, _, _, _, _, _), 1305 [28] = PINGROUP(28, qup11, qdss_cti, _, _, _, _, _, _, _), 1306 [29] = PINGROUP(29, qdss_cti, _, _, _, _, _, _, _, _), 1307 [30] = PINGROUP(30, qup11, qdss_gpio4, _, _, _, _, _, _, _), 1308 [31] = PINGROUP(31, qdss_gpio5, _, _, _, _, _, _, _, _), 1309 [32] = PINGROUP(32, qspi0, _, _, _, _, _, _, _, _), 1310 [33] = PINGROUP(33, qspi1, _, _, _, _, _, _, _, _), 1311 [34] = PINGROUP(34, qspi_clk, qup9, _, _, _, _, _, _, _), 1312 [35] = PINGROUP(35, qspi_cs0, qup9, dp0_hot, _, _, _, _, _, _), 1313 [36] = PINGROUP(36, qspi2, qdss_cti, vsense_trigger, _, _, _, _, _, _), 1314 [37] = PINGROUP(37, qspi3, qdss_cti, _, _, _, _, _, _, _), 1315 [38] = PINGROUP(38, qspi_cs1, qdss_cti, qdss_cti, _, _, _, _, _, _), 1316 [39] = PINGROUP(39, qdss_gpio12, _, _, _, _, _, _, _, _), 1317 [40] = PINGROUP(40, _, _, _, _, _, _, _, _, _), 1318 [41] = PINGROUP(41, qup3, mdp_vsync, phase_flag18, _, ddr_pxi1, _, _, _, _), 1319 [42] = PINGROUP(42, _, _, _, _, _, _, _, _, _), 1320 [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), 1321 [44] = PINGROUP(44, _, _, _, _, _, _, _, _, _), 1322 [45] = PINGROUP(45, qdss_gpio14, ddr_pxi1, atest_char, _, _, _, _, _, _), 1323 [46] = PINGROUP(46, ddr_pxi3, _, _, _, _, _, _, _, _), 1324 [47] = PINGROUP(47, qdss_cti, ddr_pxi3, _, _, _, _, _, _, _), 1325 [48] = PINGROUP(48, qdss_cti, ddr_pxi2, _, _, _, _, _, _, _), 1326 [49] = PINGROUP(49, mdp_vsync, mdp_vsync0, mdp_vsync1, _, _, _, _, _, _), 1327 [50] = PINGROUP(50, mdp_vsync, mdp_vsync2, mdp_vsync3, _, _, _, _, _, _), 1328 [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), 1329 [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), 1330 [53] = PINGROUP(53, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 1331 [54] = PINGROUP(54, pll_clk, _, _, _, _, _, _, _, _), 1332 [55] = PINGROUP(55, _, ddr_pxi2, _, _, _, _, _, _, _), 1333 [56] = PINGROUP(56, pcie0_clkreqn, _, ddr_pxi0, _, _, _, _, _, _), 1334 [57] = PINGROUP(57, ddr_pxi0, _, _, _, _, _, _, _, _), 1335 [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), 1336 [59] = PINGROUP(59, pcie1_clkreqn, dbg_out, _, _, _, _, _, _, _), 1337 [60] = PINGROUP(60, cri_trng, atest_usb03, _, _, _, _, _, _, _), 1338 [61] = PINGROUP(61, qup1, phase_flag17, _, _, _, _, _, _, _), 1339 [62] = PINGROUP(62, qup1, phase_flag16, _, _, _, _, _, _, _), 1340 [63] = PINGROUP(63, qup6, qdss_gpio10, _, _, _, _, _, _, _), 1341 [64] = PINGROUP(64, qup6, qdss_gpio11, _, _, _, _, _, _, _), 1342 [65] = PINGROUP(65, qdss_gpio0, _, _, _, _, _, _, _, _), 1343 [66] = PINGROUP(66, qdss_gpio1, _, _, _, _, _, _, _, _), 1344 [67] = PINGROUP(67, cci_i2c, qdss_gpio2, _, _, _, _, _, _, _), 1345 [68] = PINGROUP(68, cci_i2c, qdss_gpio3, _, _, _, _, _, _, _), 1346 [69] = PINGROUP(69, cam_mclk, tb_trig, _, _, _, _, _, _, _), 1347 [70] = PINGROUP(70, cam_mclk, cri_trng0, _, _, _, _, _, _, _), 1348 [71] = PINGROUP(71, cam_mclk, cri_trng1, _, _, _, _, _, _, _), 1349 [72] = PINGROUP(72, cam_mclk, prng_rosc0, _, _, _, _, _, _, _), 1350 [73] = PINGROUP(73, cam_mclk, prng_rosc1, _, _, _, _, _, _, _), 1351 [74] = PINGROUP(74, cam_mclk, prng_rosc2, _, _, _, _, _, _, _), 1352 [75] = PINGROUP(75, cam_mclk, prng_rosc3, _, _, _, _, _, _, _), 1353 [76] = PINGROUP(76, cam_mclk, _, _, _, _, _, _, _, _), 1354 [77] = PINGROUP(77, cci_timer0, qdss_gpio4, _, _, _, _, _, _, _), 1355 [78] = PINGROUP(78, cci_timer1, cci_i2c, qdss_gpio5, _, _, _, _, _, _), 1356 [79] = PINGROUP(79, cci_timer2, cci_i2c, tmess_prng1, qdss_gpio6, _, _, _, _, _), 1357 [80] = PINGROUP(80, cci_timer3, cci_i2c, cci_async, tmess_prng0, qdss_gpio7, _, _, _, _), 1358 [81] = PINGROUP(81, cci_timer4, cci_i2c, cci_async, tmess_prng3, qdss_gpio8, _, _, _, _), 1359 [82] = PINGROUP(82, cci_async, qdss_gpio9, _, _, _, _, _, _, _), 1360 [83] = PINGROUP(83, cci_i2c, tmess_prng2, qdss_gpio10, _, _, _, _, _, _), 1361 [84] = PINGROUP(84, cci_i2c, qdss_gpio11, _, _, _, _, _, _, _), 1362 [85] = PINGROUP(85, cci_i2c, qdss_gpio12, _, _, _, _, _, _, _), 1363 [86] = PINGROUP(86, cci_i2c, qdss_gpio13, tsense_pwm1, tsense_pwm2, _, _, _, _, _), 1364 [87] = PINGROUP(87, cci_i2c, qdss_gpio14, atest_char3, _, _, _, _, _, _), 1365 [88] = PINGROUP(88, cci_i2c, qdss_gpio15, atest_char2, _, _, _, _, _, _), 1366 [89] = PINGROUP(89, cci_i2c, qdss_gpio, atest_char1, _, _, _, _, _, _), 1367 [90] = PINGROUP(90, cci_i2c, qdss_gpio, atest_char0, _, _, _, _, _, _), 1368 [91] = PINGROUP(91, cci_i2c, qup6, ibi_i3c, _, _, _, _, _, _), 1369 [92] = PINGROUP(92, cci_i2c, qup6, ibi_i3c, _, _, _, _, _, _), 1370 [93] = PINGROUP(93, qup0, phase_flag11, _, _, _, _, _, _, _), 1371 [94] = PINGROUP(94, qup4, phase_flag10, _, _, _, _, _, _, _), 1372 [95] = PINGROUP(95, qup5, phase_flag9, _, _, _, _, _, _, _), 1373 [96] = PINGROUP(96, qup5, phase_flag8, _, _, _, _, _, _, _), 1374 [97] = PINGROUP(97, qup5, phase_flag7, _, _, _, _, _, _, _), 1375 [98] = PINGROUP(98, qup5, phase_flag6, _, _, _, _, _, _, _), 1376 [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), 1377 [100] = PINGROUP(100, usb0_phy, ddr_bist, _, _, _, _, _, _, _), 1378 [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _), 1379 [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _), 1380 [103] = PINGROUP(103, ext_mclk1, audio_ref, dp0_hot, ddr_bist, _, _, _, _, _), 1381 [104] = PINGROUP(104, ext_mclk0, _, _, _, _, _, _, _, _), 1382 [105] = PINGROUP(105, i2s0_sck, _, qdss_cti, _, _, _, _, _, _), 1383 [106] = PINGROUP(106, i2s0_data0, _, qdss_cti, _, _, _, _, _, _), 1384 [107] = PINGROUP(107, i2s0_data1, _, _, _, _, _, _, _, _), 1385 [108] = PINGROUP(108, i2s0_ws, _, _, _, _, _, _, _, _), 1386 [109] = PINGROUP(109, qup9, qdss_gpio, atest_usb01, _, _, _, _, _, _), 1387 [110] = PINGROUP(110, qup9, qdss_gpio, atest_usb00, _, _, _, _, _, _), 1388 [111] = PINGROUP(111, host2wlan_sol, _, _, _, _, _, _, _, _), 1389 [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _), 1390 [113] = PINGROUP(113, _, _, _, _, _, _, _, _, _), 1391 [114] = PINGROUP(114, _, _, _, _, _, _, _, _, _), 1392 [115] = PINGROUP(115, _, _, _, _, _, _, _, _, _), 1393 [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _), 1394 [117] = PINGROUP(117, _, _, _, _, _, _, _, _, _), 1395 [118] = PINGROUP(118, _, _, _, _, _, _, _, _, _), 1396 [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _), 1397 [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _), 1398 [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _), 1399 [122] = PINGROUP(122, _, _, _, _, _, _, _, _, _), 1400 [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _), 1401 [124] = PINGROUP(124, _, _, _, _, _, _, _, _, _), 1402 [125] = PINGROUP(125, _, _, _, _, _, _, _, _, _), 1403 [126] = PINGROUP(126, phase_flag3, _, _, _, _, _, _, _, _), 1404 [127] = PINGROUP(127, phase_flag2, _, _, _, _, _, _, _, _), 1405 [128] = PINGROUP(128, phase_flag1, _, _, _, _, _, _, _, _), 1406 [129] = PINGROUP(129, gcc_gp1, _, _, _, _, _, _, _, _), 1407 [130] = PINGROUP(130, gcc_gp2, _, _, _, _, _, _, _, _), 1408 [131] = PINGROUP(131, gcc_gp3, _, _, _, _, _, _, _, _), 1409 [132] = PINGROUP(132, gcc_gp1, _, _, _, _, _, _, _, _), 1410 [133] = PINGROUP(133, phase_flag0, _, _, _, _, _, _, _, _), 1411 [134] = PINGROUP(134, phase_flag12, _, _, _, _, _, _, _, _), 1412 [135] = PINGROUP(135, gcc_gp2, _, _, _, _, _, _, _, _), 1413 [136] = PINGROUP(136, gcc_gp3, _, _, _, _, _, _, _, _), 1414 [137] = PINGROUP(137, phase_flag15, _, _, _, _, _, _, _, _), 1415 [138] = PINGROUP(138, phase_flag14, _, _, _, _, _, _, _, _), 1416 [139] = PINGROUP(139, phase_flag13, _, _, _, _, _, _, _, _), 1417 [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), 1418 [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), 1419 [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), 1420 [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), 1421 [144] = PINGROUP(144, _, _, _, _, _, _, _, _, _), 1422 [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), 1423 [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), 1424 [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), 1425 [148] = PINGROUP(148, phase_flag31, _, _, _, _, _, _, _, _), 1426 [149] = PINGROUP(149, phase_flag30, _, _, _, _, _, _, _, _), 1427 [150] = PINGROUP(150, phase_flag5, _, _, _, _, _, _, _, _), 1428 [151] = PINGROUP(151, phase_flag4, _, _, _, _, _, _, _, _), 1429 [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _), 1430 [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _), 1431 [154] = PINGROUP(154, qdss_cti, _, _, _, _, _, _, _, _), 1432 [155] = PINGROUP(155, qdss_cti, _, _, _, _, _, _, _, _), 1433 [156] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xa1000, 0, 0), 1434 [157] = SDC_QDSD_PINGROUP(sdc1_clk, 0xa0000, 13, 6), 1435 [158] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xa0000, 11, 3), 1436 [159] = SDC_QDSD_PINGROUP(sdc1_data, 0xa0000, 9, 0), 1437}; 1438 1439static const struct msm_gpio_wakeirq_map sar2130p_pdc_map[] = { 1440 { 0, 50 }, { 3, 68 }, { 6, 88 }, { 7, 55 }, { 10, 66 }, { 11, 96 }, 1441 { 12, 48 }, { 13, 49 }, { 15, 62 }, { 18, 57 }, { 19, 59 }, { 23, 51 }, 1442 { 27, 74 }, { 28, 67 }, { 29, 84 }, { 30, 58 }, { 31, 94 }, { 32, 60 }, 1443 { 33, 61 }, { 35, 69 }, { 37, 70 }, { 38, 64 }, { 39, 65 }, { 40, 63 }, 1444 { 41, 92 }, { 42, 82 }, { 44, 83 }, { 45, 43 }, { 46, 72 }, { 47, 45 }, 1445 { 48, 44 }, { 49, 71 }, { 50, 87 }, { 53, 77 }, { 54, 78 }, 1446 { 55, 106 }, { 56, 79 }, { 57, 80 }, { 58, 107 }, { 59, 81 }, 1447 { 60, 89 }, { 61, 54 }, { 62, 73 }, { 63, 93 }, { 64, 86 }, { 65, 75 }, 1448 { 67, 42 }, { 68, 76 }, { 76, 116 }, { 77, 12 }, { 83, 13 }, 1449 { 91, 90 }, { 94, 95 }, { 95, 91 }, { 98, 47 }, { 100, 85 }, 1450 { 101, 52 }, { 102, 53 }, { 103, 97 }, { 104, 98 }, { 105, 99 }, 1451 { 106, 100 }, { 107, 101 }, { 108, 102 }, { 109, 103 }, { 111, 104 }, 1452 { 113, 46 }, { 114, 56 }, { 115, 108 }, { 116, 109 }, { 117, 110 }, 1453 { 118, 111 }, { 121, 112 }, { 122, 113 }, { 124, 114 }, { 127, 115 }, 1454 { 132, 118 }, { 134, 119 }, { 135, 120 }, { 136, 121 }, { 139, 122 }, 1455 { 140, 123 }, { 141, 124 }, { 143, 128 }, { 144, 129 }, { 145, 130 }, 1456 { 146, 131 }, { 148, 132 }, { 150, 133 }, { 151, 134 }, { 153, 135 }, 1457 { 155, 137 }, 1458}; 1459 1460static const struct msm_pinctrl_soc_data sar2130p_tlmm = { 1461 .pins = sar2130p_pins, 1462 .npins = ARRAY_SIZE(sar2130p_pins), 1463 .functions = sar2130p_functions, 1464 .nfunctions = ARRAY_SIZE(sar2130p_functions), 1465 .groups = sar2130p_groups, 1466 .ngroups = ARRAY_SIZE(sar2130p_groups), 1467 .ngpios = 156, 1468 .wakeirq_map = sar2130p_pdc_map, 1469 .nwakeirq_map = ARRAY_SIZE(sar2130p_pdc_map), 1470}; 1471 1472static int sar2130p_tlmm_probe(struct platform_device *pdev) 1473{ 1474 return msm_pinctrl_probe(pdev, &sar2130p_tlmm); 1475} 1476 1477static const struct of_device_id sar2130p_tlmm_of_match[] = { 1478 { .compatible = "qcom,sar2130p-tlmm", .data = &sar2130p_tlmm}, 1479 { }, 1480}; 1481MODULE_DEVICE_TABLE(of, sar2130p_tlmm_of_match); 1482 1483static struct platform_driver sar2130p_tlmm_driver = { 1484 .driver = { 1485 .name = "sar2130p-tlmm", 1486 .of_match_table = sar2130p_tlmm_of_match, 1487 }, 1488 .probe = sar2130p_tlmm_probe, 1489}; 1490 1491static int __init sar2130p_tlmm_init(void) 1492{ 1493 return platform_driver_register(&sar2130p_tlmm_driver); 1494} 1495arch_initcall(sar2130p_tlmm_init); 1496 1497static void __exit sar2130p_tlmm_exit(void) 1498{ 1499 platform_driver_unregister(&sar2130p_tlmm_driver); 1500} 1501module_exit(sar2130p_tlmm_exit); 1502 1503MODULE_DESCRIPTION("QTI SAR2130P TLMM driver"); 1504MODULE_LICENSE("GPL");