tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 *
6 */
7
8#include <linux/device.h>
9#include <linux/interconnect.h>
10#include <linux/interconnect-provider.h>
11#include <linux/mod_devicetable.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <dt-bindings/interconnect/qcom,sc7280.h>
15
16#include "bcm-voter.h"
17#include "icc-rpmh.h"
18#include "sc7280.h"
19
20static struct qcom_icc_node qhm_qspi = {
21 .name = "qhm_qspi",
22 .id = SC7280_MASTER_QSPI_0,
23 .channels = 1,
24 .buswidth = 4,
25 .qosbox = &(const struct qcom_icc_qosbox) {
26 .num_ports = 1,
27 .port_offsets = { 0x7000 },
28 .prio = 2,
29 .urg_fwd = 0,
30 },
31 .num_links = 1,
32 .links = { SC7280_SLAVE_A1NOC_SNOC },
33};
34
35static struct qcom_icc_node qhm_qup0 = {
36 .name = "qhm_qup0",
37 .id = SC7280_MASTER_QUP_0,
38 .channels = 1,
39 .buswidth = 4,
40 .qosbox = &(const struct qcom_icc_qosbox) {
41 .num_ports = 1,
42 .port_offsets = { 0x11000 },
43 .prio = 2,
44 .urg_fwd = 0,
45 },
46 .num_links = 1,
47 .links = { SC7280_SLAVE_A1NOC_SNOC },
48};
49
50static struct qcom_icc_node qhm_qup1 = {
51 .name = "qhm_qup1",
52 .id = SC7280_MASTER_QUP_1,
53 .channels = 1,
54 .buswidth = 4,
55 .qosbox = &(const struct qcom_icc_qosbox) {
56 .num_ports = 1,
57 .port_offsets = { 0x8000 },
58 .prio = 2,
59 .urg_fwd = 0,
60 },
61 .num_links = 1,
62 .links = { SC7280_SLAVE_A1NOC_SNOC },
63};
64
65static struct qcom_icc_node qnm_a1noc_cfg = {
66 .name = "qnm_a1noc_cfg",
67 .id = SC7280_MASTER_A1NOC_CFG,
68 .channels = 1,
69 .buswidth = 4,
70 .num_links = 1,
71 .links = { SC7280_SLAVE_SERVICE_A1NOC },
72};
73
74static struct qcom_icc_node xm_sdc1 = {
75 .name = "xm_sdc1",
76 .id = SC7280_MASTER_SDCC_1,
77 .channels = 1,
78 .buswidth = 8,
79 .qosbox = &(const struct qcom_icc_qosbox) {
80 .num_ports = 1,
81 .port_offsets = { 0xc000 },
82 .prio = 2,
83 .urg_fwd = 0,
84 },
85 .num_links = 1,
86 .links = { SC7280_SLAVE_A1NOC_SNOC },
87};
88
89static struct qcom_icc_node xm_sdc2 = {
90 .name = "xm_sdc2",
91 .id = SC7280_MASTER_SDCC_2,
92 .channels = 1,
93 .buswidth = 8,
94 .qosbox = &(const struct qcom_icc_qosbox) {
95 .num_ports = 1,
96 .port_offsets = { 0xe000 },
97 .prio = 2,
98 .urg_fwd = 0,
99 },
100 .num_links = 1,
101 .links = { SC7280_SLAVE_A1NOC_SNOC },
102};
103
104static struct qcom_icc_node xm_sdc4 = {
105 .name = "xm_sdc4",
106 .id = SC7280_MASTER_SDCC_4,
107 .channels = 1,
108 .buswidth = 8,
109 .qosbox = &(const struct qcom_icc_qosbox) {
110 .num_ports = 1,
111 .port_offsets = { 0x9000 },
112 .prio = 2,
113 .urg_fwd = 0,
114 },
115 .num_links = 1,
116 .links = { SC7280_SLAVE_A1NOC_SNOC },
117};
118
119static struct qcom_icc_node xm_ufs_mem = {
120 .name = "xm_ufs_mem",
121 .id = SC7280_MASTER_UFS_MEM,
122 .channels = 1,
123 .buswidth = 8,
124 .qosbox = &(const struct qcom_icc_qosbox) {
125 .num_ports = 1,
126 .port_offsets = { 0xa000 },
127 .prio = 2,
128 .urg_fwd = 0,
129 },
130 .num_links = 1,
131 .links = { SC7280_SLAVE_A1NOC_SNOC },
132};
133
134static struct qcom_icc_node xm_usb2 = {
135 .name = "xm_usb2",
136 .id = SC7280_MASTER_USB2,
137 .channels = 1,
138 .buswidth = 8,
139 .num_links = 1,
140 .links = { SC7280_SLAVE_A1NOC_SNOC },
141};
142
143static struct qcom_icc_node xm_usb3_0 = {
144 .name = "xm_usb3_0",
145 .id = SC7280_MASTER_USB3_0,
146 .channels = 1,
147 .buswidth = 8,
148 .qosbox = &(const struct qcom_icc_qosbox) {
149 .num_ports = 1,
150 .port_offsets = { 0xb000 },
151 .prio = 2,
152 .urg_fwd = 0,
153 },
154 .num_links = 1,
155 .links = { SC7280_SLAVE_A1NOC_SNOC },
156};
157
158static struct qcom_icc_node qhm_qdss_bam = {
159 .name = "qhm_qdss_bam",
160 .id = SC7280_MASTER_QDSS_BAM,
161 .channels = 1,
162 .buswidth = 4,
163 .qosbox = &(const struct qcom_icc_qosbox) {
164 .num_ports = 1,
165 .port_offsets = { 0x18000 },
166 .prio = 2,
167 .urg_fwd = 0,
168 },
169 .num_links = 1,
170 .links = { SC7280_SLAVE_A2NOC_SNOC },
171};
172
173static struct qcom_icc_node qnm_a2noc_cfg = {
174 .name = "qnm_a2noc_cfg",
175 .id = SC7280_MASTER_A2NOC_CFG,
176 .channels = 1,
177 .buswidth = 4,
178 .num_links = 1,
179 .links = { SC7280_SLAVE_SERVICE_A2NOC },
180};
181
182static struct qcom_icc_node qnm_cnoc_datapath = {
183 .name = "qnm_cnoc_datapath",
184 .id = SC7280_MASTER_CNOC_A2NOC,
185 .channels = 1,
186 .buswidth = 8,
187 .qosbox = &(const struct qcom_icc_qosbox) {
188 .num_ports = 1,
189 .port_offsets = { 0x1c000 },
190 .prio = 2,
191 .urg_fwd = 0,
192 },
193 .num_links = 1,
194 .links = { SC7280_SLAVE_A2NOC_SNOC },
195};
196
197static struct qcom_icc_node qxm_crypto = {
198 .name = "qxm_crypto",
199 .id = SC7280_MASTER_CRYPTO,
200 .channels = 1,
201 .buswidth = 8,
202 .qosbox = &(const struct qcom_icc_qosbox) {
203 .num_ports = 1,
204 .port_offsets = { 0x1d000 },
205 .prio = 2,
206 .urg_fwd = 0,
207 },
208 .num_links = 1,
209 .links = { SC7280_SLAVE_A2NOC_SNOC },
210};
211
212static struct qcom_icc_node qxm_ipa = {
213 .name = "qxm_ipa",
214 .id = SC7280_MASTER_IPA,
215 .channels = 1,
216 .buswidth = 8,
217 .qosbox = &(const struct qcom_icc_qosbox) {
218 .num_ports = 1,
219 .port_offsets = { 0x10000 },
220 .prio = 2,
221 .urg_fwd = 0,
222 },
223 .num_links = 1,
224 .links = { SC7280_SLAVE_A2NOC_SNOC },
225};
226
227static struct qcom_icc_node xm_pcie3_0 = {
228 .name = "xm_pcie3_0",
229 .id = SC7280_MASTER_PCIE_0,
230 .channels = 1,
231 .buswidth = 8,
232 .num_links = 1,
233 .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
234};
235
236static struct qcom_icc_node xm_pcie3_1 = {
237 .name = "xm_pcie3_1",
238 .id = SC7280_MASTER_PCIE_1,
239 .channels = 1,
240 .buswidth = 8,
241 .num_links = 1,
242 .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
243};
244
245static struct qcom_icc_node xm_qdss_etr = {
246 .name = "xm_qdss_etr",
247 .id = SC7280_MASTER_QDSS_ETR,
248 .channels = 1,
249 .buswidth = 8,
250 .qosbox = &(const struct qcom_icc_qosbox) {
251 .num_ports = 1,
252 .port_offsets = { 0x15000 },
253 .prio = 2,
254 .urg_fwd = 0,
255 },
256 .num_links = 1,
257 .links = { SC7280_SLAVE_A2NOC_SNOC },
258};
259
260static struct qcom_icc_node qup0_core_master = {
261 .name = "qup0_core_master",
262 .id = SC7280_MASTER_QUP_CORE_0,
263 .channels = 1,
264 .buswidth = 4,
265 .num_links = 1,
266 .links = { SC7280_SLAVE_QUP_CORE_0 },
267};
268
269static struct qcom_icc_node qup1_core_master = {
270 .name = "qup1_core_master",
271 .id = SC7280_MASTER_QUP_CORE_1,
272 .channels = 1,
273 .buswidth = 4,
274 .num_links = 1,
275 .links = { SC7280_SLAVE_QUP_CORE_1 },
276};
277
278static struct qcom_icc_node qnm_cnoc3_cnoc2 = {
279 .name = "qnm_cnoc3_cnoc2",
280 .id = SC7280_MASTER_CNOC3_CNOC2,
281 .channels = 1,
282 .buswidth = 8,
283 .num_links = 44,
284 .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
285 SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
286 SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
287 SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
288 SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
289 SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
290 SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
291 SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
292 SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
293 SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
294 SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
295 SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
296 SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
297 SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
298 SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
299 SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
300 SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
301 SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
302 SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
303 SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
304 SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
305 SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG },
306};
307
308static struct qcom_icc_node xm_qdss_dap = {
309 .name = "xm_qdss_dap",
310 .id = SC7280_MASTER_QDSS_DAP,
311 .channels = 1,
312 .buswidth = 8,
313 .num_links = 45,
314 .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
315 SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
316 SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
317 SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
318 SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
319 SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
320 SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
321 SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
322 SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
323 SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
324 SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
325 SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
326 SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
327 SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
328 SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
329 SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
330 SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
331 SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
332 SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
333 SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
334 SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
335 SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG,
336 SC7280_SLAVE_SNOC_CFG },
337};
338
339static struct qcom_icc_node qnm_cnoc2_cnoc3 = {
340 .name = "qnm_cnoc2_cnoc3",
341 .id = SC7280_MASTER_CNOC2_CNOC3,
342 .channels = 1,
343 .buswidth = 8,
344 .num_links = 9,
345 .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
346 SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG,
347 SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
348 SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
349 SC7280_SLAVE_TCU },
350};
351
352static struct qcom_icc_node qnm_gemnoc_cnoc = {
353 .name = "qnm_gemnoc_cnoc",
354 .id = SC7280_MASTER_GEM_NOC_CNOC,
355 .channels = 1,
356 .buswidth = 16,
357 .num_links = 9,
358 .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
359 SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG,
360 SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
361 SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
362 SC7280_SLAVE_TCU },
363};
364
365static struct qcom_icc_node qnm_gemnoc_pcie = {
366 .name = "qnm_gemnoc_pcie",
367 .id = SC7280_MASTER_GEM_NOC_PCIE_SNOC,
368 .channels = 1,
369 .buswidth = 8,
370 .num_links = 2,
371 .links = { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 },
372};
373
374static struct qcom_icc_node qnm_cnoc_dc_noc = {
375 .name = "qnm_cnoc_dc_noc",
376 .id = SC7280_MASTER_CNOC_DC_NOC,
377 .channels = 1,
378 .buswidth = 4,
379 .num_links = 2,
380 .links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG },
381};
382
383static struct qcom_icc_node alm_gpu_tcu = {
384 .name = "alm_gpu_tcu",
385 .id = SC7280_MASTER_GPU_TCU,
386 .channels = 1,
387 .buswidth = 8,
388 .qosbox = &(const struct qcom_icc_qosbox) {
389 .num_ports = 1,
390 .port_offsets = { 0xd7000 },
391 .prio = 2,
392 .urg_fwd = 0,
393 },
394 .num_links = 2,
395 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
396};
397
398static struct qcom_icc_node alm_sys_tcu = {
399 .name = "alm_sys_tcu",
400 .id = SC7280_MASTER_SYS_TCU,
401 .channels = 1,
402 .buswidth = 8,
403 .qosbox = &(const struct qcom_icc_qosbox) {
404 .num_ports = 1,
405 .port_offsets = { 0xd6000 },
406 .prio = 6,
407 .urg_fwd = 0,
408 },
409 .num_links = 2,
410 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
411};
412
413static struct qcom_icc_node chm_apps = {
414 .name = "chm_apps",
415 .id = SC7280_MASTER_APPSS_PROC,
416 .channels = 1,
417 .buswidth = 32,
418 .num_links = 3,
419 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
420 SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
421};
422
423static struct qcom_icc_node qnm_cmpnoc = {
424 .name = "qnm_cmpnoc",
425 .id = SC7280_MASTER_COMPUTE_NOC,
426 .channels = 2,
427 .buswidth = 32,
428 .qosbox = &(const struct qcom_icc_qosbox) {
429 .num_ports = 2,
430 .port_offsets = { 0x21000, 0x61000 },
431 .prio = 0,
432 .urg_fwd = 1,
433 },
434 .num_links = 2,
435 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
436};
437
438static struct qcom_icc_node qnm_gemnoc_cfg = {
439 .name = "qnm_gemnoc_cfg",
440 .id = SC7280_MASTER_GEM_NOC_CFG,
441 .channels = 1,
442 .buswidth = 4,
443 .num_links = 5,
444 .links = { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_CFG,
445 SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2,
446 SC7280_SLAVE_SERVICE_GEM_NOC },
447};
448
449static struct qcom_icc_node qnm_gpu = {
450 .name = "qnm_gpu",
451 .id = SC7280_MASTER_GFX3D,
452 .channels = 2,
453 .buswidth = 32,
454 .qosbox = &(const struct qcom_icc_qosbox) {
455 .num_ports = 2,
456 .port_offsets = { 0x22000, 0x62000 },
457 .prio = 0,
458 .urg_fwd = 0,
459 },
460 .num_links = 2,
461 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
462};
463
464static struct qcom_icc_node qnm_mnoc_hf = {
465 .name = "qnm_mnoc_hf",
466 .id = SC7280_MASTER_MNOC_HF_MEM_NOC,
467 .channels = 2,
468 .buswidth = 32,
469 .qosbox = &(const struct qcom_icc_qosbox) {
470 .num_ports = 2,
471 .port_offsets = { 0x23000, 0x63000 },
472 .prio = 0,
473 .urg_fwd = 1,
474 },
475 .num_links = 1,
476 .links = { SC7280_SLAVE_LLCC },
477};
478
479static struct qcom_icc_node qnm_mnoc_sf = {
480 .name = "qnm_mnoc_sf",
481 .id = SC7280_MASTER_MNOC_SF_MEM_NOC,
482 .channels = 1,
483 .buswidth = 32,
484 .qosbox = &(const struct qcom_icc_qosbox) {
485 .num_ports = 1,
486 .port_offsets = { 0xcf000 },
487 .prio = 0,
488 .urg_fwd = 1,
489 },
490 .num_links = 2,
491 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
492};
493
494static struct qcom_icc_node qnm_pcie = {
495 .name = "qnm_pcie",
496 .id = SC7280_MASTER_ANOC_PCIE_GEM_NOC,
497 .channels = 1,
498 .buswidth = 16,
499 .num_links = 2,
500 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
501};
502
503static struct qcom_icc_node qnm_snoc_gc = {
504 .name = "qnm_snoc_gc",
505 .id = SC7280_MASTER_SNOC_GC_MEM_NOC,
506 .channels = 1,
507 .buswidth = 8,
508 .qosbox = &(const struct qcom_icc_qosbox) {
509 .num_ports = 1,
510 .port_offsets = { 0xd3000 },
511 .prio = 0,
512 .urg_fwd = 1,
513 },
514 .num_links = 1,
515 .links = { SC7280_SLAVE_LLCC },
516};
517
518static struct qcom_icc_node qnm_snoc_sf = {
519 .name = "qnm_snoc_sf",
520 .id = SC7280_MASTER_SNOC_SF_MEM_NOC,
521 .channels = 1,
522 .buswidth = 16,
523 .qosbox = &(const struct qcom_icc_qosbox) {
524 .num_ports = 1,
525 .port_offsets = { 0xd4000 },
526 .prio = 0,
527 .urg_fwd = 1,
528 },
529 .num_links = 3,
530 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
531 SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
532};
533
534static struct qcom_icc_node qhm_config_noc = {
535 .name = "qhm_config_noc",
536 .id = SC7280_MASTER_CNOC_LPASS_AG_NOC,
537 .channels = 1,
538 .buswidth = 4,
539 .num_links = 6,
540 .links = { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG,
541 SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG,
542 SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NOC },
543};
544
545static struct qcom_icc_node llcc_mc = {
546 .name = "llcc_mc",
547 .id = SC7280_MASTER_LLCC,
548 .channels = 2,
549 .buswidth = 4,
550 .num_links = 1,
551 .links = { SC7280_SLAVE_EBI1 },
552};
553
554static struct qcom_icc_node qnm_mnoc_cfg = {
555 .name = "qnm_mnoc_cfg",
556 .id = SC7280_MASTER_CNOC_MNOC_CFG,
557 .channels = 1,
558 .buswidth = 4,
559 .num_links = 1,
560 .links = { SC7280_SLAVE_SERVICE_MNOC },
561};
562
563static struct qcom_icc_node qnm_video0 = {
564 .name = "qnm_video0",
565 .id = SC7280_MASTER_VIDEO_P0,
566 .channels = 1,
567 .buswidth = 32,
568 .qosbox = &(const struct qcom_icc_qosbox) {
569 .num_ports = 1,
570 .port_offsets = { 0x14000 },
571 .prio = 0,
572 .urg_fwd = 1,
573 },
574 .num_links = 1,
575 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
576};
577
578static struct qcom_icc_node qnm_video_cpu = {
579 .name = "qnm_video_cpu",
580 .id = SC7280_MASTER_VIDEO_PROC,
581 .channels = 1,
582 .buswidth = 8,
583 .qosbox = &(const struct qcom_icc_qosbox) {
584 .num_ports = 1,
585 .port_offsets = { 0x15000 },
586 .prio = 0,
587 .urg_fwd = 1,
588 },
589 .num_links = 1,
590 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
591};
592
593static struct qcom_icc_node qxm_camnoc_hf = {
594 .name = "qxm_camnoc_hf",
595 .id = SC7280_MASTER_CAMNOC_HF,
596 .channels = 2,
597 .buswidth = 32,
598 .qosbox = &(const struct qcom_icc_qosbox) {
599 .num_ports = 2,
600 .port_offsets = { 0x10000, 0x10180 },
601 .prio = 0,
602 .urg_fwd = 1,
603 },
604 .num_links = 1,
605 .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
606};
607
608static struct qcom_icc_node qxm_camnoc_icp = {
609 .name = "qxm_camnoc_icp",
610 .id = SC7280_MASTER_CAMNOC_ICP,
611 .channels = 1,
612 .buswidth = 8,
613 .qosbox = &(const struct qcom_icc_qosbox) {
614 .num_ports = 1,
615 .port_offsets = { 0x11000 },
616 .prio = 0,
617 .urg_fwd = 1,
618 },
619 .num_links = 1,
620 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
621};
622
623static struct qcom_icc_node qxm_camnoc_sf = {
624 .name = "qxm_camnoc_sf",
625 .id = SC7280_MASTER_CAMNOC_SF,
626 .channels = 1,
627 .buswidth = 32,
628 .qosbox = &(const struct qcom_icc_qosbox) {
629 .num_ports = 1,
630 .port_offsets = { 0x12000 },
631 .prio = 0,
632 .urg_fwd = 1,
633 },
634 .num_links = 1,
635 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
636};
637
638static struct qcom_icc_node qxm_mdp0 = {
639 .name = "qxm_mdp0",
640 .id = SC7280_MASTER_MDP0,
641 .channels = 1,
642 .buswidth = 32,
643 .qosbox = &(const struct qcom_icc_qosbox) {
644 .num_ports = 1,
645 .port_offsets = { 0x16000 },
646 .prio = 0,
647 .urg_fwd = 1,
648 },
649 .num_links = 1,
650 .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
651};
652
653static struct qcom_icc_node qhm_nsp_noc_config = {
654 .name = "qhm_nsp_noc_config",
655 .id = SC7280_MASTER_CDSP_NOC_CFG,
656 .channels = 1,
657 .buswidth = 4,
658 .num_links = 1,
659 .links = { SC7280_SLAVE_SERVICE_NSP_NOC },
660};
661
662static struct qcom_icc_node qxm_nsp = {
663 .name = "qxm_nsp",
664 .id = SC7280_MASTER_CDSP_PROC,
665 .channels = 2,
666 .buswidth = 32,
667 .num_links = 1,
668 .links = { SC7280_SLAVE_CDSP_MEM_NOC },
669};
670
671static struct qcom_icc_node qnm_aggre1_noc = {
672 .name = "qnm_aggre1_noc",
673 .id = SC7280_MASTER_A1NOC_SNOC,
674 .channels = 1,
675 .buswidth = 16,
676 .num_links = 1,
677 .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
678};
679
680static struct qcom_icc_node qnm_aggre2_noc = {
681 .name = "qnm_aggre2_noc",
682 .id = SC7280_MASTER_A2NOC_SNOC,
683 .channels = 1,
684 .buswidth = 16,
685 .num_links = 1,
686 .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
687};
688
689static struct qcom_icc_node qnm_snoc_cfg = {
690 .name = "qnm_snoc_cfg",
691 .id = SC7280_MASTER_SNOC_CFG,
692 .channels = 1,
693 .buswidth = 4,
694 .num_links = 1,
695 .links = { SC7280_SLAVE_SERVICE_SNOC },
696};
697
698static struct qcom_icc_node qxm_pimem = {
699 .name = "qxm_pimem",
700 .id = SC7280_MASTER_PIMEM,
701 .channels = 1,
702 .buswidth = 8,
703 .qosbox = &(const struct qcom_icc_qosbox) {
704 .num_ports = 1,
705 .port_offsets = { 0x8000 },
706 .prio = 2,
707 .urg_fwd = 0,
708 },
709 .num_links = 1,
710 .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
711};
712
713static struct qcom_icc_node xm_gic = {
714 .name = "xm_gic",
715 .id = SC7280_MASTER_GIC,
716 .channels = 1,
717 .buswidth = 8,
718 .qosbox = &(const struct qcom_icc_qosbox) {
719 .num_ports = 1,
720 .port_offsets = { 0xa000 },
721 .prio = 2,
722 .urg_fwd = 0,
723 },
724 .num_links = 1,
725 .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
726};
727
728static struct qcom_icc_node qns_a1noc_snoc = {
729 .name = "qns_a1noc_snoc",
730 .id = SC7280_SLAVE_A1NOC_SNOC,
731 .channels = 1,
732 .buswidth = 16,
733 .num_links = 1,
734 .links = { SC7280_MASTER_A1NOC_SNOC },
735};
736
737static struct qcom_icc_node srvc_aggre1_noc = {
738 .name = "srvc_aggre1_noc",
739 .id = SC7280_SLAVE_SERVICE_A1NOC,
740 .channels = 1,
741 .buswidth = 4,
742 .num_links = 0,
743};
744
745static struct qcom_icc_node qns_a2noc_snoc = {
746 .name = "qns_a2noc_snoc",
747 .id = SC7280_SLAVE_A2NOC_SNOC,
748 .channels = 1,
749 .buswidth = 16,
750 .num_links = 1,
751 .links = { SC7280_MASTER_A2NOC_SNOC },
752};
753
754static struct qcom_icc_node qns_pcie_mem_noc = {
755 .name = "qns_pcie_mem_noc",
756 .id = SC7280_SLAVE_ANOC_PCIE_GEM_NOC,
757 .channels = 1,
758 .buswidth = 16,
759 .num_links = 1,
760 .links = { SC7280_MASTER_ANOC_PCIE_GEM_NOC },
761};
762
763static struct qcom_icc_node srvc_aggre2_noc = {
764 .name = "srvc_aggre2_noc",
765 .id = SC7280_SLAVE_SERVICE_A2NOC,
766 .channels = 1,
767 .buswidth = 4,
768 .num_links = 0,
769};
770
771static struct qcom_icc_node qup0_core_slave = {
772 .name = "qup0_core_slave",
773 .id = SC7280_SLAVE_QUP_CORE_0,
774 .channels = 1,
775 .buswidth = 4,
776 .num_links = 0,
777};
778
779static struct qcom_icc_node qup1_core_slave = {
780 .name = "qup1_core_slave",
781 .id = SC7280_SLAVE_QUP_CORE_1,
782 .channels = 1,
783 .buswidth = 4,
784 .num_links = 0,
785};
786
787static struct qcom_icc_node qhs_ahb2phy0 = {
788 .name = "qhs_ahb2phy0",
789 .id = SC7280_SLAVE_AHB2PHY_SOUTH,
790 .channels = 1,
791 .buswidth = 4,
792 .num_links = 0,
793};
794
795static struct qcom_icc_node qhs_ahb2phy1 = {
796 .name = "qhs_ahb2phy1",
797 .id = SC7280_SLAVE_AHB2PHY_NORTH,
798 .channels = 1,
799 .buswidth = 4,
800 .num_links = 0,
801};
802
803static struct qcom_icc_node qhs_camera_cfg = {
804 .name = "qhs_camera_cfg",
805 .id = SC7280_SLAVE_CAMERA_CFG,
806 .channels = 1,
807 .buswidth = 4,
808 .num_links = 0,
809};
810
811static struct qcom_icc_node qhs_clk_ctl = {
812 .name = "qhs_clk_ctl",
813 .id = SC7280_SLAVE_CLK_CTL,
814 .channels = 1,
815 .buswidth = 4,
816 .num_links = 0,
817};
818
819static struct qcom_icc_node qhs_compute_cfg = {
820 .name = "qhs_compute_cfg",
821 .id = SC7280_SLAVE_CDSP_CFG,
822 .channels = 1,
823 .buswidth = 4,
824 .num_links = 1,
825 .links = { SC7280_MASTER_CDSP_NOC_CFG },
826};
827
828static struct qcom_icc_node qhs_cpr_cx = {
829 .name = "qhs_cpr_cx",
830 .id = SC7280_SLAVE_RBCPR_CX_CFG,
831 .channels = 1,
832 .buswidth = 4,
833 .num_links = 0,
834};
835
836static struct qcom_icc_node qhs_cpr_mx = {
837 .name = "qhs_cpr_mx",
838 .id = SC7280_SLAVE_RBCPR_MX_CFG,
839 .channels = 1,
840 .buswidth = 4,
841 .num_links = 0,
842};
843
844static struct qcom_icc_node qhs_crypto0_cfg = {
845 .name = "qhs_crypto0_cfg",
846 .id = SC7280_SLAVE_CRYPTO_0_CFG,
847 .channels = 1,
848 .buswidth = 4,
849 .num_links = 0,
850};
851
852static struct qcom_icc_node qhs_cx_rdpm = {
853 .name = "qhs_cx_rdpm",
854 .id = SC7280_SLAVE_CX_RDPM,
855 .channels = 1,
856 .buswidth = 4,
857 .num_links = 0,
858};
859
860static struct qcom_icc_node qhs_dcc_cfg = {
861 .name = "qhs_dcc_cfg",
862 .id = SC7280_SLAVE_DCC_CFG,
863 .channels = 1,
864 .buswidth = 4,
865 .num_links = 0,
866};
867
868static struct qcom_icc_node qhs_display_cfg = {
869 .name = "qhs_display_cfg",
870 .id = SC7280_SLAVE_DISPLAY_CFG,
871 .channels = 1,
872 .buswidth = 4,
873 .num_links = 0,
874};
875
876static struct qcom_icc_node qhs_gpuss_cfg = {
877 .name = "qhs_gpuss_cfg",
878 .id = SC7280_SLAVE_GFX3D_CFG,
879 .channels = 1,
880 .buswidth = 8,
881 .num_links = 0,
882};
883
884static struct qcom_icc_node qhs_hwkm = {
885 .name = "qhs_hwkm",
886 .id = SC7280_SLAVE_HWKM,
887 .channels = 1,
888 .buswidth = 4,
889 .num_links = 0,
890};
891
892static struct qcom_icc_node qhs_imem_cfg = {
893 .name = "qhs_imem_cfg",
894 .id = SC7280_SLAVE_IMEM_CFG,
895 .channels = 1,
896 .buswidth = 4,
897 .num_links = 0,
898};
899
900static struct qcom_icc_node qhs_ipa = {
901 .name = "qhs_ipa",
902 .id = SC7280_SLAVE_IPA_CFG,
903 .channels = 1,
904 .buswidth = 4,
905 .num_links = 0,
906};
907
908static struct qcom_icc_node qhs_ipc_router = {
909 .name = "qhs_ipc_router",
910 .id = SC7280_SLAVE_IPC_ROUTER_CFG,
911 .channels = 1,
912 .buswidth = 4,
913 .num_links = 0,
914};
915
916static struct qcom_icc_node qhs_lpass_cfg = {
917 .name = "qhs_lpass_cfg",
918 .id = SC7280_SLAVE_LPASS,
919 .channels = 1,
920 .buswidth = 4,
921 .num_links = 1,
922 .links = { SC7280_MASTER_CNOC_LPASS_AG_NOC },
923};
924
925static struct qcom_icc_node qhs_mss_cfg = {
926 .name = "qhs_mss_cfg",
927 .id = SC7280_SLAVE_CNOC_MSS,
928 .channels = 1,
929 .buswidth = 4,
930 .num_links = 0,
931};
932
933static struct qcom_icc_node qhs_mx_rdpm = {
934 .name = "qhs_mx_rdpm",
935 .id = SC7280_SLAVE_MX_RDPM,
936 .channels = 1,
937 .buswidth = 4,
938 .num_links = 0,
939};
940
941static struct qcom_icc_node qhs_pcie0_cfg = {
942 .name = "qhs_pcie0_cfg",
943 .id = SC7280_SLAVE_PCIE_0_CFG,
944 .channels = 1,
945 .buswidth = 4,
946 .num_links = 0,
947};
948
949static struct qcom_icc_node qhs_pcie1_cfg = {
950 .name = "qhs_pcie1_cfg",
951 .id = SC7280_SLAVE_PCIE_1_CFG,
952 .channels = 1,
953 .buswidth = 4,
954 .num_links = 0,
955};
956
957static struct qcom_icc_node qhs_pdm = {
958 .name = "qhs_pdm",
959 .id = SC7280_SLAVE_PDM,
960 .channels = 1,
961 .buswidth = 4,
962 .num_links = 0,
963};
964
965static struct qcom_icc_node qhs_pimem_cfg = {
966 .name = "qhs_pimem_cfg",
967 .id = SC7280_SLAVE_PIMEM_CFG,
968 .channels = 1,
969 .buswidth = 4,
970 .num_links = 0,
971};
972
973static struct qcom_icc_node qhs_pka_wrapper_cfg = {
974 .name = "qhs_pka_wrapper_cfg",
975 .id = SC7280_SLAVE_PKA_WRAPPER_CFG,
976 .channels = 1,
977 .buswidth = 4,
978 .num_links = 0,
979};
980
981static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
982 .name = "qhs_pmu_wrapper_cfg",
983 .id = SC7280_SLAVE_PMU_WRAPPER_CFG,
984 .channels = 1,
985 .buswidth = 4,
986 .num_links = 0,
987};
988
989static struct qcom_icc_node qhs_qdss_cfg = {
990 .name = "qhs_qdss_cfg",
991 .id = SC7280_SLAVE_QDSS_CFG,
992 .channels = 1,
993 .buswidth = 4,
994 .num_links = 0,
995};
996
997static struct qcom_icc_node qhs_qspi = {
998 .name = "qhs_qspi",
999 .id = SC7280_SLAVE_QSPI_0,
1000 .channels = 1,
1001 .buswidth = 4,
1002 .num_links = 0,
1003};
1004
1005static struct qcom_icc_node qhs_qup0 = {
1006 .name = "qhs_qup0",
1007 .id = SC7280_SLAVE_QUP_0,
1008 .channels = 1,
1009 .buswidth = 4,
1010 .num_links = 0,
1011};
1012
1013static struct qcom_icc_node qhs_qup1 = {
1014 .name = "qhs_qup1",
1015 .id = SC7280_SLAVE_QUP_1,
1016 .channels = 1,
1017 .buswidth = 4,
1018 .num_links = 0,
1019};
1020
1021static struct qcom_icc_node qhs_sdc1 = {
1022 .name = "qhs_sdc1",
1023 .id = SC7280_SLAVE_SDCC_1,
1024 .channels = 1,
1025 .buswidth = 4,
1026 .num_links = 0,
1027};
1028
1029static struct qcom_icc_node qhs_sdc2 = {
1030 .name = "qhs_sdc2",
1031 .id = SC7280_SLAVE_SDCC_2,
1032 .channels = 1,
1033 .buswidth = 4,
1034 .num_links = 0,
1035};
1036
1037static struct qcom_icc_node qhs_sdc4 = {
1038 .name = "qhs_sdc4",
1039 .id = SC7280_SLAVE_SDCC_4,
1040 .channels = 1,
1041 .buswidth = 4,
1042 .num_links = 0,
1043};
1044
1045static struct qcom_icc_node qhs_security = {
1046 .name = "qhs_security",
1047 .id = SC7280_SLAVE_SECURITY,
1048 .channels = 1,
1049 .buswidth = 4,
1050 .num_links = 0,
1051};
1052
1053static struct qcom_icc_node qhs_tcsr = {
1054 .name = "qhs_tcsr",
1055 .id = SC7280_SLAVE_TCSR,
1056 .channels = 1,
1057 .buswidth = 4,
1058 .num_links = 0,
1059};
1060
1061static struct qcom_icc_node qhs_tlmm = {
1062 .name = "qhs_tlmm",
1063 .id = SC7280_SLAVE_TLMM,
1064 .channels = 1,
1065 .buswidth = 4,
1066 .num_links = 0,
1067};
1068
1069static struct qcom_icc_node qhs_ufs_mem_cfg = {
1070 .name = "qhs_ufs_mem_cfg",
1071 .id = SC7280_SLAVE_UFS_MEM_CFG,
1072 .channels = 1,
1073 .buswidth = 4,
1074 .num_links = 0,
1075};
1076
1077static struct qcom_icc_node qhs_usb2 = {
1078 .name = "qhs_usb2",
1079 .id = SC7280_SLAVE_USB2,
1080 .channels = 1,
1081 .buswidth = 4,
1082 .num_links = 0,
1083};
1084
1085static struct qcom_icc_node qhs_usb3_0 = {
1086 .name = "qhs_usb3_0",
1087 .id = SC7280_SLAVE_USB3_0,
1088 .channels = 1,
1089 .buswidth = 4,
1090 .num_links = 0,
1091};
1092
1093static struct qcom_icc_node qhs_venus_cfg = {
1094 .name = "qhs_venus_cfg",
1095 .id = SC7280_SLAVE_VENUS_CFG,
1096 .channels = 1,
1097 .buswidth = 4,
1098 .num_links = 0,
1099};
1100
1101static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1102 .name = "qhs_vsense_ctrl_cfg",
1103 .id = SC7280_SLAVE_VSENSE_CTRL_CFG,
1104 .channels = 1,
1105 .buswidth = 4,
1106 .num_links = 0,
1107};
1108
1109static struct qcom_icc_node qns_a1_noc_cfg = {
1110 .name = "qns_a1_noc_cfg",
1111 .id = SC7280_SLAVE_A1NOC_CFG,
1112 .channels = 1,
1113 .buswidth = 4,
1114 .num_links = 1,
1115 .links = { SC7280_MASTER_A1NOC_CFG },
1116};
1117
1118static struct qcom_icc_node qns_a2_noc_cfg = {
1119 .name = "qns_a2_noc_cfg",
1120 .id = SC7280_SLAVE_A2NOC_CFG,
1121 .channels = 1,
1122 .buswidth = 4,
1123 .num_links = 1,
1124 .links = { SC7280_MASTER_A2NOC_CFG },
1125};
1126
1127static struct qcom_icc_node qns_cnoc2_cnoc3 = {
1128 .name = "qns_cnoc2_cnoc3",
1129 .id = SC7280_SLAVE_CNOC2_CNOC3,
1130 .channels = 1,
1131 .buswidth = 8,
1132 .num_links = 1,
1133 .links = { SC7280_MASTER_CNOC2_CNOC3 },
1134};
1135
1136static struct qcom_icc_node qns_mnoc_cfg = {
1137 .name = "qns_mnoc_cfg",
1138 .id = SC7280_SLAVE_CNOC_MNOC_CFG,
1139 .channels = 1,
1140 .buswidth = 4,
1141 .num_links = 1,
1142 .links = { SC7280_MASTER_CNOC_MNOC_CFG },
1143};
1144
1145static struct qcom_icc_node qns_snoc_cfg = {
1146 .name = "qns_snoc_cfg",
1147 .id = SC7280_SLAVE_SNOC_CFG,
1148 .channels = 1,
1149 .buswidth = 4,
1150 .num_links = 1,
1151 .links = { SC7280_MASTER_SNOC_CFG },
1152};
1153
1154static struct qcom_icc_node qhs_aoss = {
1155 .name = "qhs_aoss",
1156 .id = SC7280_SLAVE_AOSS,
1157 .channels = 1,
1158 .buswidth = 4,
1159 .num_links = 0,
1160};
1161
1162static struct qcom_icc_node qhs_apss = {
1163 .name = "qhs_apss",
1164 .id = SC7280_SLAVE_APPSS,
1165 .channels = 1,
1166 .buswidth = 8,
1167 .num_links = 0,
1168};
1169
1170static struct qcom_icc_node qns_cnoc3_cnoc2 = {
1171 .name = "qns_cnoc3_cnoc2",
1172 .id = SC7280_SLAVE_CNOC3_CNOC2,
1173 .channels = 1,
1174 .buswidth = 8,
1175 .num_links = 1,
1176 .links = { SC7280_MASTER_CNOC3_CNOC2 },
1177};
1178
1179static struct qcom_icc_node qns_cnoc_a2noc = {
1180 .name = "qns_cnoc_a2noc",
1181 .id = SC7280_SLAVE_CNOC_A2NOC,
1182 .channels = 1,
1183 .buswidth = 8,
1184 .num_links = 1,
1185 .links = { SC7280_MASTER_CNOC_A2NOC },
1186};
1187
1188static struct qcom_icc_node qns_ddrss_cfg = {
1189 .name = "qns_ddrss_cfg",
1190 .id = SC7280_SLAVE_DDRSS_CFG,
1191 .channels = 1,
1192 .buswidth = 4,
1193 .num_links = 1,
1194 .links = { SC7280_MASTER_CNOC_DC_NOC },
1195};
1196
1197static struct qcom_icc_node qxs_boot_imem = {
1198 .name = "qxs_boot_imem",
1199 .id = SC7280_SLAVE_BOOT_IMEM,
1200 .channels = 1,
1201 .buswidth = 8,
1202 .num_links = 0,
1203};
1204
1205static struct qcom_icc_node qxs_imem = {
1206 .name = "qxs_imem",
1207 .id = SC7280_SLAVE_IMEM,
1208 .channels = 1,
1209 .buswidth = 8,
1210 .num_links = 0,
1211};
1212
1213static struct qcom_icc_node qxs_pimem = {
1214 .name = "qxs_pimem",
1215 .id = SC7280_SLAVE_PIMEM,
1216 .channels = 1,
1217 .buswidth = 8,
1218 .num_links = 0,
1219};
1220
1221static struct qcom_icc_node xs_pcie_0 = {
1222 .name = "xs_pcie_0",
1223 .id = SC7280_SLAVE_PCIE_0,
1224 .channels = 1,
1225 .buswidth = 8,
1226 .num_links = 0,
1227};
1228
1229static struct qcom_icc_node xs_pcie_1 = {
1230 .name = "xs_pcie_1",
1231 .id = SC7280_SLAVE_PCIE_1,
1232 .channels = 1,
1233 .buswidth = 8,
1234 .num_links = 0,
1235};
1236
1237static struct qcom_icc_node xs_qdss_stm = {
1238 .name = "xs_qdss_stm",
1239 .id = SC7280_SLAVE_QDSS_STM,
1240 .channels = 1,
1241 .buswidth = 4,
1242 .num_links = 0,
1243};
1244
1245static struct qcom_icc_node xs_sys_tcu_cfg = {
1246 .name = "xs_sys_tcu_cfg",
1247 .id = SC7280_SLAVE_TCU,
1248 .channels = 1,
1249 .buswidth = 8,
1250 .num_links = 0,
1251};
1252
1253static struct qcom_icc_node qhs_llcc = {
1254 .name = "qhs_llcc",
1255 .id = SC7280_SLAVE_LLCC_CFG,
1256 .channels = 1,
1257 .buswidth = 4,
1258 .num_links = 0,
1259};
1260
1261static struct qcom_icc_node qns_gemnoc = {
1262 .name = "qns_gemnoc",
1263 .id = SC7280_SLAVE_GEM_NOC_CFG,
1264 .channels = 1,
1265 .buswidth = 4,
1266 .num_links = 1,
1267 .links = { SC7280_MASTER_GEM_NOC_CFG },
1268};
1269
1270static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1271 .name = "qhs_mdsp_ms_mpu_cfg",
1272 .id = SC7280_SLAVE_MSS_PROC_MS_MPU_CFG,
1273 .channels = 1,
1274 .buswidth = 4,
1275 .num_links = 0,
1276};
1277
1278static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
1279 .name = "qhs_modem_ms_mpu_cfg",
1280 .id = SC7280_SLAVE_MCDMA_MS_MPU_CFG,
1281 .channels = 1,
1282 .buswidth = 4,
1283 .num_links = 0,
1284};
1285
1286static struct qcom_icc_node qns_gem_noc_cnoc = {
1287 .name = "qns_gem_noc_cnoc",
1288 .id = SC7280_SLAVE_GEM_NOC_CNOC,
1289 .channels = 1,
1290 .buswidth = 16,
1291 .num_links = 1,
1292 .links = { SC7280_MASTER_GEM_NOC_CNOC },
1293};
1294
1295static struct qcom_icc_node qns_llcc = {
1296 .name = "qns_llcc",
1297 .id = SC7280_SLAVE_LLCC,
1298 .channels = 2,
1299 .buswidth = 16,
1300 .num_links = 1,
1301 .links = { SC7280_MASTER_LLCC },
1302};
1303
1304static struct qcom_icc_node qns_pcie = {
1305 .name = "qns_pcie",
1306 .id = SC7280_SLAVE_MEM_NOC_PCIE_SNOC,
1307 .channels = 1,
1308 .buswidth = 8,
1309 .num_links = 1,
1310 .links = { SC7280_MASTER_GEM_NOC_PCIE_SNOC },
1311};
1312
1313static struct qcom_icc_node srvc_even_gemnoc = {
1314 .name = "srvc_even_gemnoc",
1315 .id = SC7280_SLAVE_SERVICE_GEM_NOC_1,
1316 .channels = 1,
1317 .buswidth = 4,
1318 .num_links = 0,
1319};
1320
1321static struct qcom_icc_node srvc_odd_gemnoc = {
1322 .name = "srvc_odd_gemnoc",
1323 .id = SC7280_SLAVE_SERVICE_GEM_NOC_2,
1324 .channels = 1,
1325 .buswidth = 4,
1326 .num_links = 0,
1327};
1328
1329static struct qcom_icc_node srvc_sys_gemnoc = {
1330 .name = "srvc_sys_gemnoc",
1331 .id = SC7280_SLAVE_SERVICE_GEM_NOC,
1332 .channels = 1,
1333 .buswidth = 4,
1334 .num_links = 0,
1335};
1336
1337static struct qcom_icc_node qhs_lpass_core = {
1338 .name = "qhs_lpass_core",
1339 .id = SC7280_SLAVE_LPASS_CORE_CFG,
1340 .channels = 1,
1341 .buswidth = 4,
1342 .num_links = 0,
1343};
1344
1345static struct qcom_icc_node qhs_lpass_lpi = {
1346 .name = "qhs_lpass_lpi",
1347 .id = SC7280_SLAVE_LPASS_LPI_CFG,
1348 .channels = 1,
1349 .buswidth = 4,
1350 .num_links = 0,
1351};
1352
1353static struct qcom_icc_node qhs_lpass_mpu = {
1354 .name = "qhs_lpass_mpu",
1355 .id = SC7280_SLAVE_LPASS_MPU_CFG,
1356 .channels = 1,
1357 .buswidth = 4,
1358 .num_links = 0,
1359};
1360
1361static struct qcom_icc_node qhs_lpass_top = {
1362 .name = "qhs_lpass_top",
1363 .id = SC7280_SLAVE_LPASS_TOP_CFG,
1364 .channels = 1,
1365 .buswidth = 4,
1366 .num_links = 0,
1367};
1368
1369static struct qcom_icc_node srvc_niu_aml_noc = {
1370 .name = "srvc_niu_aml_noc",
1371 .id = SC7280_SLAVE_SERVICES_LPASS_AML_NOC,
1372 .channels = 1,
1373 .buswidth = 4,
1374 .num_links = 0,
1375};
1376
1377static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1378 .name = "srvc_niu_lpass_agnoc",
1379 .id = SC7280_SLAVE_SERVICE_LPASS_AG_NOC,
1380 .channels = 1,
1381 .buswidth = 4,
1382 .num_links = 0,
1383};
1384
1385static struct qcom_icc_node ebi = {
1386 .name = "ebi",
1387 .id = SC7280_SLAVE_EBI1,
1388 .channels = 2,
1389 .buswidth = 4,
1390 .num_links = 0,
1391};
1392
1393static struct qcom_icc_node qns_mem_noc_hf = {
1394 .name = "qns_mem_noc_hf",
1395 .id = SC7280_SLAVE_MNOC_HF_MEM_NOC,
1396 .channels = 2,
1397 .buswidth = 32,
1398 .num_links = 1,
1399 .links = { SC7280_MASTER_MNOC_HF_MEM_NOC },
1400};
1401
1402static struct qcom_icc_node qns_mem_noc_sf = {
1403 .name = "qns_mem_noc_sf",
1404 .id = SC7280_SLAVE_MNOC_SF_MEM_NOC,
1405 .channels = 1,
1406 .buswidth = 32,
1407 .num_links = 1,
1408 .links = { SC7280_MASTER_MNOC_SF_MEM_NOC },
1409};
1410
1411static struct qcom_icc_node srvc_mnoc = {
1412 .name = "srvc_mnoc",
1413 .id = SC7280_SLAVE_SERVICE_MNOC,
1414 .channels = 1,
1415 .buswidth = 4,
1416 .num_links = 0,
1417};
1418
1419static struct qcom_icc_node qns_nsp_gemnoc = {
1420 .name = "qns_nsp_gemnoc",
1421 .id = SC7280_SLAVE_CDSP_MEM_NOC,
1422 .channels = 2,
1423 .buswidth = 32,
1424 .num_links = 1,
1425 .links = { SC7280_MASTER_COMPUTE_NOC },
1426};
1427
1428static struct qcom_icc_node service_nsp_noc = {
1429 .name = "service_nsp_noc",
1430 .id = SC7280_SLAVE_SERVICE_NSP_NOC,
1431 .channels = 1,
1432 .buswidth = 4,
1433 .num_links = 0,
1434};
1435
1436static struct qcom_icc_node qns_gemnoc_gc = {
1437 .name = "qns_gemnoc_gc",
1438 .id = SC7280_SLAVE_SNOC_GEM_NOC_GC,
1439 .channels = 1,
1440 .buswidth = 8,
1441 .num_links = 1,
1442 .links = { SC7280_MASTER_SNOC_GC_MEM_NOC },
1443};
1444
1445static struct qcom_icc_node qns_gemnoc_sf = {
1446 .name = "qns_gemnoc_sf",
1447 .id = SC7280_SLAVE_SNOC_GEM_NOC_SF,
1448 .channels = 1,
1449 .buswidth = 16,
1450 .num_links = 1,
1451 .links = { SC7280_MASTER_SNOC_SF_MEM_NOC },
1452};
1453
1454static struct qcom_icc_node srvc_snoc = {
1455 .name = "srvc_snoc",
1456 .id = SC7280_SLAVE_SERVICE_SNOC,
1457 .channels = 1,
1458 .buswidth = 4,
1459 .num_links = 0,
1460};
1461
1462static struct qcom_icc_bcm bcm_acv = {
1463 .name = "ACV",
1464 .enable_mask = BIT(3),
1465 .num_nodes = 1,
1466 .nodes = { &ebi },
1467};
1468
1469static struct qcom_icc_bcm bcm_ce0 = {
1470 .name = "CE0",
1471 .num_nodes = 1,
1472 .nodes = { &qxm_crypto },
1473};
1474
1475static struct qcom_icc_bcm bcm_cn0 = {
1476 .name = "CN0",
1477 .keepalive = true,
1478 .num_nodes = 2,
1479 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1480};
1481
1482static struct qcom_icc_bcm bcm_cn1 = {
1483 .name = "CN1",
1484 .num_nodes = 47,
1485 .nodes = { &qnm_cnoc3_cnoc2, &xm_qdss_dap,
1486 &qhs_ahb2phy0, &qhs_ahb2phy1,
1487 &qhs_camera_cfg, &qhs_clk_ctl,
1488 &qhs_compute_cfg, &qhs_cpr_cx,
1489 &qhs_cpr_mx, &qhs_crypto0_cfg,
1490 &qhs_cx_rdpm, &qhs_dcc_cfg,
1491 &qhs_display_cfg, &qhs_gpuss_cfg,
1492 &qhs_hwkm, &qhs_imem_cfg,
1493 &qhs_ipa, &qhs_ipc_router,
1494 &qhs_mss_cfg, &qhs_mx_rdpm,
1495 &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1496 &qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
1497 &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
1498 &qhs_qup0, &qhs_qup1,
1499 &qhs_security, &qhs_tcsr,
1500 &qhs_tlmm, &qhs_ufs_mem_cfg, &qhs_usb2,
1501 &qhs_usb3_0, &qhs_venus_cfg,
1502 &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg,
1503 &qns_a2_noc_cfg, &qns_cnoc2_cnoc3,
1504 &qns_mnoc_cfg, &qns_snoc_cfg,
1505 &qnm_cnoc2_cnoc3, &qhs_aoss,
1506 &qhs_apss, &qns_cnoc3_cnoc2,
1507 &qns_cnoc_a2noc, &qns_ddrss_cfg },
1508};
1509
1510static struct qcom_icc_bcm bcm_cn2 = {
1511 .name = "CN2",
1512 .num_nodes = 6,
1513 .nodes = { &qhs_lpass_cfg, &qhs_pdm,
1514 &qhs_qspi, &qhs_sdc1,
1515 &qhs_sdc2, &qhs_sdc4 },
1516};
1517
1518static struct qcom_icc_bcm bcm_co0 = {
1519 .name = "CO0",
1520 .num_nodes = 1,
1521 .nodes = { &qns_nsp_gemnoc },
1522};
1523
1524static struct qcom_icc_bcm bcm_co3 = {
1525 .name = "CO3",
1526 .num_nodes = 1,
1527 .nodes = { &qxm_nsp },
1528};
1529
1530static struct qcom_icc_bcm bcm_mc0 = {
1531 .name = "MC0",
1532 .keepalive = true,
1533 .num_nodes = 1,
1534 .nodes = { &ebi },
1535};
1536
1537static struct qcom_icc_bcm bcm_mm0 = {
1538 .name = "MM0",
1539 .keepalive = true,
1540 .num_nodes = 1,
1541 .nodes = { &qns_mem_noc_hf },
1542};
1543
1544static struct qcom_icc_bcm bcm_mm1 = {
1545 .name = "MM1",
1546 .num_nodes = 2,
1547 .nodes = { &qxm_camnoc_hf, &qxm_mdp0 },
1548};
1549
1550static struct qcom_icc_bcm bcm_mm4 = {
1551 .name = "MM4",
1552 .num_nodes = 1,
1553 .nodes = { &qns_mem_noc_sf },
1554};
1555
1556static struct qcom_icc_bcm bcm_mm5 = {
1557 .name = "MM5",
1558 .num_nodes = 3,
1559 .nodes = { &qnm_video0, &qxm_camnoc_icp,
1560 &qxm_camnoc_sf },
1561};
1562
1563static struct qcom_icc_bcm bcm_qup0 = {
1564 .name = "QUP0",
1565 .vote_scale = 1,
1566 .num_nodes = 1,
1567 .nodes = { &qup0_core_slave },
1568};
1569
1570static struct qcom_icc_bcm bcm_qup1 = {
1571 .name = "QUP1",
1572 .vote_scale = 1,
1573 .num_nodes = 1,
1574 .nodes = { &qup1_core_slave },
1575};
1576
1577static struct qcom_icc_bcm bcm_sh0 = {
1578 .name = "SH0",
1579 .keepalive = true,
1580 .num_nodes = 1,
1581 .nodes = { &qns_llcc },
1582};
1583
1584static struct qcom_icc_bcm bcm_sh2 = {
1585 .name = "SH2",
1586 .num_nodes = 2,
1587 .nodes = { &alm_gpu_tcu, &alm_sys_tcu },
1588};
1589
1590static struct qcom_icc_bcm bcm_sh3 = {
1591 .name = "SH3",
1592 .num_nodes = 1,
1593 .nodes = { &qnm_cmpnoc },
1594};
1595
1596static struct qcom_icc_bcm bcm_sh4 = {
1597 .name = "SH4",
1598 .num_nodes = 1,
1599 .nodes = { &chm_apps },
1600};
1601
1602static struct qcom_icc_bcm bcm_sn0 = {
1603 .name = "SN0",
1604 .keepalive = true,
1605 .num_nodes = 1,
1606 .nodes = { &qns_gemnoc_sf },
1607};
1608
1609static struct qcom_icc_bcm bcm_sn2 = {
1610 .name = "SN2",
1611 .num_nodes = 1,
1612 .nodes = { &qns_gemnoc_gc },
1613};
1614
1615static struct qcom_icc_bcm bcm_sn3 = {
1616 .name = "SN3",
1617 .num_nodes = 1,
1618 .nodes = { &qxs_pimem },
1619};
1620
1621static struct qcom_icc_bcm bcm_sn4 = {
1622 .name = "SN4",
1623 .num_nodes = 1,
1624 .nodes = { &xs_qdss_stm },
1625};
1626
1627static struct qcom_icc_bcm bcm_sn5 = {
1628 .name = "SN5",
1629 .num_nodes = 1,
1630 .nodes = { &xm_pcie3_0 },
1631};
1632
1633static struct qcom_icc_bcm bcm_sn6 = {
1634 .name = "SN6",
1635 .num_nodes = 1,
1636 .nodes = { &xm_pcie3_1 },
1637};
1638
1639static struct qcom_icc_bcm bcm_sn7 = {
1640 .name = "SN7",
1641 .num_nodes = 1,
1642 .nodes = { &qnm_aggre1_noc },
1643};
1644
1645static struct qcom_icc_bcm bcm_sn8 = {
1646 .name = "SN8",
1647 .num_nodes = 1,
1648 .nodes = { &qnm_aggre2_noc },
1649};
1650
1651static struct qcom_icc_bcm bcm_sn14 = {
1652 .name = "SN14",
1653 .num_nodes = 1,
1654 .nodes = { &qns_pcie_mem_noc },
1655};
1656
1657static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1658 &bcm_sn5,
1659 &bcm_sn6,
1660 &bcm_sn14,
1661};
1662
1663static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1664 [MASTER_QSPI_0] = &qhm_qspi,
1665 [MASTER_QUP_0] = &qhm_qup0,
1666 [MASTER_QUP_1] = &qhm_qup1,
1667 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
1668 [MASTER_PCIE_0] = &xm_pcie3_0,
1669 [MASTER_PCIE_1] = &xm_pcie3_1,
1670 [MASTER_SDCC_1] = &xm_sdc1,
1671 [MASTER_SDCC_2] = &xm_sdc2,
1672 [MASTER_SDCC_4] = &xm_sdc4,
1673 [MASTER_UFS_MEM] = &xm_ufs_mem,
1674 [MASTER_USB2] = &xm_usb2,
1675 [MASTER_USB3_0] = &xm_usb3_0,
1676 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1677 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1678 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1679};
1680
1681static const struct regmap_config sc7280_aggre1_noc_regmap_config = {
1682 .reg_bits = 32,
1683 .reg_stride = 4,
1684 .val_bits = 32,
1685 .max_register = 0x1c080,
1686 .fast_io = true,
1687};
1688
1689static const struct qcom_icc_desc sc7280_aggre1_noc = {
1690 .config = &sc7280_aggre1_noc_regmap_config,
1691 .nodes = aggre1_noc_nodes,
1692 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1693 .bcms = aggre1_noc_bcms,
1694 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1695 .qos_requires_clocks = true,
1696};
1697
1698static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1699 &bcm_ce0,
1700};
1701
1702static const struct regmap_config sc7280_aggre2_noc_regmap_config = {
1703 .reg_bits = 32,
1704 .reg_stride = 4,
1705 .val_bits = 32,
1706 .max_register = 0x2b080,
1707 .fast_io = true,
1708};
1709
1710static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1711 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1712 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
1713 [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
1714 [MASTER_CRYPTO] = &qxm_crypto,
1715 [MASTER_IPA] = &qxm_ipa,
1716 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1717 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1718 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1719};
1720
1721static const struct qcom_icc_desc sc7280_aggre2_noc = {
1722 .config = &sc7280_aggre2_noc_regmap_config,
1723 .nodes = aggre2_noc_nodes,
1724 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1725 .bcms = aggre2_noc_bcms,
1726 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1727 .qos_requires_clocks = true,
1728};
1729
1730static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1731 &bcm_qup0,
1732 &bcm_qup1,
1733};
1734
1735static struct qcom_icc_node * const clk_virt_nodes[] = {
1736 [MASTER_QUP_CORE_0] = &qup0_core_master,
1737 [MASTER_QUP_CORE_1] = &qup1_core_master,
1738 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1739 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1740};
1741
1742static const struct qcom_icc_desc sc7280_clk_virt = {
1743 .nodes = clk_virt_nodes,
1744 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1745 .bcms = clk_virt_bcms,
1746 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1747};
1748
1749static struct qcom_icc_bcm * const cnoc2_bcms[] = {
1750 &bcm_cn1,
1751 &bcm_cn2,
1752};
1753
1754static struct qcom_icc_node * const cnoc2_nodes[] = {
1755 [MASTER_CNOC3_CNOC2] = &qnm_cnoc3_cnoc2,
1756 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1757 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1758 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1759 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1760 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1761 [SLAVE_CDSP_CFG] = &qhs_compute_cfg,
1762 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1763 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1764 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1765 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1766 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1767 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1768 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1769 [SLAVE_HWKM] = &qhs_hwkm,
1770 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1771 [SLAVE_IPA_CFG] = &qhs_ipa,
1772 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1773 [SLAVE_LPASS] = &qhs_lpass_cfg,
1774 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1775 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1776 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1777 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1778 [SLAVE_PDM] = &qhs_pdm,
1779 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1780 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
1781 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
1782 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1783 [SLAVE_QSPI_0] = &qhs_qspi,
1784 [SLAVE_QUP_0] = &qhs_qup0,
1785 [SLAVE_QUP_1] = &qhs_qup1,
1786 [SLAVE_SDCC_1] = &qhs_sdc1,
1787 [SLAVE_SDCC_2] = &qhs_sdc2,
1788 [SLAVE_SDCC_4] = &qhs_sdc4,
1789 [SLAVE_SECURITY] = &qhs_security,
1790 [SLAVE_TCSR] = &qhs_tcsr,
1791 [SLAVE_TLMM] = &qhs_tlmm,
1792 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1793 [SLAVE_USB2] = &qhs_usb2,
1794 [SLAVE_USB3_0] = &qhs_usb3_0,
1795 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1796 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1797 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
1798 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
1799 [SLAVE_CNOC2_CNOC3] = &qns_cnoc2_cnoc3,
1800 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
1801 [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1802};
1803
1804static const struct regmap_config sc7280_cnoc2_regmap_config = {
1805 .reg_bits = 32,
1806 .reg_stride = 4,
1807 .val_bits = 32,
1808 .max_register = 0x1000,
1809 .fast_io = true,
1810};
1811
1812static const struct qcom_icc_desc sc7280_cnoc2 = {
1813 .config = &sc7280_cnoc2_regmap_config,
1814 .nodes = cnoc2_nodes,
1815 .num_nodes = ARRAY_SIZE(cnoc2_nodes),
1816 .bcms = cnoc2_bcms,
1817 .num_bcms = ARRAY_SIZE(cnoc2_bcms),
1818};
1819
1820static struct qcom_icc_bcm * const cnoc3_bcms[] = {
1821 &bcm_cn0,
1822 &bcm_cn1,
1823 &bcm_sn3,
1824 &bcm_sn4,
1825};
1826
1827static struct qcom_icc_node * const cnoc3_nodes[] = {
1828 [MASTER_CNOC2_CNOC3] = &qnm_cnoc2_cnoc3,
1829 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1830 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1831 [SLAVE_AOSS] = &qhs_aoss,
1832 [SLAVE_APPSS] = &qhs_apss,
1833 [SLAVE_CNOC3_CNOC2] = &qns_cnoc3_cnoc2,
1834 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1835 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1836 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1837 [SLAVE_IMEM] = &qxs_imem,
1838 [SLAVE_PIMEM] = &qxs_pimem,
1839 [SLAVE_PCIE_0] = &xs_pcie_0,
1840 [SLAVE_PCIE_1] = &xs_pcie_1,
1841 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1842 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1843};
1844
1845static const struct regmap_config sc7280_cnoc3_regmap_config = {
1846 .reg_bits = 32,
1847 .reg_stride = 4,
1848 .val_bits = 32,
1849 .max_register = 0x1000,
1850 .fast_io = true,
1851};
1852
1853static const struct qcom_icc_desc sc7280_cnoc3 = {
1854 .config = &sc7280_cnoc3_regmap_config,
1855 .nodes = cnoc3_nodes,
1856 .num_nodes = ARRAY_SIZE(cnoc3_nodes),
1857 .bcms = cnoc3_bcms,
1858 .num_bcms = ARRAY_SIZE(cnoc3_bcms),
1859};
1860
1861static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1862};
1863
1864static struct qcom_icc_node * const dc_noc_nodes[] = {
1865 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
1866 [SLAVE_LLCC_CFG] = &qhs_llcc,
1867 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
1868};
1869
1870static const struct regmap_config sc7280_dc_noc_regmap_config = {
1871 .reg_bits = 32,
1872 .reg_stride = 4,
1873 .val_bits = 32,
1874 .max_register = 0x5080,
1875 .fast_io = true,
1876};
1877
1878static const struct qcom_icc_desc sc7280_dc_noc = {
1879 .config = &sc7280_dc_noc_regmap_config,
1880 .nodes = dc_noc_nodes,
1881 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1882 .bcms = dc_noc_bcms,
1883 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
1884};
1885
1886static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1887 &bcm_sh0,
1888 &bcm_sh2,
1889 &bcm_sh3,
1890 &bcm_sh4,
1891};
1892
1893static struct qcom_icc_node * const gem_noc_nodes[] = {
1894 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1895 [MASTER_SYS_TCU] = &alm_sys_tcu,
1896 [MASTER_APPSS_PROC] = &chm_apps,
1897 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1898 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
1899 [MASTER_GFX3D] = &qnm_gpu,
1900 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1901 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1902 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1903 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1904 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1905 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1906 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
1907 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1908 [SLAVE_LLCC] = &qns_llcc,
1909 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1910 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
1911 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
1912 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
1913};
1914
1915static const struct regmap_config sc7280_gem_noc_regmap_config = {
1916 .reg_bits = 32,
1917 .reg_stride = 4,
1918 .val_bits = 32,
1919 .max_register = 0xe2200,
1920 .fast_io = true,
1921};
1922
1923static const struct qcom_icc_desc sc7280_gem_noc = {
1924 .config = &sc7280_gem_noc_regmap_config,
1925 .nodes = gem_noc_nodes,
1926 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1927 .bcms = gem_noc_bcms,
1928 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1929};
1930
1931static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1932};
1933
1934static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1935 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1936 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1937 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1938 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1939 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1940 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1941 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1942};
1943
1944static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = {
1945 .reg_bits = 32,
1946 .reg_stride = 4,
1947 .val_bits = 32,
1948 .max_register = 0xf080,
1949 .fast_io = true,
1950};
1951
1952static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
1953 .config = &sc7280_lpass_ag_noc_regmap_config,
1954 .nodes = lpass_ag_noc_nodes,
1955 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1956 .bcms = lpass_ag_noc_bcms,
1957 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1958};
1959
1960static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1961 &bcm_acv,
1962 &bcm_mc0,
1963};
1964
1965static struct qcom_icc_node * const mc_virt_nodes[] = {
1966 [MASTER_LLCC] = &llcc_mc,
1967 [SLAVE_EBI1] = &ebi,
1968};
1969
1970static const struct regmap_config sc7280_mc_virt_regmap_config = {
1971 .reg_bits = 32,
1972 .reg_stride = 4,
1973 .val_bits = 32,
1974 .max_register = 0x4,
1975 .fast_io = true,
1976};
1977
1978static const struct qcom_icc_desc sc7280_mc_virt = {
1979 .config = &sc7280_mc_virt_regmap_config,
1980 .nodes = mc_virt_nodes,
1981 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1982 .bcms = mc_virt_bcms,
1983 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1984};
1985
1986static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1987 &bcm_mm0,
1988 &bcm_mm1,
1989 &bcm_mm4,
1990 &bcm_mm5,
1991};
1992
1993static struct qcom_icc_node * const mmss_noc_nodes[] = {
1994 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
1995 [MASTER_VIDEO_P0] = &qnm_video0,
1996 [MASTER_VIDEO_PROC] = &qnm_video_cpu,
1997 [MASTER_CAMNOC_HF] = &qxm_camnoc_hf,
1998 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp,
1999 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
2000 [MASTER_MDP0] = &qxm_mdp0,
2001 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
2002 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
2003 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
2004};
2005
2006static const struct regmap_config sc7280_mmss_noc_regmap_config = {
2007 .reg_bits = 32,
2008 .reg_stride = 4,
2009 .val_bits = 32,
2010 .max_register = 0x1e080,
2011 .fast_io = true,
2012};
2013
2014static const struct qcom_icc_desc sc7280_mmss_noc = {
2015 .config = &sc7280_mmss_noc_regmap_config,
2016 .nodes = mmss_noc_nodes,
2017 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2018 .bcms = mmss_noc_bcms,
2019 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2020};
2021
2022static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
2023 &bcm_co0,
2024 &bcm_co3,
2025};
2026
2027static struct qcom_icc_node * const nsp_noc_nodes[] = {
2028 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
2029 [MASTER_CDSP_PROC] = &qxm_nsp,
2030 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
2031 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
2032};
2033
2034static const struct regmap_config sc7280_nsp_noc_regmap_config = {
2035 .reg_bits = 32,
2036 .reg_stride = 4,
2037 .val_bits = 32,
2038 .max_register = 0x10000,
2039 .fast_io = true,
2040};
2041
2042static const struct qcom_icc_desc sc7280_nsp_noc = {
2043 .config = &sc7280_nsp_noc_regmap_config,
2044 .nodes = nsp_noc_nodes,
2045 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
2046 .bcms = nsp_noc_bcms,
2047 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
2048};
2049
2050static struct qcom_icc_bcm * const system_noc_bcms[] = {
2051 &bcm_sn0,
2052 &bcm_sn2,
2053 &bcm_sn7,
2054 &bcm_sn8,
2055};
2056
2057static struct qcom_icc_node * const system_noc_nodes[] = {
2058 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2059 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2060 [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
2061 [MASTER_PIMEM] = &qxm_pimem,
2062 [MASTER_GIC] = &xm_gic,
2063 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
2064 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2065 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
2066};
2067
2068static const struct regmap_config sc7280_system_noc_regmap_config = {
2069 .reg_bits = 32,
2070 .reg_stride = 4,
2071 .val_bits = 32,
2072 .max_register = 0x15480,
2073 .fast_io = true,
2074};
2075
2076static const struct qcom_icc_desc sc7280_system_noc = {
2077 .config = &sc7280_system_noc_regmap_config,
2078 .nodes = system_noc_nodes,
2079 .num_nodes = ARRAY_SIZE(system_noc_nodes),
2080 .bcms = system_noc_bcms,
2081 .num_bcms = ARRAY_SIZE(system_noc_bcms),
2082};
2083
2084static const struct of_device_id qnoc_of_match[] = {
2085 { .compatible = "qcom,sc7280-aggre1-noc",
2086 .data = &sc7280_aggre1_noc},
2087 { .compatible = "qcom,sc7280-aggre2-noc",
2088 .data = &sc7280_aggre2_noc},
2089 { .compatible = "qcom,sc7280-clk-virt",
2090 .data = &sc7280_clk_virt},
2091 { .compatible = "qcom,sc7280-cnoc2",
2092 .data = &sc7280_cnoc2},
2093 { .compatible = "qcom,sc7280-cnoc3",
2094 .data = &sc7280_cnoc3},
2095 { .compatible = "qcom,sc7280-dc-noc",
2096 .data = &sc7280_dc_noc},
2097 { .compatible = "qcom,sc7280-gem-noc",
2098 .data = &sc7280_gem_noc},
2099 { .compatible = "qcom,sc7280-lpass-ag-noc",
2100 .data = &sc7280_lpass_ag_noc},
2101 { .compatible = "qcom,sc7280-mc-virt",
2102 .data = &sc7280_mc_virt},
2103 { .compatible = "qcom,sc7280-mmss-noc",
2104 .data = &sc7280_mmss_noc},
2105 { .compatible = "qcom,sc7280-nsp-noc",
2106 .data = &sc7280_nsp_noc},
2107 { .compatible = "qcom,sc7280-system-noc",
2108 .data = &sc7280_system_noc},
2109 { }
2110};
2111MODULE_DEVICE_TABLE(of, qnoc_of_match);
2112
2113static struct platform_driver qnoc_driver = {
2114 .probe = qcom_icc_rpmh_probe,
2115 .remove = qcom_icc_rpmh_remove,
2116 .driver = {
2117 .name = "qnoc-sc7280",
2118 .of_match_table = qnoc_of_match,
2119 .sync_state = icc_sync_state,
2120 },
2121};
2122module_platform_driver(qnoc_driver);
2123
2124MODULE_DESCRIPTION("SC7280 NoC driver");
2125MODULE_LICENSE("GPL v2");