Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
4 *
5 * Authors:
6 * Peter Pan <peterpandong@micron.com>
7 */
8#ifndef __LINUX_MTD_SPINAND_H
9#define __LINUX_MTD_SPINAND_H
10
11#include <linux/mutex.h>
12#include <linux/bitops.h>
13#include <linux/device.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/nand.h>
16#include <linux/spi/spi.h>
17#include <linux/spi/spi-mem.h>
18
19/**
20 * Standard SPI NAND flash operations
21 */
22
23#define SPINAND_RESET_1S_0_0_OP \
24 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \
25 SPI_MEM_OP_NO_ADDR, \
26 SPI_MEM_OP_NO_DUMMY, \
27 SPI_MEM_OP_NO_DATA)
28
29#define SPINAND_WR_EN_DIS_1S_0_0_OP(enable) \
30 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \
31 SPI_MEM_OP_NO_ADDR, \
32 SPI_MEM_OP_NO_DUMMY, \
33 SPI_MEM_OP_NO_DATA)
34
35#define SPINAND_READID_1S_1S_1S_OP(naddr, ndummy, buf, len) \
36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
37 SPI_MEM_OP_ADDR(naddr, 0, 1), \
38 SPI_MEM_OP_DUMMY(ndummy, 1), \
39 SPI_MEM_OP_DATA_IN(len, buf, 1))
40
41#define SPINAND_SET_FEATURE_1S_1S_1S_OP(reg, valptr) \
42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
43 SPI_MEM_OP_ADDR(1, reg, 1), \
44 SPI_MEM_OP_NO_DUMMY, \
45 SPI_MEM_OP_DATA_OUT(1, valptr, 1))
46
47#define SPINAND_GET_FEATURE_1S_1S_1S_OP(reg, valptr) \
48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \
49 SPI_MEM_OP_ADDR(1, reg, 1), \
50 SPI_MEM_OP_NO_DUMMY, \
51 SPI_MEM_OP_DATA_IN(1, valptr, 1))
52
53#define SPINAND_BLK_ERASE_1S_1S_0_OP(addr) \
54 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \
55 SPI_MEM_OP_ADDR(3, addr, 1), \
56 SPI_MEM_OP_NO_DUMMY, \
57 SPI_MEM_OP_NO_DATA)
58
59#define SPINAND_PAGE_READ_1S_1S_0_OP(addr) \
60 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \
61 SPI_MEM_OP_ADDR(3, addr, 1), \
62 SPI_MEM_OP_NO_DUMMY, \
63 SPI_MEM_OP_NO_DATA)
64
65#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(addr, ndummy, buf, len, ...) \
66 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
67 SPI_MEM_OP_ADDR(2, addr, 1), \
68 SPI_MEM_OP_DUMMY(ndummy, 1), \
69 SPI_MEM_OP_DATA_IN(len, buf, 1), \
70 SPI_MEM_OP_MAX_FREQ(__VA_ARGS__ + 0))
71
72#define SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(addr, ndummy, buf, len) \
73 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
74 SPI_MEM_OP_ADDR(2, addr, 1), \
75 SPI_MEM_OP_DUMMY(ndummy, 1), \
76 SPI_MEM_OP_DATA_IN(len, buf, 1))
77
78#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_1S_OP(addr, ndummy, buf, len) \
79 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
80 SPI_MEM_OP_ADDR(3, addr, 1), \
81 SPI_MEM_OP_DUMMY(ndummy, 1), \
82 SPI_MEM_OP_DATA_IN(len, buf, 1))
83
84#define SPINAND_PAGE_READ_FROM_CACHE_FAST_3A_1S_1S_1S_OP(addr, ndummy, buf, len) \
85 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
86 SPI_MEM_OP_ADDR(3, addr, 1), \
87 SPI_MEM_OP_DUMMY(ndummy, 1), \
88 SPI_MEM_OP_DATA_IN(len, buf, 1))
89
90#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_1D_OP(addr, ndummy, buf, len, freq) \
91 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \
92 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
93 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
94 SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \
95 SPI_MEM_OP_MAX_FREQ(freq))
96
97#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(addr, ndummy, buf, len) \
98 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
99 SPI_MEM_OP_ADDR(2, addr, 1), \
100 SPI_MEM_OP_DUMMY(ndummy, 1), \
101 SPI_MEM_OP_DATA_IN(len, buf, 2))
102
103#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_2S_OP(addr, ndummy, buf, len) \
104 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
105 SPI_MEM_OP_ADDR(3, addr, 1), \
106 SPI_MEM_OP_DUMMY(ndummy, 1), \
107 SPI_MEM_OP_DATA_IN(len, buf, 2))
108
109#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_2D_OP(addr, ndummy, buf, len, freq) \
110 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3d, 1), \
111 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
112 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
113 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
114 SPI_MEM_OP_MAX_FREQ(freq))
115
116#define SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(addr, ndummy, buf, len, ...) \
117 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
118 SPI_MEM_OP_ADDR(2, addr, 2), \
119 SPI_MEM_OP_DUMMY(ndummy, 2), \
120 SPI_MEM_OP_DATA_IN(len, buf, 2), \
121 SPI_MEM_OP_MAX_FREQ(__VA_ARGS__ + 0))
122
123#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_2S_2S_OP(addr, ndummy, buf, len) \
124 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
125 SPI_MEM_OP_ADDR(3, addr, 2), \
126 SPI_MEM_OP_DUMMY(ndummy, 2), \
127 SPI_MEM_OP_DATA_IN(len, buf, 2))
128
129#define SPINAND_PAGE_READ_FROM_CACHE_1S_2D_2D_OP(addr, ndummy, buf, len, freq) \
130 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \
131 SPI_MEM_DTR_OP_ADDR(2, addr, 2), \
132 SPI_MEM_DTR_OP_DUMMY(ndummy, 2), \
133 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
134 SPI_MEM_OP_MAX_FREQ(freq))
135
136#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(addr, ndummy, buf, len) \
137 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
138 SPI_MEM_OP_ADDR(2, addr, 1), \
139 SPI_MEM_OP_DUMMY(ndummy, 1), \
140 SPI_MEM_OP_DATA_IN(len, buf, 4))
141
142#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_4S_OP(addr, ndummy, buf, len) \
143 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
144 SPI_MEM_OP_ADDR(3, addr, 1), \
145 SPI_MEM_OP_DUMMY(ndummy, 1), \
146 SPI_MEM_OP_DATA_IN(len, buf, 4))
147
148#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_4D_OP(addr, ndummy, buf, len, freq) \
149 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \
150 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
151 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
152 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
153 SPI_MEM_OP_MAX_FREQ(freq))
154
155#define SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(addr, ndummy, buf, len, ...) \
156 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
157 SPI_MEM_OP_ADDR(2, addr, 4), \
158 SPI_MEM_OP_DUMMY(ndummy, 4), \
159 SPI_MEM_OP_DATA_IN(len, buf, 4), \
160 SPI_MEM_OP_MAX_FREQ(__VA_ARGS__ + 0))
161
162#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_4S_4S_OP(addr, ndummy, buf, len) \
163 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
164 SPI_MEM_OP_ADDR(3, addr, 4), \
165 SPI_MEM_OP_DUMMY(ndummy, 4), \
166 SPI_MEM_OP_DATA_IN(len, buf, 4))
167
168#define SPINAND_PAGE_READ_FROM_CACHE_1S_4D_4D_OP(addr, ndummy, buf, len, freq) \
169 SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \
170 SPI_MEM_DTR_OP_ADDR(2, addr, 4), \
171 SPI_MEM_DTR_OP_DUMMY(ndummy, 4), \
172 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
173 SPI_MEM_OP_MAX_FREQ(freq))
174
175#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_8S_OP(addr, ndummy, buf, len, freq) \
176 SPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1), \
177 SPI_MEM_OP_ADDR(2, addr, 1), \
178 SPI_MEM_OP_DUMMY(ndummy, 1), \
179 SPI_MEM_OP_DATA_IN(len, buf, 8), \
180 SPI_MEM_OP_MAX_FREQ(freq))
181
182#define SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(addr, ndummy, buf, len, freq) \
183 SPI_MEM_OP(SPI_MEM_OP_CMD(0xcb, 1), \
184 SPI_MEM_OP_ADDR(2, addr, 8), \
185 SPI_MEM_OP_DUMMY(ndummy, 8), \
186 SPI_MEM_OP_DATA_IN(len, buf, 8), \
187 SPI_MEM_OP_MAX_FREQ(freq))
188
189#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(addr, ndummy, buf, len, freq) \
190 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9d, 1), \
191 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
192 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
193 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \
194 SPI_MEM_OP_MAX_FREQ(freq))
195
196#define SPINAND_PROG_EXEC_1S_1S_0_OP(addr) \
197 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
198 SPI_MEM_OP_ADDR(3, addr, 1), \
199 SPI_MEM_OP_NO_DUMMY, \
200 SPI_MEM_OP_NO_DATA)
201
202#define SPINAND_PROG_LOAD_1S_1S_1S_OP(reset, addr, buf, len) \
203 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \
204 SPI_MEM_OP_ADDR(2, addr, 1), \
205 SPI_MEM_OP_NO_DUMMY, \
206 SPI_MEM_OP_DATA_OUT(len, buf, 1))
207
208#define SPINAND_PROG_LOAD_1S_1S_4S_OP(reset, addr, buf, len) \
209 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \
210 SPI_MEM_OP_ADDR(2, addr, 1), \
211 SPI_MEM_OP_NO_DUMMY, \
212 SPI_MEM_OP_DATA_OUT(len, buf, 4))
213
214#define SPINAND_PROG_LOAD_1S_1S_8S_OP(addr, buf, len) \
215 SPI_MEM_OP(SPI_MEM_OP_CMD(0x82, 1), \
216 SPI_MEM_OP_ADDR(2, addr, 1), \
217 SPI_MEM_OP_NO_DUMMY, \
218 SPI_MEM_OP_DATA_OUT(len, buf, 8))
219
220#define SPINAND_PROG_LOAD_1S_8S_8S_OP(reset, addr, buf, len) \
221 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0xc2 : 0xc4, 1), \
222 SPI_MEM_OP_ADDR(2, addr, 8), \
223 SPI_MEM_OP_NO_DUMMY, \
224 SPI_MEM_OP_DATA_OUT(len, buf, 8))
225
226/**
227 * Standard SPI NAND flash commands
228 */
229#define SPINAND_CMD_PROG_LOAD_X4 0x32
230#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34
231
232/* feature register */
233#define REG_BLOCK_LOCK 0xa0
234#define BL_ALL_UNLOCKED 0x00
235
236/* configuration register */
237#define REG_CFG 0xb0
238#define CFG_OTP_ENABLE BIT(6)
239#define CFG_ECC_ENABLE BIT(4)
240#define CFG_QUAD_ENABLE BIT(0)
241
242/* status register */
243#define REG_STATUS 0xc0
244#define STATUS_BUSY BIT(0)
245#define STATUS_ERASE_FAILED BIT(2)
246#define STATUS_PROG_FAILED BIT(3)
247#define STATUS_ECC_MASK GENMASK(5, 4)
248#define STATUS_ECC_NO_BITFLIPS (0 << 4)
249#define STATUS_ECC_HAS_BITFLIPS (1 << 4)
250#define STATUS_ECC_UNCOR_ERROR (2 << 4)
251
252struct spinand_op;
253struct spinand_device;
254
255#define SPINAND_MAX_ID_LEN 5
256/*
257 * For erase, write and read operation, we got the following timings :
258 * tBERS (erase) 1ms to 4ms
259 * tPROG 300us to 400us
260 * tREAD 25us to 100us
261 * In order to minimize latency, the min value is divided by 4 for the
262 * initial delay, and dividing by 20 for the poll delay.
263 * For reset, 5us/10us/500us if the device is respectively
264 * reading/programming/erasing when the RESET occurs. Since we always
265 * issue a RESET when the device is IDLE, 5us is selected for both initial
266 * and poll delay.
267 */
268#define SPINAND_READ_INITIAL_DELAY_US 6
269#define SPINAND_READ_POLL_DELAY_US 5
270#define SPINAND_RESET_INITIAL_DELAY_US 5
271#define SPINAND_RESET_POLL_DELAY_US 5
272#define SPINAND_WRITE_INITIAL_DELAY_US 75
273#define SPINAND_WRITE_POLL_DELAY_US 15
274#define SPINAND_ERASE_INITIAL_DELAY_US 250
275#define SPINAND_ERASE_POLL_DELAY_US 50
276
277#define SPINAND_WAITRDY_TIMEOUT_MS 400
278
279/**
280 * struct spinand_id - SPI NAND id structure
281 * @data: buffer containing the id bytes. Currently 4 bytes large, but can
282 * be extended if required
283 * @len: ID length
284 */
285struct spinand_id {
286 u8 data[SPINAND_MAX_ID_LEN];
287 int len;
288};
289
290enum spinand_readid_method {
291 SPINAND_READID_METHOD_OPCODE,
292 SPINAND_READID_METHOD_OPCODE_ADDR,
293 SPINAND_READID_METHOD_OPCODE_DUMMY,
294};
295
296/**
297 * struct spinand_devid - SPI NAND device id structure
298 * @id: device id of current chip
299 * @len: number of bytes in device id
300 * @method: method to read chip id
301 * There are 3 possible variants:
302 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
303 * after read_id opcode.
304 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
305 * read_id opcode + 1-byte address.
306 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
307 * read_id opcode + 1 dummy byte.
308 */
309struct spinand_devid {
310 const u8 *id;
311 const u8 len;
312 const enum spinand_readid_method method;
313};
314
315/**
316 * struct manufacurer_ops - SPI NAND manufacturer specific operations
317 * @init: initialize a SPI NAND device
318 * @cleanup: cleanup a SPI NAND device
319 *
320 * Each SPI NAND manufacturer driver should implement this interface so that
321 * NAND chips coming from this vendor can be initialized properly.
322 */
323struct spinand_manufacturer_ops {
324 int (*init)(struct spinand_device *spinand);
325 void (*cleanup)(struct spinand_device *spinand);
326};
327
328/**
329 * struct spinand_manufacturer - SPI NAND manufacturer instance
330 * @id: manufacturer ID
331 * @name: manufacturer name
332 * @devid_len: number of bytes in device ID
333 * @chips: supported SPI NANDs under current manufacturer
334 * @nchips: number of SPI NANDs available in chips array
335 * @ops: manufacturer operations
336 */
337struct spinand_manufacturer {
338 u8 id;
339 char *name;
340 const struct spinand_info *chips;
341 const size_t nchips;
342 const struct spinand_manufacturer_ops *ops;
343};
344
345/* SPI NAND manufacturers */
346extern const struct spinand_manufacturer alliancememory_spinand_manufacturer;
347extern const struct spinand_manufacturer ato_spinand_manufacturer;
348extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
349extern const struct spinand_manufacturer foresee_spinand_manufacturer;
350extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
351extern const struct spinand_manufacturer macronix_spinand_manufacturer;
352extern const struct spinand_manufacturer micron_spinand_manufacturer;
353extern const struct spinand_manufacturer paragon_spinand_manufacturer;
354extern const struct spinand_manufacturer skyhigh_spinand_manufacturer;
355extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
356extern const struct spinand_manufacturer winbond_spinand_manufacturer;
357extern const struct spinand_manufacturer xtx_spinand_manufacturer;
358
359/**
360 * struct spinand_op_variants - SPI NAND operation variants
361 * @ops: the list of variants for a given operation
362 * @nops: the number of variants
363 *
364 * Some operations like read-from-cache/write-to-cache have several variants
365 * depending on the number of IO lines you use to transfer data or address
366 * cycles. This structure is a way to describe the different variants supported
367 * by a chip and let the core pick the best one based on the SPI mem controller
368 * capabilities.
369 */
370struct spinand_op_variants {
371 const struct spi_mem_op *ops;
372 unsigned int nops;
373};
374
375#define SPINAND_OP_VARIANTS(name, ...) \
376 const struct spinand_op_variants name = { \
377 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \
378 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \
379 sizeof(struct spi_mem_op), \
380 }
381
382/**
383 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
384 * chip
385 * @get_status: get the ECC status. Should return a positive number encoding
386 * the number of corrected bitflips if correction was possible or
387 * -EBADMSG if there are uncorrectable errors. I can also return
388 * other negative error codes if the error is not caused by
389 * uncorrectable bitflips
390 * @ooblayout: the OOB layout used by the on-die ECC implementation
391 */
392struct spinand_ecc_info {
393 int (*get_status)(struct spinand_device *spinand, u8 status);
394 const struct mtd_ooblayout_ops *ooblayout;
395};
396
397#define SPINAND_HAS_QE_BIT BIT(0)
398#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
399#define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2)
400#define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3)
401#define SPINAND_NO_RAW_ACCESS BIT(4)
402
403/**
404 * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
405 * @status: status of the last wait operation that will be used in case
406 * ->get_status() is not populated by the spinand device.
407 */
408struct spinand_ondie_ecc_conf {
409 u8 status;
410};
411
412/**
413 * struct spinand_otp_layout - structure to describe the SPI NAND OTP area
414 * @npages: number of pages in the OTP
415 * @start_page: start page of the user/factory OTP area.
416 */
417struct spinand_otp_layout {
418 unsigned int npages;
419 unsigned int start_page;
420};
421
422/**
423 * struct spinand_fact_otp_ops - SPI NAND OTP methods for factory area
424 * @info: get the OTP area information
425 * @read: read from the SPI NAND OTP area
426 */
427struct spinand_fact_otp_ops {
428 int (*info)(struct spinand_device *spinand, size_t len,
429 struct otp_info *buf, size_t *retlen);
430 int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
431 size_t *retlen, u8 *buf);
432};
433
434/**
435 * struct spinand_user_otp_ops - SPI NAND OTP methods for user area
436 * @info: get the OTP area information
437 * @lock: lock an OTP region
438 * @erase: erase an OTP region
439 * @read: read from the SPI NAND OTP area
440 * @write: write to the SPI NAND OTP area
441 */
442struct spinand_user_otp_ops {
443 int (*info)(struct spinand_device *spinand, size_t len,
444 struct otp_info *buf, size_t *retlen);
445 int (*lock)(struct spinand_device *spinand, loff_t from, size_t len);
446 int (*erase)(struct spinand_device *spinand, loff_t from, size_t len);
447 int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
448 size_t *retlen, u8 *buf);
449 int (*write)(struct spinand_device *spinand, loff_t from, size_t len,
450 size_t *retlen, const u8 *buf);
451};
452
453/**
454 * struct spinand_fact_otp - SPI NAND OTP grouping structure for factory area
455 * @layout: OTP region layout
456 * @ops: OTP access ops
457 */
458struct spinand_fact_otp {
459 const struct spinand_otp_layout layout;
460 const struct spinand_fact_otp_ops *ops;
461};
462
463/**
464 * struct spinand_user_otp - SPI NAND OTP grouping structure for user area
465 * @layout: OTP region layout
466 * @ops: OTP access ops
467 */
468struct spinand_user_otp {
469 const struct spinand_otp_layout layout;
470 const struct spinand_user_otp_ops *ops;
471};
472
473/**
474 * struct spinand_info - Structure used to describe SPI NAND chips
475 * @model: model name
476 * @devid: device ID
477 * @flags: OR-ing of the SPINAND_XXX flags
478 * @memorg: memory organization
479 * @eccreq: ECC requirements
480 * @eccinfo: on-die ECC info
481 * @op_variants: operations variants
482 * @op_variants.read_cache: variants of the read-cache operation
483 * @op_variants.write_cache: variants of the write-cache operation
484 * @op_variants.update_cache: variants of the update-cache operation
485 * @select_target: function used to select a target/die. Required only for
486 * multi-die chips
487 * @set_cont_read: enable/disable continuous cached reads
488 * @fact_otp: SPI NAND factory OTP info.
489 * @user_otp: SPI NAND user OTP info.
490 * @read_retries: the number of read retry modes supported
491 * @set_read_retry: enable/disable read retry for data recovery
492 *
493 * Each SPI NAND manufacturer driver should have a spinand_info table
494 * describing all the chips supported by the driver.
495 */
496struct spinand_info {
497 const char *model;
498 struct spinand_devid devid;
499 u32 flags;
500 struct nand_memory_organization memorg;
501 struct nand_ecc_props eccreq;
502 struct spinand_ecc_info eccinfo;
503 struct {
504 const struct spinand_op_variants *read_cache;
505 const struct spinand_op_variants *write_cache;
506 const struct spinand_op_variants *update_cache;
507 } op_variants;
508 int (*select_target)(struct spinand_device *spinand,
509 unsigned int target);
510 int (*set_cont_read)(struct spinand_device *spinand,
511 bool enable);
512 struct spinand_fact_otp fact_otp;
513 struct spinand_user_otp user_otp;
514 unsigned int read_retries;
515 int (*set_read_retry)(struct spinand_device *spinand,
516 unsigned int read_retry);
517};
518
519#define SPINAND_ID(__method, ...) \
520 { \
521 .id = (const u8[]){ __VA_ARGS__ }, \
522 .len = sizeof((u8[]){ __VA_ARGS__ }), \
523 .method = __method, \
524 }
525
526#define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
527 { \
528 .read_cache = __read, \
529 .write_cache = __write, \
530 .update_cache = __update, \
531 }
532
533#define SPINAND_ECCINFO(__ooblayout, __get_status) \
534 .eccinfo = { \
535 .ooblayout = __ooblayout, \
536 .get_status = __get_status, \
537 }
538
539#define SPINAND_SELECT_TARGET(__func) \
540 .select_target = __func
541
542#define SPINAND_CONT_READ(__set_cont_read) \
543 .set_cont_read = __set_cont_read
544
545#define SPINAND_FACT_OTP_INFO(__npages, __start_page, __ops) \
546 .fact_otp = { \
547 .layout = { \
548 .npages = __npages, \
549 .start_page = __start_page, \
550 }, \
551 .ops = __ops, \
552 }
553
554#define SPINAND_USER_OTP_INFO(__npages, __start_page, __ops) \
555 .user_otp = { \
556 .layout = { \
557 .npages = __npages, \
558 .start_page = __start_page, \
559 }, \
560 .ops = __ops, \
561 }
562
563#define SPINAND_READ_RETRY(__read_retries, __set_read_retry) \
564 .read_retries = __read_retries, \
565 .set_read_retry = __set_read_retry
566
567#define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \
568 __flags, ...) \
569 { \
570 .model = __model, \
571 .devid = __id, \
572 .memorg = __memorg, \
573 .eccreq = __eccreq, \
574 .op_variants = __op_variants, \
575 .flags = __flags, \
576 __VA_ARGS__ \
577 }
578
579struct spinand_dirmap {
580 struct spi_mem_dirmap_desc *wdesc;
581 struct spi_mem_dirmap_desc *rdesc;
582 struct spi_mem_dirmap_desc *wdesc_ecc;
583 struct spi_mem_dirmap_desc *rdesc_ecc;
584};
585
586/**
587 * struct spinand_device - SPI NAND device instance
588 * @base: NAND device instance
589 * @spimem: pointer to the SPI mem object
590 * @lock: lock used to serialize accesses to the NAND
591 * @id: NAND ID as returned by READ_ID
592 * @flags: NAND flags
593 * @op_templates: various SPI mem op templates
594 * @op_templates.read_cache: read cache op template
595 * @op_templates.write_cache: write cache op template
596 * @op_templates.update_cache: update cache op template
597 * @select_target: select a specific target/die. Usually called before sending
598 * a command addressing a page or an eraseblock embedded in
599 * this die. Only required if your chip exposes several dies
600 * @cur_target: currently selected target/die
601 * @eccinfo: on-die ECC information
602 * @cfg_cache: config register cache. One entry per die
603 * @databuf: bounce buffer for data
604 * @oobbuf: bounce buffer for OOB data
605 * @scratchbuf: buffer used for everything but page accesses. This is needed
606 * because the spi-mem interface explicitly requests that buffers
607 * passed in spi_mem_op be DMA-able, so we can't based the bufs on
608 * the stack
609 * @manufacturer: SPI NAND manufacturer information
610 * @cont_read_possible: Field filled by the core once the whole system
611 * configuration is known to tell whether continuous reads are
612 * suitable to use or not in general with this chip/configuration.
613 * A per-transfer check must of course be done to ensure it is
614 * actually relevant to enable this feature.
615 * @set_cont_read: Enable/disable the continuous read feature
616 * @priv: manufacturer private data
617 * @fact_otp: SPI NAND factory OTP info.
618 * @user_otp: SPI NAND user OTP info.
619 * @read_retries: the number of read retry modes supported
620 * @set_read_retry: Enable/disable the read retry feature
621 */
622struct spinand_device {
623 struct nand_device base;
624 struct spi_mem *spimem;
625 struct mutex lock;
626 struct spinand_id id;
627 u32 flags;
628
629 struct {
630 const struct spi_mem_op *read_cache;
631 const struct spi_mem_op *write_cache;
632 const struct spi_mem_op *update_cache;
633 } op_templates;
634
635 struct spinand_dirmap *dirmaps;
636
637 int (*select_target)(struct spinand_device *spinand,
638 unsigned int target);
639 unsigned int cur_target;
640
641 struct spinand_ecc_info eccinfo;
642
643 u8 *cfg_cache;
644 u8 *databuf;
645 u8 *oobbuf;
646 u8 *scratchbuf;
647 const struct spinand_manufacturer *manufacturer;
648 void *priv;
649
650 bool cont_read_possible;
651 int (*set_cont_read)(struct spinand_device *spinand,
652 bool enable);
653
654 const struct spinand_fact_otp *fact_otp;
655 const struct spinand_user_otp *user_otp;
656
657 unsigned int read_retries;
658 int (*set_read_retry)(struct spinand_device *spinand,
659 unsigned int retry_mode);
660};
661
662/**
663 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
664 * @mtd: MTD instance
665 *
666 * Return: the SPI NAND device attached to @mtd.
667 */
668static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
669{
670 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
671}
672
673/**
674 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
675 * @spinand: SPI NAND device
676 *
677 * Return: the MTD device embedded in @spinand.
678 */
679static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
680{
681 return nanddev_to_mtd(&spinand->base);
682}
683
684/**
685 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
686 * @nand: NAND object
687 *
688 * Return: the SPI NAND device embedding @nand.
689 */
690static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
691{
692 return container_of(nand, struct spinand_device, base);
693}
694
695/**
696 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
697 * @spinand: SPI NAND device
698 *
699 * Return: the NAND device embedded in @spinand.
700 */
701static inline struct nand_device *
702spinand_to_nand(struct spinand_device *spinand)
703{
704 return &spinand->base;
705}
706
707/**
708 * spinand_set_of_node - Attach a DT node to a SPI NAND device
709 * @spinand: SPI NAND device
710 * @np: DT node
711 *
712 * Attach a DT node to a SPI NAND device.
713 */
714static inline void spinand_set_of_node(struct spinand_device *spinand,
715 struct device_node *np)
716{
717 nanddev_set_of_node(&spinand->base, np);
718}
719
720int spinand_match_and_init(struct spinand_device *spinand,
721 const struct spinand_info *table,
722 unsigned int table_size,
723 enum spinand_readid_method rdid_method);
724
725int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
726int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val);
727int spinand_select_target(struct spinand_device *spinand, unsigned int target);
728
729int spinand_wait(struct spinand_device *spinand, unsigned long initial_delay_us,
730 unsigned long poll_delay_us, u8 *s);
731
732int spinand_read_page(struct spinand_device *spinand,
733 const struct nand_page_io_req *req);
734
735int spinand_write_page(struct spinand_device *spinand,
736 const struct nand_page_io_req *req);
737
738size_t spinand_otp_page_size(struct spinand_device *spinand);
739size_t spinand_fact_otp_size(struct spinand_device *spinand);
740size_t spinand_user_otp_size(struct spinand_device *spinand);
741
742int spinand_fact_otp_read(struct spinand_device *spinand, loff_t ofs,
743 size_t len, size_t *retlen, u8 *buf);
744int spinand_user_otp_read(struct spinand_device *spinand, loff_t ofs,
745 size_t len, size_t *retlen, u8 *buf);
746int spinand_user_otp_write(struct spinand_device *spinand, loff_t ofs,
747 size_t len, size_t *retlen, const u8 *buf);
748
749int spinand_set_mtd_otp_ops(struct spinand_device *spinand);
750
751#endif /* __LINUX_MTD_SPINAND_H */