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1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2016-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#include "kfd_device_queue_manager.h"
26#include "vega10_enum.h"
27#include "gc/gc_9_4_3_sh_mask.h"
28
29static int update_qpd_v9(struct device_queue_manager *dqm,
30 struct qcm_process_device *qpd);
31static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
32 struct qcm_process_device *qpd);
33static bool set_cache_memory_policy_v9(struct device_queue_manager *dqm,
34 struct qcm_process_device *qpd,
35 enum cache_policy default_policy,
36 enum cache_policy alternate_policy,
37 void __user *alternate_aperture_base,
38 uint64_t alternate_aperture_size,
39 u32 misc_process_properties);
40
41void device_queue_manager_init_v9(
42 struct device_queue_manager_asic_ops *asic_ops)
43{
44 asic_ops->set_cache_memory_policy = set_cache_memory_policy_v9;
45 asic_ops->update_qpd = update_qpd_v9;
46 asic_ops->init_sdma_vm = init_sdma_vm_v9;
47 asic_ops->mqd_manager_init = mqd_manager_init_v9;
48}
49
50static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
51{
52 uint32_t shared_base = pdd->lds_base >> 48;
53 uint32_t private_base = pdd->scratch_base >> 48;
54
55 return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
56 private_base;
57}
58
59static bool set_cache_memory_policy_v9(struct device_queue_manager *dqm,
60 struct qcm_process_device *qpd,
61 enum cache_policy default_policy,
62 enum cache_policy alternate_policy,
63 void __user *alternate_aperture_base,
64 uint64_t alternate_aperture_size,
65 u32 misc_process_properties)
66{
67 qpd->sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
68 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
69
70 if (dqm->dev->kfd->noretry)
71 qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
72
73 if (KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 3) ||
74 KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 4))
75 qpd->sh_mem_config |= (1 << SH_MEM_CONFIG__F8_MODE__SHIFT);
76
77 if (KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 5, 0)) {
78 if (misc_process_properties & KFD_PROC_FLAG_MFMA_HIGH_PRECISION)
79 qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__PRECISION_MODE__SHIFT;
80 }
81
82 qpd->sh_mem_ape1_limit = 0;
83 qpd->sh_mem_ape1_base = 0;
84 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));
85
86 pr_debug("sh_mem_bases 0x%X sh_mem_config 0x%X\n", qpd->sh_mem_bases,
87 qpd->sh_mem_config);
88 return true;
89}
90
91static int update_qpd_v9(struct device_queue_manager *dqm,
92 struct qcm_process_device *qpd)
93{
94 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
95
96 pdd = qpd_to_pdd(qpd);
97
98 /* check if sh_mem_config register already configured */
99 if (qpd->sh_mem_config == 0) {
100 qpd->sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
101 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
102
103 if (dqm->dev->kfd->noretry)
104 qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
105
106 if (KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 3) ||
107 KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 4))
108 qpd->sh_mem_config |=
109 (1 << SH_MEM_CONFIG__F8_MODE__SHIFT);
110
111 qpd->sh_mem_ape1_limit = 0;
112 qpd->sh_mem_ape1_base = 0;
113 }
114
115 if (KFD_SUPPORT_XNACK_PER_PROCESS(dqm->dev)) {
116 if (!pdd->process->xnack_enabled)
117 qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
118 else
119 qpd->sh_mem_config &= ~(1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT);
120 }
121
122 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
123
124 pr_debug("sh_mem_bases 0x%X sh_mem_config 0x%X\n", qpd->sh_mem_bases,
125 qpd->sh_mem_config);
126
127 return 0;
128}
129
130static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
131 struct qcm_process_device *qpd)
132{
133 /* Not needed on SDMAv4 any more */
134 q->properties.sdma_vm_addr = 0;
135}