Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_MWAIT_H
3#define _ASM_X86_MWAIT_H
4
5#include <linux/sched.h>
6#include <linux/sched/idle.h>
7
8#include <asm/cpufeature.h>
9#include <asm/nospec-branch.h>
10
11#define MWAIT_SUBSTATE_MASK 0xf
12#define MWAIT_CSTATE_MASK 0xf
13#define MWAIT_SUBSTATE_SIZE 4
14#define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK)
15#define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK)
16#define MWAIT_C1_SUBSTATE_MASK 0xf0
17
18#define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
19#define CPUID5_ECX_INTERRUPT_BREAK 0x2
20
21#define MWAIT_ECX_INTERRUPT_BREAK 0x1
22#define MWAITX_ECX_TIMER_ENABLE BIT(1)
23#define MWAITX_MAX_WAIT_CYCLES UINT_MAX
24#define MWAITX_DISABLE_CSTATES 0xf0
25#define TPAUSE_C01_STATE 1
26#define TPAUSE_C02_STATE 0
27
28static __always_inline void __monitor(const void *eax, u32 ecx, u32 edx)
29{
30 /*
31 * Use the instruction mnemonic with implicit operands, as the LLVM
32 * assembler fails to assemble the mnemonic with explicit operands:
33 */
34 asm volatile("monitor" :: "a" (eax), "c" (ecx), "d" (edx));
35}
36
37static __always_inline void __monitorx(const void *eax, u32 ecx, u32 edx)
38{
39 /* "monitorx %eax, %ecx, %edx" */
40 asm volatile(".byte 0x0f, 0x01, 0xfa"
41 :: "a" (eax), "c" (ecx), "d"(edx));
42}
43
44static __always_inline void __mwait(u32 eax, u32 ecx)
45{
46 /*
47 * Use the instruction mnemonic with implicit operands, as the LLVM
48 * assembler fails to assemble the mnemonic with explicit operands:
49 */
50 asm volatile("mwait" :: "a" (eax), "c" (ecx));
51}
52
53/*
54 * MWAITX allows for a timer expiration to get the core out a wait state in
55 * addition to the default MWAIT exit condition of a store appearing at a
56 * monitored virtual address.
57 *
58 * Registers:
59 *
60 * MWAITX ECX[1]: enable timer if set
61 * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0
62 * frequency is the same as the TSC frequency.
63 *
64 * Below is a comparison between MWAIT and MWAITX on AMD processors:
65 *
66 * MWAIT MWAITX
67 * opcode 0f 01 c9 | 0f 01 fb
68 * ECX[0] value of RFLAGS.IF seen by instruction
69 * ECX[1] unused/#GP if set | enable timer if set
70 * ECX[31:2] unused/#GP if set
71 * EAX unused (reserve for hint)
72 * EBX[31:0] unused | max wait time (P0 clocks)
73 *
74 * MONITOR MONITORX
75 * opcode 0f 01 c8 | 0f 01 fa
76 * EAX (logical) address to monitor
77 * ECX #GP if not zero
78 */
79static __always_inline void __mwaitx(u32 eax, u32 ebx, u32 ecx)
80{
81 /* No need for TSA buffer clearing on AMD */
82
83 /* "mwaitx %eax, %ebx, %ecx" */
84 asm volatile(".byte 0x0f, 0x01, 0xfb"
85 :: "a" (eax), "b" (ebx), "c" (ecx));
86}
87
88/*
89 * Re-enable interrupts right upon calling mwait in such a way that
90 * no interrupt can fire _before_ the execution of mwait, ie: no
91 * instruction must be placed between "sti" and "mwait".
92 *
93 * This is necessary because if an interrupt queues a timer before
94 * executing mwait, it would otherwise go unnoticed and the next tick
95 * would not be reprogrammed accordingly before mwait ever wakes up.
96 */
97static __always_inline void __sti_mwait(u32 eax, u32 ecx)
98{
99
100 asm volatile("sti; mwait" :: "a" (eax), "c" (ecx));
101}
102
103/*
104 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
105 * which can obviate IPI to trigger checking of need_resched.
106 * We execute MONITOR against need_resched and enter optimized wait state
107 * through MWAIT. Whenever someone changes need_resched, we would be woken
108 * up from MWAIT (without an IPI).
109 *
110 * New with Core Duo processors, MWAIT can take some hints based on CPU
111 * capability.
112 */
113static __always_inline void mwait_idle_with_hints(u32 eax, u32 ecx)
114{
115 if (need_resched())
116 return;
117
118 x86_idle_clear_cpu_buffers();
119
120 if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test()) {
121 const void *addr = ¤t_thread_info()->flags;
122
123 alternative_input("", "clflush (%[addr])", X86_BUG_CLFLUSH_MONITOR, [addr] "a" (addr));
124 __monitor(addr, 0, 0);
125
126 if (need_resched())
127 goto out;
128
129 if (ecx & 1) {
130 __mwait(eax, ecx);
131 } else {
132 __sti_mwait(eax, ecx);
133 raw_local_irq_disable();
134 }
135 }
136
137out:
138 current_clr_polling();
139}
140
141/*
142 * Caller can specify whether to enter C0.1 (low latency, less
143 * power saving) or C0.2 state (saves more power, but longer wakeup
144 * latency). This may be overridden by the IA32_UMWAIT_CONTROL MSR
145 * which can force requests for C0.2 to be downgraded to C0.1.
146 */
147static inline void __tpause(u32 ecx, u32 edx, u32 eax)
148{
149 /* "tpause %ecx" */
150 asm volatile(".byte 0x66, 0x0f, 0xae, 0xf1"
151 :: "c" (ecx), "d" (edx), "a" (eax));
152}
153
154#endif /* _ASM_X86_MWAIT_H */